1 /* 2 * Copyright (C) 2011 Samsung Electronics 3 * Heungjun Kim <riverful.kim@samsung.com> 4 * Kyungmin Park <kyungmin.park@samsung.com> 5 * Donghwa Lee <dh09.lee@samsung.com> 6 * 7 * See file CREDITS for list of people who contributed to this 8 * project. 9 * 10 * This program is free software; you can redistribute it and/or 11 * modify it under the terms of the GNU General Public License as 12 * published by the Free Software Foundation; either version 2 of 13 * the License, or (at your option) any later version. 14 * 15 * This program is distributed in the hope that it will be useful, 16 * but WITHOUT ANY WARRANTY; without even the implied warranty of 17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 18 * GNU General Public License for more details. 19 * 20 * You should have received a copy of the GNU General Public License 21 * along with this program; if not, write to the Free Software 22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 23 * MA 02111-1307 USA 24 */ 25 26 #include <common.h> 27 #include <lcd.h> 28 #include <asm/io.h> 29 #include <asm/arch/cpu.h> 30 #include <asm/arch/gpio.h> 31 #include <asm/arch/mmc.h> 32 #include <asm/arch/clock.h> 33 #include <asm/arch/clk.h> 34 #include <asm/arch/mipi_dsim.h> 35 #include <asm/arch/watchdog.h> 36 #include <asm/arch/power.h> 37 #include <pmic.h> 38 #include <usb/s3c_udc.h> 39 #include <max8997_pmic.h> 40 #include <libtizen.h> 41 42 #include "setup.h" 43 44 DECLARE_GLOBAL_DATA_PTR; 45 46 unsigned int board_rev; 47 48 #ifdef CONFIG_REVISION_TAG 49 u32 get_board_rev(void) 50 { 51 return board_rev; 52 } 53 #endif 54 55 static void check_hw_revision(void); 56 57 static int hwrevision(int rev) 58 { 59 return (board_rev & 0xf) == rev; 60 } 61 62 int board_init(void) 63 { 64 gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100; 65 66 check_hw_revision(); 67 printf("HW Revision:\t0x%x\n", board_rev); 68 69 #if defined(CONFIG_PMIC) 70 pmic_init(); 71 #endif 72 73 return 0; 74 } 75 76 int dram_init(void) 77 { 78 gd->ram_size = get_ram_size((long *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE) + 79 get_ram_size((long *)PHYS_SDRAM_2, PHYS_SDRAM_2_SIZE); 80 81 return 0; 82 } 83 84 void dram_init_banksize(void) 85 { 86 gd->bd->bi_dram[0].start = PHYS_SDRAM_1; 87 gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; 88 gd->bd->bi_dram[1].start = PHYS_SDRAM_2; 89 gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE; 90 } 91 92 static unsigned int get_hw_revision(void) 93 { 94 struct exynos4_gpio_part1 *gpio = 95 (struct exynos4_gpio_part1 *)samsung_get_base_gpio_part1(); 96 int hwrev = 0; 97 int i; 98 99 /* hw_rev[3:0] == GPE1[3:0] */ 100 for (i = 0; i < 4; i++) { 101 s5p_gpio_cfg_pin(&gpio->e1, i, GPIO_INPUT); 102 s5p_gpio_set_pull(&gpio->e1, i, GPIO_PULL_NONE); 103 } 104 105 udelay(1); 106 107 for (i = 0; i < 4; i++) 108 hwrev |= (s5p_gpio_get_value(&gpio->e1, i) << i); 109 110 debug("hwrev 0x%x\n", hwrev); 111 112 return hwrev; 113 } 114 115 static void check_hw_revision(void) 116 { 117 int hwrev; 118 119 hwrev = get_hw_revision(); 120 121 board_rev |= hwrev; 122 } 123 124 #ifdef CONFIG_DISPLAY_BOARDINFO 125 int checkboard(void) 126 { 127 puts("Board:\tTRATS\n"); 128 return 0; 129 } 130 #endif 131 132 #ifdef CONFIG_GENERIC_MMC 133 int board_mmc_init(bd_t *bis) 134 { 135 struct exynos4_gpio_part2 *gpio = 136 (struct exynos4_gpio_part2 *)samsung_get_base_gpio_part2(); 137 int i, err; 138 139 /* eMMC_EN: SD_0_CDn: GPK0[2] Output High */ 140 s5p_gpio_direction_output(&gpio->k0, 2, 1); 141 s5p_gpio_set_pull(&gpio->k0, 2, GPIO_PULL_NONE); 142 143 /* 144 * eMMC GPIO: 145 * SDR 8-bit@48MHz at MMC0 146 * GPK0[0] SD_0_CLK(2) 147 * GPK0[1] SD_0_CMD(2) 148 * GPK0[2] SD_0_CDn -> Not used 149 * GPK0[3:6] SD_0_DATA[0:3](2) 150 * GPK1[3:6] SD_0_DATA[0:3](3) 151 * 152 * DDR 4-bit@26MHz at MMC4 153 * GPK0[0] SD_4_CLK(3) 154 * GPK0[1] SD_4_CMD(3) 155 * GPK0[2] SD_4_CDn -> Not used 156 * GPK0[3:6] SD_4_DATA[0:3](3) 157 * GPK1[3:6] SD_4_DATA[4:7](4) 158 */ 159 for (i = 0; i < 7; i++) { 160 if (i == 2) 161 continue; 162 /* GPK0[0:6] special function 2 */ 163 s5p_gpio_cfg_pin(&gpio->k0, i, 0x2); 164 /* GPK0[0:6] pull disable */ 165 s5p_gpio_set_pull(&gpio->k0, i, GPIO_PULL_NONE); 166 /* GPK0[0:6] drv 4x */ 167 s5p_gpio_set_drv(&gpio->k0, i, GPIO_DRV_4X); 168 } 169 170 for (i = 3; i < 7; i++) { 171 /* GPK1[3:6] special function 3 */ 172 s5p_gpio_cfg_pin(&gpio->k1, i, 0x3); 173 /* GPK1[3:6] pull disable */ 174 s5p_gpio_set_pull(&gpio->k1, i, GPIO_PULL_NONE); 175 /* GPK1[3:6] drv 4x */ 176 s5p_gpio_set_drv(&gpio->k1, i, GPIO_DRV_4X); 177 } 178 179 /* 180 * MMC device init 181 * mmc0 : eMMC (8-bit buswidth) 182 * mmc2 : SD card (4-bit buswidth) 183 */ 184 err = s5p_mmc_init(0, 8); 185 186 /* T-flash detect */ 187 s5p_gpio_cfg_pin(&gpio->x3, 4, 0xf); 188 s5p_gpio_set_pull(&gpio->x3, 4, GPIO_PULL_UP); 189 190 /* 191 * Check the T-flash detect pin 192 * GPX3[4] T-flash detect pin 193 */ 194 if (!s5p_gpio_get_value(&gpio->x3, 4)) { 195 /* 196 * SD card GPIO: 197 * GPK2[0] SD_2_CLK(2) 198 * GPK2[1] SD_2_CMD(2) 199 * GPK2[2] SD_2_CDn -> Not used 200 * GPK2[3:6] SD_2_DATA[0:3](2) 201 */ 202 for (i = 0; i < 7; i++) { 203 if (i == 2) 204 continue; 205 /* GPK2[0:6] special function 2 */ 206 s5p_gpio_cfg_pin(&gpio->k2, i, 0x2); 207 /* GPK2[0:6] pull disable */ 208 s5p_gpio_set_pull(&gpio->k2, i, GPIO_PULL_NONE); 209 /* GPK2[0:6] drv 4x */ 210 s5p_gpio_set_drv(&gpio->k2, i, GPIO_DRV_4X); 211 } 212 err = s5p_mmc_init(2, 4); 213 } 214 215 return err; 216 } 217 #endif 218 219 #ifdef CONFIG_USB_GADGET 220 static int s5pc210_phy_control(int on) 221 { 222 int ret = 0; 223 struct pmic *p = get_pmic(); 224 225 if (pmic_probe(p)) 226 return -1; 227 228 if (on) { 229 ret |= pmic_set_output(p, MAX8997_REG_SAFEOUTCTRL, 230 ENSAFEOUT1, LDO_ON); 231 ret |= pmic_reg_write(p, MAX8997_REG_LDO3CTRL, EN_LDO); 232 ret |= pmic_reg_write(p, MAX8997_REG_LDO8CTRL, EN_LDO); 233 } else { 234 ret |= pmic_reg_write(p, MAX8997_REG_LDO8CTRL, DIS_LDO); 235 ret |= pmic_reg_write(p, MAX8997_REG_LDO3CTRL, DIS_LDO); 236 ret |= pmic_set_output(p, MAX8997_REG_SAFEOUTCTRL, 237 ENSAFEOUT1, LDO_OFF); 238 } 239 240 if (ret) { 241 puts("MAX8997 LDO setting error!\n"); 242 return -1; 243 } 244 245 return 0; 246 } 247 248 struct s3c_plat_otg_data s5pc210_otg_data = { 249 .phy_control = s5pc210_phy_control, 250 .regs_phy = EXYNOS4_USBPHY_BASE, 251 .regs_otg = EXYNOS4_USBOTG_BASE, 252 .usb_phy_ctrl = EXYNOS4_USBPHY_CONTROL, 253 .usb_flags = PHY0_SLEEP, 254 }; 255 #endif 256 257 static void pmic_reset(void) 258 { 259 struct exynos4_gpio_part2 *gpio = 260 (struct exynos4_gpio_part2 *)samsung_get_base_gpio_part2(); 261 262 s5p_gpio_direction_output(&gpio->x0, 7, 1); 263 s5p_gpio_set_pull(&gpio->x2, 7, GPIO_PULL_NONE); 264 } 265 266 static void board_clock_init(void) 267 { 268 struct exynos4_clock *clk = 269 (struct exynos4_clock *)samsung_get_base_clock(); 270 271 writel(CLK_SRC_CPU_VAL, (unsigned int)&clk->src_cpu); 272 writel(CLK_SRC_TOP0_VAL, (unsigned int)&clk->src_top0); 273 writel(CLK_SRC_FSYS_VAL, (unsigned int)&clk->src_fsys); 274 writel(CLK_SRC_PERIL0_VAL, (unsigned int)&clk->src_peril0); 275 276 writel(CLK_DIV_CPU0_VAL, (unsigned int)&clk->div_cpu0); 277 writel(CLK_DIV_CPU1_VAL, (unsigned int)&clk->div_cpu1); 278 writel(CLK_DIV_DMC0_VAL, (unsigned int)&clk->div_dmc0); 279 writel(CLK_DIV_DMC1_VAL, (unsigned int)&clk->div_dmc1); 280 writel(CLK_DIV_LEFTBUS_VAL, (unsigned int)&clk->div_leftbus); 281 writel(CLK_DIV_RIGHTBUS_VAL, (unsigned int)&clk->div_rightbus); 282 writel(CLK_DIV_TOP_VAL, (unsigned int)&clk->div_top); 283 writel(CLK_DIV_FSYS1_VAL, (unsigned int)&clk->div_fsys1); 284 writel(CLK_DIV_FSYS2_VAL, (unsigned int)&clk->div_fsys2); 285 writel(CLK_DIV_FSYS3_VAL, (unsigned int)&clk->div_fsys3); 286 writel(CLK_DIV_PERIL0_VAL, (unsigned int)&clk->div_peril0); 287 writel(CLK_DIV_PERIL3_VAL, (unsigned int)&clk->div_peril3); 288 289 writel(PLL_LOCKTIME, (unsigned int)&clk->apll_lock); 290 writel(PLL_LOCKTIME, (unsigned int)&clk->mpll_lock); 291 writel(PLL_LOCKTIME, (unsigned int)&clk->epll_lock); 292 writel(PLL_LOCKTIME, (unsigned int)&clk->vpll_lock); 293 writel(APLL_CON1_VAL, (unsigned int)&clk->apll_con1); 294 writel(APLL_CON0_VAL, (unsigned int)&clk->apll_con0); 295 writel(MPLL_CON1_VAL, (unsigned int)&clk->mpll_con1); 296 writel(MPLL_CON0_VAL, (unsigned int)&clk->mpll_con0); 297 writel(EPLL_CON1_VAL, (unsigned int)&clk->epll_con1); 298 writel(EPLL_CON0_VAL, (unsigned int)&clk->epll_con0); 299 writel(VPLL_CON1_VAL, (unsigned int)&clk->vpll_con1); 300 writel(VPLL_CON0_VAL, (unsigned int)&clk->vpll_con0); 301 302 writel(CLK_GATE_IP_CAM_VAL, (unsigned int)&clk->gate_ip_cam); 303 writel(CLK_GATE_IP_VP_VAL, (unsigned int)&clk->gate_ip_tv); 304 writel(CLK_GATE_IP_MFC_VAL, (unsigned int)&clk->gate_ip_mfc); 305 writel(CLK_GATE_IP_G3D_VAL, (unsigned int)&clk->gate_ip_g3d); 306 writel(CLK_GATE_IP_IMAGE_VAL, (unsigned int)&clk->gate_ip_image); 307 writel(CLK_GATE_IP_LCD0_VAL, (unsigned int)&clk->gate_ip_lcd0); 308 writel(CLK_GATE_IP_LCD1_VAL, (unsigned int)&clk->gate_ip_lcd1); 309 writel(CLK_GATE_IP_FSYS_VAL, (unsigned int)&clk->gate_ip_fsys); 310 writel(CLK_GATE_IP_GPS_VAL, (unsigned int)&clk->gate_ip_gps); 311 writel(CLK_GATE_IP_PERIL_VAL, (unsigned int)&clk->gate_ip_peril); 312 writel(CLK_GATE_IP_PERIR_VAL, (unsigned int)&clk->gate_ip_perir); 313 writel(CLK_GATE_BLOCK_VAL, (unsigned int)&clk->gate_block); 314 } 315 316 static void board_power_init(void) 317 { 318 struct exynos4_power *pwr = 319 (struct exynos4_power *)samsung_get_base_power(); 320 321 /* PS HOLD */ 322 writel(EXYNOS4_PS_HOLD_CON_VAL, (unsigned int)&pwr->ps_hold_control); 323 324 /* Set power down */ 325 writel(0, (unsigned int)&pwr->cam_configuration); 326 writel(0, (unsigned int)&pwr->tv_configuration); 327 writel(0, (unsigned int)&pwr->mfc_configuration); 328 writel(0, (unsigned int)&pwr->g3d_configuration); 329 writel(0, (unsigned int)&pwr->lcd1_configuration); 330 writel(0, (unsigned int)&pwr->gps_configuration); 331 writel(0, (unsigned int)&pwr->gps_alive_configuration); 332 } 333 334 static void board_uart_init(void) 335 { 336 struct exynos4_gpio_part1 *gpio1 = 337 (struct exynos4_gpio_part1 *)samsung_get_base_gpio_part1(); 338 struct exynos4_gpio_part2 *gpio2 = 339 (struct exynos4_gpio_part2 *)samsung_get_base_gpio_part2(); 340 int i; 341 342 /* 343 * UART2 GPIOs 344 * GPA1CON[0] = UART_2_RXD(2) 345 * GPA1CON[1] = UART_2_TXD(2) 346 * GPA1CON[2] = I2C_3_SDA (3) 347 * GPA1CON[3] = I2C_3_SCL (3) 348 */ 349 350 for (i = 0; i < 4; i++) { 351 s5p_gpio_set_pull(&gpio1->a1, i, GPIO_PULL_NONE); 352 s5p_gpio_cfg_pin(&gpio1->a1, i, GPIO_FUNC((i > 1) ? 0x3 : 0x2)); 353 } 354 355 /* UART_SEL GPY4[7] (part2) at EXYNOS4 */ 356 s5p_gpio_set_pull(&gpio2->y4, 7, GPIO_PULL_UP); 357 s5p_gpio_direction_output(&gpio2->y4, 7, 1); 358 } 359 360 int board_early_init_f(void) 361 { 362 wdt_stop(); 363 pmic_reset(); 364 board_clock_init(); 365 board_uart_init(); 366 board_power_init(); 367 368 return 0; 369 } 370 371 static void lcd_reset(void) 372 { 373 struct exynos4_gpio_part2 *gpio2 = 374 (struct exynos4_gpio_part2 *)samsung_get_base_gpio_part2(); 375 376 s5p_gpio_direction_output(&gpio2->y4, 5, 1); 377 udelay(10000); 378 s5p_gpio_direction_output(&gpio2->y4, 5, 0); 379 udelay(10000); 380 s5p_gpio_direction_output(&gpio2->y4, 5, 1); 381 } 382 383 static int lcd_power(void) 384 { 385 int ret = 0; 386 struct pmic *p = get_pmic(); 387 388 if (pmic_probe(p)) 389 return 0; 390 391 /* LDO15 voltage: 2.2v */ 392 ret |= pmic_reg_write(p, MAX8997_REG_LDO15CTRL, 0x1c | EN_LDO); 393 /* LDO13 voltage: 3.0v */ 394 ret |= pmic_reg_write(p, MAX8997_REG_LDO13CTRL, 0x2c | EN_LDO); 395 396 if (ret) { 397 puts("MAX8997 LDO setting error!\n"); 398 return -1; 399 } 400 401 return 0; 402 } 403 404 static struct mipi_dsim_config dsim_config = { 405 .e_interface = DSIM_VIDEO, 406 .e_virtual_ch = DSIM_VIRTUAL_CH_0, 407 .e_pixel_format = DSIM_24BPP_888, 408 .e_burst_mode = DSIM_BURST_SYNC_EVENT, 409 .e_no_data_lane = DSIM_DATA_LANE_4, 410 .e_byte_clk = DSIM_PLL_OUT_DIV8, 411 .hfp = 1, 412 413 .p = 3, 414 .m = 120, 415 .s = 1, 416 417 /* D-PHY PLL stable time spec :min = 200usec ~ max 400usec */ 418 .pll_stable_time = 500, 419 420 /* escape clk : 10MHz */ 421 .esc_clk = 20 * 1000000, 422 423 /* stop state holding counter after bta change count 0 ~ 0xfff */ 424 .stop_holding_cnt = 0x7ff, 425 /* bta timeout 0 ~ 0xff */ 426 .bta_timeout = 0xff, 427 /* lp rx timeout 0 ~ 0xffff */ 428 .rx_timeout = 0xffff, 429 }; 430 431 static struct exynos_platform_mipi_dsim s6e8ax0_platform_data = { 432 .lcd_panel_info = NULL, 433 .dsim_config = &dsim_config, 434 }; 435 436 static struct mipi_dsim_lcd_device mipi_lcd_device = { 437 .name = "s6e8ax0", 438 .id = -1, 439 .bus_id = 0, 440 .platform_data = (void *)&s6e8ax0_platform_data, 441 }; 442 443 static int mipi_power(void) 444 { 445 int ret = 0; 446 struct pmic *p = get_pmic(); 447 448 if (pmic_probe(p)) 449 return 0; 450 451 /* LDO3 voltage: 1.1v */ 452 ret |= pmic_reg_write(p, MAX8997_REG_LDO3CTRL, 0x6 | EN_LDO); 453 /* LDO4 voltage: 1.8v */ 454 ret |= pmic_reg_write(p, MAX8997_REG_LDO4CTRL, 0x14 | EN_LDO); 455 456 if (ret) { 457 puts("MAX8997 LDO setting error!\n"); 458 return -1; 459 } 460 461 return 0; 462 } 463 464 void init_panel_info(vidinfo_t *vid) 465 { 466 vid->vl_freq = 60; 467 vid->vl_col = 720; 468 vid->vl_row = 1280; 469 vid->vl_width = 720; 470 vid->vl_height = 1280; 471 vid->vl_clkp = CONFIG_SYS_HIGH; 472 vid->vl_hsp = CONFIG_SYS_LOW; 473 vid->vl_vsp = CONFIG_SYS_LOW; 474 vid->vl_dp = CONFIG_SYS_LOW; 475 476 vid->vl_bpix = 5; 477 vid->dual_lcd_enabled = 0; 478 479 /* s6e8ax0 Panel */ 480 vid->vl_hspw = 5; 481 vid->vl_hbpd = 10; 482 vid->vl_hfpd = 10; 483 484 vid->vl_vspw = 2; 485 vid->vl_vbpd = 1; 486 vid->vl_vfpd = 13; 487 vid->vl_cmd_allow_len = 0xf; 488 489 vid->win_id = 3; 490 vid->cfg_gpio = NULL; 491 vid->backlight_on = NULL; 492 vid->lcd_power_on = NULL; /* lcd_power_on in mipi dsi driver */ 493 vid->reset_lcd = lcd_reset; 494 495 vid->init_delay = 0; 496 vid->power_on_delay = 0; 497 vid->reset_delay = 0; 498 vid->interface_mode = FIMD_RGB_INTERFACE; 499 vid->mipi_enabled = 1; 500 vid->logo_on = 1, 501 vid->resolution = HD_RESOLUTION, 502 vid->rgb_mode = MODE_RGB_P, 503 504 #ifdef CONFIG_TIZEN 505 get_tizen_logo_info(vid); 506 #endif 507 508 if (hwrevision(2)) 509 mipi_lcd_device.reverse_panel = 1; 510 511 strcpy(s6e8ax0_platform_data.lcd_panel_name, mipi_lcd_device.name); 512 s6e8ax0_platform_data.lcd_power = lcd_power; 513 s6e8ax0_platform_data.mipi_power = mipi_power; 514 s6e8ax0_platform_data.phy_enable = set_mipi_phy_ctrl; 515 s6e8ax0_platform_data.lcd_panel_info = (void *)vid; 516 exynos_mipi_dsi_register_lcd_device(&mipi_lcd_device); 517 s6e8ax0_init(); 518 exynos_set_dsim_platform_data(&s6e8ax0_platform_data); 519 520 setenv("lcdinfo", "lcd=s6e8ax0"); 521 } 522