1 /* 2 * Copyright (C) 2011 Samsung Electronics 3 * Heungjun Kim <riverful.kim@samsung.com> 4 * Kyungmin Park <kyungmin.park@samsung.com> 5 * Donghwa Lee <dh09.lee@samsung.com> 6 * 7 * See file CREDITS for list of people who contributed to this 8 * project. 9 * 10 * This program is free software; you can redistribute it and/or 11 * modify it under the terms of the GNU General Public License as 12 * published by the Free Software Foundation; either version 2 of 13 * the License, or (at your option) any later version. 14 * 15 * This program is distributed in the hope that it will be useful, 16 * but WITHOUT ANY WARRANTY; without even the implied warranty of 17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 18 * GNU General Public License for more details. 19 * 20 * You should have received a copy of the GNU General Public License 21 * along with this program; if not, write to the Free Software 22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 23 * MA 02111-1307 USA 24 */ 25 26 #include <common.h> 27 #include <lcd.h> 28 #include <asm/io.h> 29 #include <asm/arch/cpu.h> 30 #include <asm/arch/gpio.h> 31 #include <asm/arch/mmc.h> 32 #include <asm/arch/pinmux.h> 33 #include <asm/arch/clock.h> 34 #include <asm/arch/clk.h> 35 #include <asm/arch/mipi_dsim.h> 36 #include <asm/arch/watchdog.h> 37 #include <asm/arch/power.h> 38 #include <power/pmic.h> 39 #include <usb/s3c_udc.h> 40 #include <power/max8997_pmic.h> 41 #include <libtizen.h> 42 #include <power/max8997_muic.h> 43 #include <power/battery.h> 44 #include <power/max17042_fg.h> 45 46 #include "setup.h" 47 48 DECLARE_GLOBAL_DATA_PTR; 49 50 unsigned int board_rev; 51 52 #ifdef CONFIG_REVISION_TAG 53 u32 get_board_rev(void) 54 { 55 return board_rev; 56 } 57 #endif 58 59 static void check_hw_revision(void); 60 61 static int hwrevision(int rev) 62 { 63 return (board_rev & 0xf) == rev; 64 } 65 66 struct s3c_plat_otg_data s5pc210_otg_data; 67 68 int board_init(void) 69 { 70 gd->bd->bi_boot_params = CONFIG_SYS_SPL_ARGS_ADDR; 71 72 check_hw_revision(); 73 printf("HW Revision:\t0x%x\n", board_rev); 74 75 return 0; 76 } 77 78 void i2c_init_board(void) 79 { 80 struct exynos4_gpio_part1 *gpio1 = 81 (struct exynos4_gpio_part1 *)samsung_get_base_gpio_part1(); 82 struct exynos4_gpio_part2 *gpio2 = 83 (struct exynos4_gpio_part2 *)samsung_get_base_gpio_part2(); 84 85 /* I2C_5 -> PMIC */ 86 s5p_gpio_direction_output(&gpio1->b, 7, 1); 87 s5p_gpio_direction_output(&gpio1->b, 6, 1); 88 /* I2C_9 -> FG */ 89 s5p_gpio_direction_output(&gpio2->y4, 0, 1); 90 s5p_gpio_direction_output(&gpio2->y4, 1, 1); 91 } 92 93 static void trats_low_power_mode(void) 94 { 95 struct exynos4_clock *clk = 96 (struct exynos4_clock *)samsung_get_base_clock(); 97 struct exynos4_power *pwr = 98 (struct exynos4_power *)samsung_get_base_power(); 99 100 /* Power down CORE1 */ 101 /* LOCAL_PWR_CFG [1:0] 0x3 EN, 0x0 DIS */ 102 writel(0x0, &pwr->arm_core1_configuration); 103 104 /* Change the APLL frequency */ 105 /* ENABLE (1 enable) | LOCKED (1 locked) */ 106 /* [31] | [29] */ 107 /* FSEL | MDIV | PDIV | SDIV */ 108 /* [27] | [25:16] | [13:8] | [2:0] */ 109 writel(0xa0c80604, &clk->apll_con0); 110 111 /* Change CPU0 clock divider */ 112 /* CORE2_RATIO | APLL_RATIO | PCLK_DBG_RATIO | ATB_RATIO */ 113 /* [30:28] | [26:24] | [22:20] | [18:16] */ 114 /* PERIPH_RATIO | COREM1_RATIO | COREM0_RATIO | CORE_RATIO */ 115 /* [14:12] | [10:8] | [6:4] | [2:0] */ 116 writel(0x00000100, &clk->div_cpu0); 117 118 /* CLK_DIV_STAT_CPU0 - wait until clock gets stable (0 = stable) */ 119 while (readl(&clk->div_stat_cpu0) & 0x1111111) 120 continue; 121 122 /* Change clock divider ratio for DMC */ 123 /* DMCP_RATIO | DMCD_RATIO */ 124 /* [22:20] | [18:16] */ 125 /* DMC_RATIO | DPHY_RATIO | ACP_PCLK_RATIO | ACP_RATIO */ 126 /* [14:12] | [10:8] | [6:4] | [2:0] */ 127 writel(0x13113117, &clk->div_dmc0); 128 129 /* CLK_DIV_STAT_DMC0 - wait until clock gets stable (0 = stable) */ 130 while (readl(&clk->div_stat_dmc0) & 0x11111111) 131 continue; 132 133 /* Turn off unnecessary power domains */ 134 writel(0x0, &pwr->xxti_configuration); /* XXTI */ 135 writel(0x0, &pwr->cam_configuration); /* CAM */ 136 writel(0x0, &pwr->tv_configuration); /* TV */ 137 writel(0x0, &pwr->mfc_configuration); /* MFC */ 138 writel(0x0, &pwr->g3d_configuration); /* G3D */ 139 writel(0x0, &pwr->gps_configuration); /* GPS */ 140 writel(0x0, &pwr->gps_alive_configuration); /* GPS_ALIVE */ 141 142 /* Turn off unnecessary clocks */ 143 writel(0x0, &clk->gate_ip_cam); /* CAM */ 144 writel(0x0, &clk->gate_ip_tv); /* TV */ 145 writel(0x0, &clk->gate_ip_mfc); /* MFC */ 146 writel(0x0, &clk->gate_ip_g3d); /* G3D */ 147 writel(0x0, &clk->gate_ip_image); /* IMAGE */ 148 writel(0x0, &clk->gate_ip_gps); /* GPS */ 149 } 150 151 static int pmic_init_max8997(void) 152 { 153 struct pmic *p = pmic_get("MAX8997_PMIC"); 154 int i = 0, ret = 0; 155 u32 val; 156 157 if (pmic_probe(p)) 158 return -1; 159 160 /* BUCK1 VARM: 1.2V */ 161 val = (1200000 - 650000) / 25000; 162 ret |= pmic_reg_write(p, MAX8997_REG_BUCK1DVS1, val); 163 val = ENBUCK | ACTIVE_DISCHARGE; /* DVS OFF */ 164 ret |= pmic_reg_write(p, MAX8997_REG_BUCK1CTRL, val); 165 166 /* BUCK2 VINT: 1.1V */ 167 val = (1100000 - 650000) / 25000; 168 ret |= pmic_reg_write(p, MAX8997_REG_BUCK2DVS1, val); 169 val = ENBUCK | ACTIVE_DISCHARGE; /* DVS OFF */ 170 ret |= pmic_reg_write(p, MAX8997_REG_BUCK2CTRL, val); 171 172 173 /* BUCK3 G3D: 1.1V - OFF */ 174 ret |= pmic_reg_read(p, MAX8997_REG_BUCK3CTRL, &val); 175 val &= ~ENBUCK; 176 ret |= pmic_reg_write(p, MAX8997_REG_BUCK3CTRL, val); 177 178 val = (1100000 - 750000) / 50000; 179 ret |= pmic_reg_write(p, MAX8997_REG_BUCK3DVS, val); 180 181 /* BUCK4 CAMISP: 1.2V - OFF */ 182 ret |= pmic_reg_read(p, MAX8997_REG_BUCK4CTRL, &val); 183 val &= ~ENBUCK; 184 ret |= pmic_reg_write(p, MAX8997_REG_BUCK4CTRL, val); 185 186 val = (1200000 - 650000) / 25000; 187 ret |= pmic_reg_write(p, MAX8997_REG_BUCK4DVS, val); 188 189 /* BUCK5 VMEM: 1.2V */ 190 val = (1200000 - 650000) / 25000; 191 for (i = 0; i < 8; i++) 192 ret |= pmic_reg_write(p, MAX8997_REG_BUCK5DVS1 + i, val); 193 194 val = ENBUCK | ACTIVE_DISCHARGE; /* DVS OFF */ 195 ret |= pmic_reg_write(p, MAX8997_REG_BUCK5CTRL, val); 196 197 /* BUCK6 CAM AF: 2.8V */ 198 /* No Voltage Setting Register */ 199 /* GNSLCT 3.0X */ 200 val = GNSLCT; 201 ret |= pmic_reg_write(p, MAX8997_REG_BUCK6CTRL, val); 202 203 /* BUCK7 VCC_SUB: 2.0V */ 204 val = (2000000 - 750000) / 50000; 205 ret |= pmic_reg_write(p, MAX8997_REG_BUCK7DVS, val); 206 207 /* LDO1 VADC: 3.3V */ 208 val = max8997_reg_ldo(3300000) | DIS_LDO; /* OFF */ 209 ret |= pmic_reg_write(p, MAX8997_REG_LDO1CTRL, val); 210 211 /* LDO1 Disable active discharging */ 212 ret |= pmic_reg_read(p, MAX8997_REG_LDO1CONFIG, &val); 213 val &= ~LDO_ADE; 214 ret |= pmic_reg_write(p, MAX8997_REG_LDO1CONFIG, val); 215 216 /* LDO2 VALIVE: 1.1V */ 217 val = max8997_reg_ldo(1100000) | EN_LDO; 218 ret |= pmic_reg_write(p, MAX8997_REG_LDO2CTRL, val); 219 220 /* LDO3 VUSB/MIPI: 1.1V */ 221 val = max8997_reg_ldo(1100000) | DIS_LDO; /* OFF */ 222 ret |= pmic_reg_write(p, MAX8997_REG_LDO3CTRL, val); 223 224 /* LDO4 VMIPI: 1.8V */ 225 val = max8997_reg_ldo(1800000) | DIS_LDO; /* OFF */ 226 ret |= pmic_reg_write(p, MAX8997_REG_LDO4CTRL, val); 227 228 /* LDO5 VHSIC: 1.2V */ 229 val = max8997_reg_ldo(1200000) | DIS_LDO; /* OFF */ 230 ret |= pmic_reg_write(p, MAX8997_REG_LDO5CTRL, val); 231 232 /* LDO6 VCC_1.8V_PDA: 1.8V */ 233 val = max8997_reg_ldo(1800000) | EN_LDO; 234 ret |= pmic_reg_write(p, MAX8997_REG_LDO6CTRL, val); 235 236 /* LDO7 CAM_ISP: 1.8V */ 237 val = max8997_reg_ldo(1800000) | DIS_LDO; /* OFF */ 238 ret |= pmic_reg_write(p, MAX8997_REG_LDO7CTRL, val); 239 240 /* LDO8 VDAC/VUSB: 3.3V */ 241 val = max8997_reg_ldo(3300000) | DIS_LDO; /* OFF */ 242 ret |= pmic_reg_write(p, MAX8997_REG_LDO8CTRL, val); 243 244 /* LDO9 VCC_2.8V_PDA: 2.8V */ 245 val = max8997_reg_ldo(2800000) | EN_LDO; 246 ret |= pmic_reg_write(p, MAX8997_REG_LDO9CTRL, val); 247 248 /* LDO10 VPLL: 1.1V */ 249 val = max8997_reg_ldo(1100000) | EN_LDO; 250 ret |= pmic_reg_write(p, MAX8997_REG_LDO10CTRL, val); 251 252 /* LDO11 TOUCH: 2.8V */ 253 val = max8997_reg_ldo(2800000) | DIS_LDO; /* OFF */ 254 ret |= pmic_reg_write(p, MAX8997_REG_LDO11CTRL, val); 255 256 /* LDO12 VTCAM: 1.8V */ 257 val = max8997_reg_ldo(1800000) | DIS_LDO; /* OFF */ 258 ret |= pmic_reg_write(p, MAX8997_REG_LDO12CTRL, val); 259 260 /* LDO13 VCC_3.0_LCD: 3.0V */ 261 val = max8997_reg_ldo(3000000) | DIS_LDO; /* OFF */ 262 ret |= pmic_reg_write(p, MAX8997_REG_LDO13CTRL, val); 263 264 /* LDO14 MOTOR: 3.0V */ 265 val = max8997_reg_ldo(3000000) | DIS_LDO; /* OFF */ 266 ret |= pmic_reg_write(p, MAX8997_REG_LDO14CTRL, val); 267 268 /* LDO15 LED_A: 2.8V */ 269 val = max8997_reg_ldo(2800000) | DIS_LDO; /* OFF */ 270 ret |= pmic_reg_write(p, MAX8997_REG_LDO15CTRL, val); 271 272 /* LDO16 CAM_SENSOR: 1.8V */ 273 val = max8997_reg_ldo(1800000) | DIS_LDO; /* OFF */ 274 ret |= pmic_reg_write(p, MAX8997_REG_LDO16CTRL, val); 275 276 /* LDO17 VTF: 2.8V */ 277 val = max8997_reg_ldo(2800000) | DIS_LDO; /* OFF */ 278 ret |= pmic_reg_write(p, MAX8997_REG_LDO17CTRL, val); 279 280 /* LDO18 TOUCH_LED 3.3V */ 281 val = max8997_reg_ldo(3300000) | DIS_LDO; /* OFF */ 282 ret |= pmic_reg_write(p, MAX8997_REG_LDO18CTRL, val); 283 284 /* LDO21 VDDQ: 1.2V */ 285 val = max8997_reg_ldo(1200000) | EN_LDO; 286 ret |= pmic_reg_write(p, MAX8997_REG_LDO21CTRL, val); 287 288 /* SAFEOUT for both 1 and 2: 4.9V, Active discharge, Enable */ 289 val = (SAFEOUT_4_90V << 0) | (SAFEOUT_4_90V << 2) | 290 ACTDISSAFEO1 | ACTDISSAFEO2 | ENSAFEOUT1 | ENSAFEOUT2; 291 ret |= pmic_reg_write(p, MAX8997_REG_SAFEOUTCTRL, val); 292 293 if (ret) { 294 puts("MAX8997 PMIC setting error!\n"); 295 return -1; 296 } 297 return 0; 298 } 299 300 int power_init_board(void) 301 { 302 int chrg, ret; 303 struct power_battery *pb; 304 struct pmic *p_fg, *p_chrg, *p_muic, *p_bat; 305 306 ret = pmic_init(I2C_5); 307 ret |= pmic_init_max8997(); 308 ret |= power_fg_init(I2C_9); 309 ret |= power_muic_init(I2C_5); 310 ret |= power_bat_init(0); 311 if (ret) 312 return ret; 313 314 p_fg = pmic_get("MAX17042_FG"); 315 if (!p_fg) { 316 puts("MAX17042_FG: Not found\n"); 317 return -ENODEV; 318 } 319 320 p_chrg = pmic_get("MAX8997_PMIC"); 321 if (!p_chrg) { 322 puts("MAX8997_PMIC: Not found\n"); 323 return -ENODEV; 324 } 325 326 p_muic = pmic_get("MAX8997_MUIC"); 327 if (!p_muic) { 328 puts("MAX8997_MUIC: Not found\n"); 329 return -ENODEV; 330 } 331 332 p_bat = pmic_get("BAT_TRATS"); 333 if (!p_bat) { 334 puts("BAT_TRATS: Not found\n"); 335 return -ENODEV; 336 } 337 338 p_fg->parent = p_bat; 339 p_chrg->parent = p_bat; 340 p_muic->parent = p_bat; 341 342 p_bat->low_power_mode = trats_low_power_mode; 343 p_bat->pbat->battery_init(p_bat, p_fg, p_chrg, p_muic); 344 345 pb = p_bat->pbat; 346 chrg = p_muic->chrg->chrg_type(p_muic); 347 debug("CHARGER TYPE: %d\n", chrg); 348 349 if (!p_chrg->chrg->chrg_bat_present(p_chrg)) { 350 puts("No battery detected\n"); 351 return -1; 352 } 353 354 p_fg->fg->fg_battery_check(p_fg, p_bat); 355 356 if (pb->bat->state == CHARGE && chrg == CHARGER_USB) 357 puts("CHARGE Battery !\n"); 358 359 return 0; 360 } 361 362 int dram_init(void) 363 { 364 gd->ram_size = get_ram_size((long *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE) + 365 get_ram_size((long *)PHYS_SDRAM_2, PHYS_SDRAM_2_SIZE) + 366 get_ram_size((long *)PHYS_SDRAM_3, PHYS_SDRAM_3_SIZE) + 367 get_ram_size((long *)PHYS_SDRAM_4, PHYS_SDRAM_4_SIZE); 368 369 return 0; 370 } 371 372 void dram_init_banksize(void) 373 { 374 gd->bd->bi_dram[0].start = PHYS_SDRAM_1; 375 gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; 376 gd->bd->bi_dram[1].start = PHYS_SDRAM_2; 377 gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE; 378 gd->bd->bi_dram[2].start = PHYS_SDRAM_3; 379 gd->bd->bi_dram[2].size = PHYS_SDRAM_3_SIZE; 380 gd->bd->bi_dram[3].start = PHYS_SDRAM_4; 381 gd->bd->bi_dram[3].size = PHYS_SDRAM_4_SIZE; 382 } 383 384 static unsigned int get_hw_revision(void) 385 { 386 struct exynos4_gpio_part1 *gpio = 387 (struct exynos4_gpio_part1 *)samsung_get_base_gpio_part1(); 388 int hwrev = 0; 389 int i; 390 391 /* hw_rev[3:0] == GPE1[3:0] */ 392 for (i = 0; i < 4; i++) { 393 s5p_gpio_cfg_pin(&gpio->e1, i, GPIO_INPUT); 394 s5p_gpio_set_pull(&gpio->e1, i, GPIO_PULL_NONE); 395 } 396 397 udelay(1); 398 399 for (i = 0; i < 4; i++) 400 hwrev |= (s5p_gpio_get_value(&gpio->e1, i) << i); 401 402 debug("hwrev 0x%x\n", hwrev); 403 404 return hwrev; 405 } 406 407 static void check_hw_revision(void) 408 { 409 int hwrev; 410 411 hwrev = get_hw_revision(); 412 413 board_rev |= hwrev; 414 } 415 416 #ifdef CONFIG_DISPLAY_BOARDINFO 417 int checkboard(void) 418 { 419 puts("Board:\tTRATS\n"); 420 return 0; 421 } 422 #endif 423 424 #ifdef CONFIG_GENERIC_MMC 425 int board_mmc_init(bd_t *bis) 426 { 427 struct exynos4_gpio_part2 *gpio = 428 (struct exynos4_gpio_part2 *)samsung_get_base_gpio_part2(); 429 int err; 430 431 /* eMMC_EN: SD_0_CDn: GPK0[2] Output High */ 432 s5p_gpio_direction_output(&gpio->k0, 2, 1); 433 s5p_gpio_set_pull(&gpio->k0, 2, GPIO_PULL_NONE); 434 435 /* 436 * MMC device init 437 * mmc0 : eMMC (8-bit buswidth) 438 * mmc2 : SD card (4-bit buswidth) 439 */ 440 err = exynos_pinmux_config(PERIPH_ID_SDMMC0, PINMUX_FLAG_8BIT_MODE); 441 if (err) 442 debug("SDMMC0 not configured\n"); 443 else 444 err = s5p_mmc_init(0, 8); 445 446 /* T-flash detect */ 447 s5p_gpio_cfg_pin(&gpio->x3, 4, 0xf); 448 s5p_gpio_set_pull(&gpio->x3, 4, GPIO_PULL_UP); 449 450 /* 451 * Check the T-flash detect pin 452 * GPX3[4] T-flash detect pin 453 */ 454 if (!s5p_gpio_get_value(&gpio->x3, 4)) { 455 err = exynos_pinmux_config(PERIPH_ID_SDMMC2, PINMUX_FLAG_NONE); 456 if (err) 457 debug("SDMMC2 not configured\n"); 458 else 459 err = s5p_mmc_init(2, 4); 460 } 461 462 return err; 463 } 464 #endif 465 466 #ifdef CONFIG_USB_GADGET 467 static int s5pc210_phy_control(int on) 468 { 469 int ret = 0; 470 u32 val = 0; 471 struct pmic *p = pmic_get("MAX8997_PMIC"); 472 if (!p) 473 return -ENODEV; 474 475 if (pmic_probe(p)) 476 return -1; 477 478 if (on) { 479 ret |= pmic_set_output(p, MAX8997_REG_SAFEOUTCTRL, 480 ENSAFEOUT1, LDO_ON); 481 ret |= pmic_reg_read(p, MAX8997_REG_LDO3CTRL, &val); 482 ret |= pmic_reg_write(p, MAX8997_REG_LDO3CTRL, EN_LDO | val); 483 484 ret |= pmic_reg_read(p, MAX8997_REG_LDO8CTRL, &val); 485 ret |= pmic_reg_write(p, MAX8997_REG_LDO8CTRL, EN_LDO | val); 486 } else { 487 ret |= pmic_reg_read(p, MAX8997_REG_LDO8CTRL, &val); 488 ret |= pmic_reg_write(p, MAX8997_REG_LDO8CTRL, DIS_LDO | val); 489 490 ret |= pmic_reg_read(p, MAX8997_REG_LDO3CTRL, &val); 491 ret |= pmic_reg_write(p, MAX8997_REG_LDO3CTRL, DIS_LDO | val); 492 ret |= pmic_set_output(p, MAX8997_REG_SAFEOUTCTRL, 493 ENSAFEOUT1, LDO_OFF); 494 } 495 496 if (ret) { 497 puts("MAX8997 LDO setting error!\n"); 498 return -1; 499 } 500 501 return 0; 502 } 503 504 struct s3c_plat_otg_data s5pc210_otg_data = { 505 .phy_control = s5pc210_phy_control, 506 .regs_phy = EXYNOS4_USBPHY_BASE, 507 .regs_otg = EXYNOS4_USBOTG_BASE, 508 .usb_phy_ctrl = EXYNOS4_USBPHY_CONTROL, 509 .usb_flags = PHY0_SLEEP, 510 }; 511 512 void board_usb_init(void) 513 { 514 debug("USB_udc_probe\n"); 515 s3c_udc_probe(&s5pc210_otg_data); 516 } 517 #endif 518 519 static void pmic_reset(void) 520 { 521 struct exynos4_gpio_part2 *gpio = 522 (struct exynos4_gpio_part2 *)samsung_get_base_gpio_part2(); 523 524 s5p_gpio_direction_output(&gpio->x0, 7, 1); 525 s5p_gpio_set_pull(&gpio->x2, 7, GPIO_PULL_NONE); 526 } 527 528 static void board_clock_init(void) 529 { 530 struct exynos4_clock *clk = 531 (struct exynos4_clock *)samsung_get_base_clock(); 532 533 writel(CLK_SRC_CPU_VAL, (unsigned int)&clk->src_cpu); 534 writel(CLK_SRC_TOP0_VAL, (unsigned int)&clk->src_top0); 535 writel(CLK_SRC_FSYS_VAL, (unsigned int)&clk->src_fsys); 536 writel(CLK_SRC_PERIL0_VAL, (unsigned int)&clk->src_peril0); 537 538 writel(CLK_DIV_CPU0_VAL, (unsigned int)&clk->div_cpu0); 539 writel(CLK_DIV_CPU1_VAL, (unsigned int)&clk->div_cpu1); 540 writel(CLK_DIV_DMC0_VAL, (unsigned int)&clk->div_dmc0); 541 writel(CLK_DIV_DMC1_VAL, (unsigned int)&clk->div_dmc1); 542 writel(CLK_DIV_LEFTBUS_VAL, (unsigned int)&clk->div_leftbus); 543 writel(CLK_DIV_RIGHTBUS_VAL, (unsigned int)&clk->div_rightbus); 544 writel(CLK_DIV_TOP_VAL, (unsigned int)&clk->div_top); 545 writel(CLK_DIV_FSYS1_VAL, (unsigned int)&clk->div_fsys1); 546 writel(CLK_DIV_FSYS2_VAL, (unsigned int)&clk->div_fsys2); 547 writel(CLK_DIV_FSYS3_VAL, (unsigned int)&clk->div_fsys3); 548 writel(CLK_DIV_PERIL0_VAL, (unsigned int)&clk->div_peril0); 549 writel(CLK_DIV_PERIL3_VAL, (unsigned int)&clk->div_peril3); 550 551 writel(PLL_LOCKTIME, (unsigned int)&clk->apll_lock); 552 writel(PLL_LOCKTIME, (unsigned int)&clk->mpll_lock); 553 writel(PLL_LOCKTIME, (unsigned int)&clk->epll_lock); 554 writel(PLL_LOCKTIME, (unsigned int)&clk->vpll_lock); 555 writel(APLL_CON1_VAL, (unsigned int)&clk->apll_con1); 556 writel(APLL_CON0_VAL, (unsigned int)&clk->apll_con0); 557 writel(MPLL_CON1_VAL, (unsigned int)&clk->mpll_con1); 558 writel(MPLL_CON0_VAL, (unsigned int)&clk->mpll_con0); 559 writel(EPLL_CON1_VAL, (unsigned int)&clk->epll_con1); 560 writel(EPLL_CON0_VAL, (unsigned int)&clk->epll_con0); 561 writel(VPLL_CON1_VAL, (unsigned int)&clk->vpll_con1); 562 writel(VPLL_CON0_VAL, (unsigned int)&clk->vpll_con0); 563 564 writel(CLK_GATE_IP_CAM_VAL, (unsigned int)&clk->gate_ip_cam); 565 writel(CLK_GATE_IP_VP_VAL, (unsigned int)&clk->gate_ip_tv); 566 writel(CLK_GATE_IP_MFC_VAL, (unsigned int)&clk->gate_ip_mfc); 567 writel(CLK_GATE_IP_G3D_VAL, (unsigned int)&clk->gate_ip_g3d); 568 writel(CLK_GATE_IP_IMAGE_VAL, (unsigned int)&clk->gate_ip_image); 569 writel(CLK_GATE_IP_LCD0_VAL, (unsigned int)&clk->gate_ip_lcd0); 570 writel(CLK_GATE_IP_LCD1_VAL, (unsigned int)&clk->gate_ip_lcd1); 571 writel(CLK_GATE_IP_FSYS_VAL, (unsigned int)&clk->gate_ip_fsys); 572 writel(CLK_GATE_IP_GPS_VAL, (unsigned int)&clk->gate_ip_gps); 573 writel(CLK_GATE_IP_PERIL_VAL, (unsigned int)&clk->gate_ip_peril); 574 writel(CLK_GATE_IP_PERIR_VAL, (unsigned int)&clk->gate_ip_perir); 575 writel(CLK_GATE_BLOCK_VAL, (unsigned int)&clk->gate_block); 576 } 577 578 static void board_power_init(void) 579 { 580 struct exynos4_power *pwr = 581 (struct exynos4_power *)samsung_get_base_power(); 582 583 /* PS HOLD */ 584 writel(EXYNOS4_PS_HOLD_CON_VAL, (unsigned int)&pwr->ps_hold_control); 585 586 /* Set power down */ 587 writel(0, (unsigned int)&pwr->cam_configuration); 588 writel(0, (unsigned int)&pwr->tv_configuration); 589 writel(0, (unsigned int)&pwr->mfc_configuration); 590 writel(0, (unsigned int)&pwr->g3d_configuration); 591 writel(0, (unsigned int)&pwr->lcd1_configuration); 592 writel(0, (unsigned int)&pwr->gps_configuration); 593 writel(0, (unsigned int)&pwr->gps_alive_configuration); 594 595 /* It is necessary to power down core 1 */ 596 /* to successfully boot CPU1 in kernel */ 597 writel(0, (unsigned int)&pwr->arm_core1_configuration); 598 } 599 600 static void board_uart_init(void) 601 { 602 struct exynos4_gpio_part1 *gpio1 = 603 (struct exynos4_gpio_part1 *)samsung_get_base_gpio_part1(); 604 struct exynos4_gpio_part2 *gpio2 = 605 (struct exynos4_gpio_part2 *)samsung_get_base_gpio_part2(); 606 int i; 607 608 /* 609 * UART2 GPIOs 610 * GPA1CON[0] = UART_2_RXD(2) 611 * GPA1CON[1] = UART_2_TXD(2) 612 * GPA1CON[2] = I2C_3_SDA (3) 613 * GPA1CON[3] = I2C_3_SCL (3) 614 */ 615 616 for (i = 0; i < 4; i++) { 617 s5p_gpio_set_pull(&gpio1->a1, i, GPIO_PULL_NONE); 618 s5p_gpio_cfg_pin(&gpio1->a1, i, GPIO_FUNC((i > 1) ? 0x3 : 0x2)); 619 } 620 621 /* UART_SEL GPY4[7] (part2) at EXYNOS4 */ 622 s5p_gpio_set_pull(&gpio2->y4, 7, GPIO_PULL_UP); 623 s5p_gpio_direction_output(&gpio2->y4, 7, 1); 624 } 625 626 int board_early_init_f(void) 627 { 628 wdt_stop(); 629 pmic_reset(); 630 board_clock_init(); 631 board_uart_init(); 632 board_power_init(); 633 634 return 0; 635 } 636 637 static void lcd_reset(void) 638 { 639 struct exynos4_gpio_part2 *gpio2 = 640 (struct exynos4_gpio_part2 *)samsung_get_base_gpio_part2(); 641 642 s5p_gpio_direction_output(&gpio2->y4, 5, 1); 643 udelay(10000); 644 s5p_gpio_direction_output(&gpio2->y4, 5, 0); 645 udelay(10000); 646 s5p_gpio_direction_output(&gpio2->y4, 5, 1); 647 } 648 649 static int lcd_power(void) 650 { 651 int ret = 0; 652 struct pmic *p = pmic_get("MAX8997_PMIC"); 653 if (!p) 654 return -ENODEV; 655 656 if (pmic_probe(p)) 657 return 0; 658 659 /* LDO15 voltage: 2.2v */ 660 ret |= pmic_reg_write(p, MAX8997_REG_LDO15CTRL, 0x1c | EN_LDO); 661 /* LDO13 voltage: 3.0v */ 662 ret |= pmic_reg_write(p, MAX8997_REG_LDO13CTRL, 0x2c | EN_LDO); 663 664 if (ret) { 665 puts("MAX8997 LDO setting error!\n"); 666 return -1; 667 } 668 669 return 0; 670 } 671 672 static struct mipi_dsim_config dsim_config = { 673 .e_interface = DSIM_VIDEO, 674 .e_virtual_ch = DSIM_VIRTUAL_CH_0, 675 .e_pixel_format = DSIM_24BPP_888, 676 .e_burst_mode = DSIM_BURST_SYNC_EVENT, 677 .e_no_data_lane = DSIM_DATA_LANE_4, 678 .e_byte_clk = DSIM_PLL_OUT_DIV8, 679 .hfp = 1, 680 681 .p = 3, 682 .m = 120, 683 .s = 1, 684 685 /* D-PHY PLL stable time spec :min = 200usec ~ max 400usec */ 686 .pll_stable_time = 500, 687 688 /* escape clk : 10MHz */ 689 .esc_clk = 20 * 1000000, 690 691 /* stop state holding counter after bta change count 0 ~ 0xfff */ 692 .stop_holding_cnt = 0x7ff, 693 /* bta timeout 0 ~ 0xff */ 694 .bta_timeout = 0xff, 695 /* lp rx timeout 0 ~ 0xffff */ 696 .rx_timeout = 0xffff, 697 }; 698 699 static struct exynos_platform_mipi_dsim s6e8ax0_platform_data = { 700 .lcd_panel_info = NULL, 701 .dsim_config = &dsim_config, 702 }; 703 704 static struct mipi_dsim_lcd_device mipi_lcd_device = { 705 .name = "s6e8ax0", 706 .id = -1, 707 .bus_id = 0, 708 .platform_data = (void *)&s6e8ax0_platform_data, 709 }; 710 711 static int mipi_power(void) 712 { 713 int ret = 0; 714 struct pmic *p = pmic_get("MAX8997_PMIC"); 715 if (!p) 716 return -ENODEV; 717 718 if (pmic_probe(p)) 719 return 0; 720 721 /* LDO3 voltage: 1.1v */ 722 ret |= pmic_reg_write(p, MAX8997_REG_LDO3CTRL, 0x6 | EN_LDO); 723 /* LDO4 voltage: 1.8v */ 724 ret |= pmic_reg_write(p, MAX8997_REG_LDO4CTRL, 0x14 | EN_LDO); 725 726 if (ret) { 727 puts("MAX8997 LDO setting error!\n"); 728 return -1; 729 } 730 731 return 0; 732 } 733 734 vidinfo_t panel_info = { 735 .vl_freq = 60, 736 .vl_col = 720, 737 .vl_row = 1280, 738 .vl_width = 720, 739 .vl_height = 1280, 740 .vl_clkp = CONFIG_SYS_HIGH, 741 .vl_hsp = CONFIG_SYS_LOW, 742 .vl_vsp = CONFIG_SYS_LOW, 743 .vl_dp = CONFIG_SYS_LOW, 744 .vl_bpix = 5, /* Bits per pixel, 2^5 = 32 */ 745 746 /* s6e8ax0 Panel infomation */ 747 .vl_hspw = 5, 748 .vl_hbpd = 10, 749 .vl_hfpd = 10, 750 751 .vl_vspw = 2, 752 .vl_vbpd = 1, 753 .vl_vfpd = 13, 754 .vl_cmd_allow_len = 0xf, 755 756 .win_id = 3, 757 .cfg_gpio = NULL, 758 .backlight_on = NULL, 759 .lcd_power_on = NULL, /* lcd_power_on in mipi dsi driver */ 760 .reset_lcd = lcd_reset, 761 .dual_lcd_enabled = 0, 762 763 .init_delay = 0, 764 .power_on_delay = 0, 765 .reset_delay = 0, 766 .interface_mode = FIMD_RGB_INTERFACE, 767 .mipi_enabled = 1, 768 }; 769 770 void init_panel_info(vidinfo_t *vid) 771 { 772 vid->logo_on = 1, 773 vid->resolution = HD_RESOLUTION, 774 vid->rgb_mode = MODE_RGB_P, 775 776 #ifdef CONFIG_TIZEN 777 get_tizen_logo_info(vid); 778 #endif 779 780 if (hwrevision(2)) 781 mipi_lcd_device.reverse_panel = 1; 782 783 strcpy(s6e8ax0_platform_data.lcd_panel_name, mipi_lcd_device.name); 784 s6e8ax0_platform_data.lcd_power = lcd_power; 785 s6e8ax0_platform_data.mipi_power = mipi_power; 786 s6e8ax0_platform_data.phy_enable = set_mipi_phy_ctrl; 787 s6e8ax0_platform_data.lcd_panel_info = (void *)vid; 788 exynos_mipi_dsi_register_lcd_device(&mipi_lcd_device); 789 s6e8ax0_init(); 790 exynos_set_dsim_platform_data(&s6e8ax0_platform_data); 791 792 setenv("lcdinfo", "lcd=s6e8ax0"); 793 } 794