1 /* 2 * Copyright (C) 2011 Samsung Electronics 3 * Heungjun Kim <riverful.kim@samsung.com> 4 * Kyungmin Park <kyungmin.park@samsung.com> 5 * Donghwa Lee <dh09.lee@samsung.com> 6 * 7 * See file CREDITS for list of people who contributed to this 8 * project. 9 * 10 * This program is free software; you can redistribute it and/or 11 * modify it under the terms of the GNU General Public License as 12 * published by the Free Software Foundation; either version 2 of 13 * the License, or (at your option) any later version. 14 * 15 * This program is distributed in the hope that it will be useful, 16 * but WITHOUT ANY WARRANTY; without even the implied warranty of 17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 18 * GNU General Public License for more details. 19 * 20 * You should have received a copy of the GNU General Public License 21 * along with this program; if not, write to the Free Software 22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 23 * MA 02111-1307 USA 24 */ 25 26 #include <common.h> 27 #include <lcd.h> 28 #include <asm/io.h> 29 #include <asm/arch/cpu.h> 30 #include <asm/arch/gpio.h> 31 #include <asm/arch/mmc.h> 32 #include <asm/arch/clock.h> 33 #include <asm/arch/clk.h> 34 #include <asm/arch/mipi_dsim.h> 35 #include <asm/arch/watchdog.h> 36 #include <asm/arch/power.h> 37 #include <pmic.h> 38 #include <usb/s3c_udc.h> 39 #include <max8997_pmic.h> 40 #include <libtizen.h> 41 42 #include "setup.h" 43 44 DECLARE_GLOBAL_DATA_PTR; 45 46 unsigned int board_rev; 47 48 #ifdef CONFIG_REVISION_TAG 49 u32 get_board_rev(void) 50 { 51 return board_rev; 52 } 53 #endif 54 55 static void check_hw_revision(void); 56 57 static int hwrevision(int rev) 58 { 59 return (board_rev & 0xf) == rev; 60 } 61 62 int board_init(void) 63 { 64 gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100; 65 66 check_hw_revision(); 67 printf("HW Revision:\t0x%x\n", board_rev); 68 69 #if defined(CONFIG_PMIC) 70 pmic_init(); 71 #endif 72 73 return 0; 74 } 75 76 int dram_init(void) 77 { 78 gd->ram_size = get_ram_size((long *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE) + 79 get_ram_size((long *)PHYS_SDRAM_2, PHYS_SDRAM_2_SIZE); 80 81 return 0; 82 } 83 84 void dram_init_banksize(void) 85 { 86 gd->bd->bi_dram[0].start = PHYS_SDRAM_1; 87 gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; 88 gd->bd->bi_dram[1].start = PHYS_SDRAM_2; 89 gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE; 90 } 91 92 static unsigned int get_hw_revision(void) 93 { 94 struct exynos4_gpio_part1 *gpio = 95 (struct exynos4_gpio_part1 *)samsung_get_base_gpio_part1(); 96 int hwrev = 0; 97 int i; 98 99 /* hw_rev[3:0] == GPE1[3:0] */ 100 for (i = 0; i < 4; i++) { 101 s5p_gpio_cfg_pin(&gpio->e1, i, GPIO_INPUT); 102 s5p_gpio_set_pull(&gpio->e1, i, GPIO_PULL_NONE); 103 } 104 105 udelay(1); 106 107 for (i = 0; i < 4; i++) 108 hwrev |= (s5p_gpio_get_value(&gpio->e1, i) << i); 109 110 debug("hwrev 0x%x\n", hwrev); 111 112 return hwrev; 113 } 114 115 static void check_hw_revision(void) 116 { 117 int hwrev; 118 119 hwrev = get_hw_revision(); 120 121 board_rev |= hwrev; 122 } 123 124 #ifdef CONFIG_DISPLAY_BOARDINFO 125 int checkboard(void) 126 { 127 puts("Board:\tTRATS\n"); 128 return 0; 129 } 130 #endif 131 132 #ifdef CONFIG_GENERIC_MMC 133 int board_mmc_init(bd_t *bis) 134 { 135 struct exynos4_gpio_part2 *gpio = 136 (struct exynos4_gpio_part2 *)samsung_get_base_gpio_part2(); 137 int i, err; 138 139 /* eMMC_EN: SD_0_CDn: GPK0[2] Output High */ 140 s5p_gpio_direction_output(&gpio->k0, 2, 1); 141 s5p_gpio_set_pull(&gpio->k0, 2, GPIO_PULL_NONE); 142 143 /* 144 * eMMC GPIO: 145 * SDR 8-bit@48MHz at MMC0 146 * GPK0[0] SD_0_CLK(2) 147 * GPK0[1] SD_0_CMD(2) 148 * GPK0[2] SD_0_CDn -> Not used 149 * GPK0[3:6] SD_0_DATA[0:3](2) 150 * GPK1[3:6] SD_0_DATA[0:3](3) 151 * 152 * DDR 4-bit@26MHz at MMC4 153 * GPK0[0] SD_4_CLK(3) 154 * GPK0[1] SD_4_CMD(3) 155 * GPK0[2] SD_4_CDn -> Not used 156 * GPK0[3:6] SD_4_DATA[0:3](3) 157 * GPK1[3:6] SD_4_DATA[4:7](4) 158 */ 159 for (i = 0; i < 7; i++) { 160 if (i == 2) 161 continue; 162 /* GPK0[0:6] special function 2 */ 163 s5p_gpio_cfg_pin(&gpio->k0, i, 0x2); 164 /* GPK0[0:6] pull disable */ 165 s5p_gpio_set_pull(&gpio->k0, i, GPIO_PULL_NONE); 166 /* GPK0[0:6] drv 4x */ 167 s5p_gpio_set_drv(&gpio->k0, i, GPIO_DRV_4X); 168 } 169 170 for (i = 3; i < 7; i++) { 171 /* GPK1[3:6] special function 3 */ 172 s5p_gpio_cfg_pin(&gpio->k1, i, 0x3); 173 /* GPK1[3:6] pull disable */ 174 s5p_gpio_set_pull(&gpio->k1, i, GPIO_PULL_NONE); 175 /* GPK1[3:6] drv 4x */ 176 s5p_gpio_set_drv(&gpio->k1, i, GPIO_DRV_4X); 177 } 178 179 /* 180 * MMC device init 181 * mmc0 : eMMC (8-bit buswidth) 182 * mmc2 : SD card (4-bit buswidth) 183 */ 184 err = s5p_mmc_init(0, 8); 185 186 /* T-flash detect */ 187 s5p_gpio_cfg_pin(&gpio->x3, 4, 0xf); 188 s5p_gpio_set_pull(&gpio->x3, 4, GPIO_PULL_UP); 189 190 /* 191 * Check the T-flash detect pin 192 * GPX3[4] T-flash detect pin 193 */ 194 if (!s5p_gpio_get_value(&gpio->x3, 4)) { 195 /* 196 * SD card GPIO: 197 * GPK2[0] SD_2_CLK(2) 198 * GPK2[1] SD_2_CMD(2) 199 * GPK2[2] SD_2_CDn -> Not used 200 * GPK2[3:6] SD_2_DATA[0:3](2) 201 */ 202 for (i = 0; i < 7; i++) { 203 if (i == 2) 204 continue; 205 /* GPK2[0:6] special function 2 */ 206 s5p_gpio_cfg_pin(&gpio->k2, i, 0x2); 207 /* GPK2[0:6] pull disable */ 208 s5p_gpio_set_pull(&gpio->k2, i, GPIO_PULL_NONE); 209 /* GPK2[0:6] drv 4x */ 210 s5p_gpio_set_drv(&gpio->k2, i, GPIO_DRV_4X); 211 } 212 err = s5p_mmc_init(2, 4); 213 } 214 215 return err; 216 } 217 #endif 218 219 #ifdef CONFIG_USB_GADGET 220 static int s5pc210_phy_control(int on) 221 { 222 int ret = 0; 223 u32 val = 0; 224 struct pmic *p = get_pmic(); 225 226 if (pmic_probe(p)) 227 return -1; 228 229 if (on) { 230 ret |= pmic_set_output(p, MAX8997_REG_SAFEOUTCTRL, 231 ENSAFEOUT1, LDO_ON); 232 ret |= pmic_reg_read(p, MAX8997_REG_LDO3CTRL, &val); 233 ret |= pmic_reg_write(p, MAX8997_REG_LDO3CTRL, EN_LDO | val); 234 235 ret |= pmic_reg_read(p, MAX8997_REG_LDO8CTRL, &val); 236 ret |= pmic_reg_write(p, MAX8997_REG_LDO8CTRL, EN_LDO | val); 237 } else { 238 ret |= pmic_reg_read(p, MAX8997_REG_LDO8CTRL, &val); 239 ret |= pmic_reg_write(p, MAX8997_REG_LDO8CTRL, DIS_LDO | val); 240 241 ret |= pmic_reg_read(p, MAX8997_REG_LDO3CTRL, &val); 242 ret |= pmic_reg_write(p, MAX8997_REG_LDO3CTRL, DIS_LDO | val); 243 ret |= pmic_set_output(p, MAX8997_REG_SAFEOUTCTRL, 244 ENSAFEOUT1, LDO_OFF); 245 } 246 247 if (ret) { 248 puts("MAX8997 LDO setting error!\n"); 249 return -1; 250 } 251 252 return 0; 253 } 254 255 struct s3c_plat_otg_data s5pc210_otg_data = { 256 .phy_control = s5pc210_phy_control, 257 .regs_phy = EXYNOS4_USBPHY_BASE, 258 .regs_otg = EXYNOS4_USBOTG_BASE, 259 .usb_phy_ctrl = EXYNOS4_USBPHY_CONTROL, 260 .usb_flags = PHY0_SLEEP, 261 }; 262 #endif 263 264 static void pmic_reset(void) 265 { 266 struct exynos4_gpio_part2 *gpio = 267 (struct exynos4_gpio_part2 *)samsung_get_base_gpio_part2(); 268 269 s5p_gpio_direction_output(&gpio->x0, 7, 1); 270 s5p_gpio_set_pull(&gpio->x2, 7, GPIO_PULL_NONE); 271 } 272 273 static void board_clock_init(void) 274 { 275 struct exynos4_clock *clk = 276 (struct exynos4_clock *)samsung_get_base_clock(); 277 278 writel(CLK_SRC_CPU_VAL, (unsigned int)&clk->src_cpu); 279 writel(CLK_SRC_TOP0_VAL, (unsigned int)&clk->src_top0); 280 writel(CLK_SRC_FSYS_VAL, (unsigned int)&clk->src_fsys); 281 writel(CLK_SRC_PERIL0_VAL, (unsigned int)&clk->src_peril0); 282 283 writel(CLK_DIV_CPU0_VAL, (unsigned int)&clk->div_cpu0); 284 writel(CLK_DIV_CPU1_VAL, (unsigned int)&clk->div_cpu1); 285 writel(CLK_DIV_DMC0_VAL, (unsigned int)&clk->div_dmc0); 286 writel(CLK_DIV_DMC1_VAL, (unsigned int)&clk->div_dmc1); 287 writel(CLK_DIV_LEFTBUS_VAL, (unsigned int)&clk->div_leftbus); 288 writel(CLK_DIV_RIGHTBUS_VAL, (unsigned int)&clk->div_rightbus); 289 writel(CLK_DIV_TOP_VAL, (unsigned int)&clk->div_top); 290 writel(CLK_DIV_FSYS1_VAL, (unsigned int)&clk->div_fsys1); 291 writel(CLK_DIV_FSYS2_VAL, (unsigned int)&clk->div_fsys2); 292 writel(CLK_DIV_FSYS3_VAL, (unsigned int)&clk->div_fsys3); 293 writel(CLK_DIV_PERIL0_VAL, (unsigned int)&clk->div_peril0); 294 writel(CLK_DIV_PERIL3_VAL, (unsigned int)&clk->div_peril3); 295 296 writel(PLL_LOCKTIME, (unsigned int)&clk->apll_lock); 297 writel(PLL_LOCKTIME, (unsigned int)&clk->mpll_lock); 298 writel(PLL_LOCKTIME, (unsigned int)&clk->epll_lock); 299 writel(PLL_LOCKTIME, (unsigned int)&clk->vpll_lock); 300 writel(APLL_CON1_VAL, (unsigned int)&clk->apll_con1); 301 writel(APLL_CON0_VAL, (unsigned int)&clk->apll_con0); 302 writel(MPLL_CON1_VAL, (unsigned int)&clk->mpll_con1); 303 writel(MPLL_CON0_VAL, (unsigned int)&clk->mpll_con0); 304 writel(EPLL_CON1_VAL, (unsigned int)&clk->epll_con1); 305 writel(EPLL_CON0_VAL, (unsigned int)&clk->epll_con0); 306 writel(VPLL_CON1_VAL, (unsigned int)&clk->vpll_con1); 307 writel(VPLL_CON0_VAL, (unsigned int)&clk->vpll_con0); 308 309 writel(CLK_GATE_IP_CAM_VAL, (unsigned int)&clk->gate_ip_cam); 310 writel(CLK_GATE_IP_VP_VAL, (unsigned int)&clk->gate_ip_tv); 311 writel(CLK_GATE_IP_MFC_VAL, (unsigned int)&clk->gate_ip_mfc); 312 writel(CLK_GATE_IP_G3D_VAL, (unsigned int)&clk->gate_ip_g3d); 313 writel(CLK_GATE_IP_IMAGE_VAL, (unsigned int)&clk->gate_ip_image); 314 writel(CLK_GATE_IP_LCD0_VAL, (unsigned int)&clk->gate_ip_lcd0); 315 writel(CLK_GATE_IP_LCD1_VAL, (unsigned int)&clk->gate_ip_lcd1); 316 writel(CLK_GATE_IP_FSYS_VAL, (unsigned int)&clk->gate_ip_fsys); 317 writel(CLK_GATE_IP_GPS_VAL, (unsigned int)&clk->gate_ip_gps); 318 writel(CLK_GATE_IP_PERIL_VAL, (unsigned int)&clk->gate_ip_peril); 319 writel(CLK_GATE_IP_PERIR_VAL, (unsigned int)&clk->gate_ip_perir); 320 writel(CLK_GATE_BLOCK_VAL, (unsigned int)&clk->gate_block); 321 } 322 323 static void board_power_init(void) 324 { 325 struct exynos4_power *pwr = 326 (struct exynos4_power *)samsung_get_base_power(); 327 328 /* PS HOLD */ 329 writel(EXYNOS4_PS_HOLD_CON_VAL, (unsigned int)&pwr->ps_hold_control); 330 331 /* Set power down */ 332 writel(0, (unsigned int)&pwr->cam_configuration); 333 writel(0, (unsigned int)&pwr->tv_configuration); 334 writel(0, (unsigned int)&pwr->mfc_configuration); 335 writel(0, (unsigned int)&pwr->g3d_configuration); 336 writel(0, (unsigned int)&pwr->lcd1_configuration); 337 writel(0, (unsigned int)&pwr->gps_configuration); 338 writel(0, (unsigned int)&pwr->gps_alive_configuration); 339 } 340 341 static void board_uart_init(void) 342 { 343 struct exynos4_gpio_part1 *gpio1 = 344 (struct exynos4_gpio_part1 *)samsung_get_base_gpio_part1(); 345 struct exynos4_gpio_part2 *gpio2 = 346 (struct exynos4_gpio_part2 *)samsung_get_base_gpio_part2(); 347 int i; 348 349 /* 350 * UART2 GPIOs 351 * GPA1CON[0] = UART_2_RXD(2) 352 * GPA1CON[1] = UART_2_TXD(2) 353 * GPA1CON[2] = I2C_3_SDA (3) 354 * GPA1CON[3] = I2C_3_SCL (3) 355 */ 356 357 for (i = 0; i < 4; i++) { 358 s5p_gpio_set_pull(&gpio1->a1, i, GPIO_PULL_NONE); 359 s5p_gpio_cfg_pin(&gpio1->a1, i, GPIO_FUNC((i > 1) ? 0x3 : 0x2)); 360 } 361 362 /* UART_SEL GPY4[7] (part2) at EXYNOS4 */ 363 s5p_gpio_set_pull(&gpio2->y4, 7, GPIO_PULL_UP); 364 s5p_gpio_direction_output(&gpio2->y4, 7, 1); 365 } 366 367 int board_early_init_f(void) 368 { 369 wdt_stop(); 370 pmic_reset(); 371 board_clock_init(); 372 board_uart_init(); 373 board_power_init(); 374 375 return 0; 376 } 377 378 static void lcd_reset(void) 379 { 380 struct exynos4_gpio_part2 *gpio2 = 381 (struct exynos4_gpio_part2 *)samsung_get_base_gpio_part2(); 382 383 s5p_gpio_direction_output(&gpio2->y4, 5, 1); 384 udelay(10000); 385 s5p_gpio_direction_output(&gpio2->y4, 5, 0); 386 udelay(10000); 387 s5p_gpio_direction_output(&gpio2->y4, 5, 1); 388 } 389 390 static int lcd_power(void) 391 { 392 int ret = 0; 393 struct pmic *p = get_pmic(); 394 395 if (pmic_probe(p)) 396 return 0; 397 398 /* LDO15 voltage: 2.2v */ 399 ret |= pmic_reg_write(p, MAX8997_REG_LDO15CTRL, 0x1c | EN_LDO); 400 /* LDO13 voltage: 3.0v */ 401 ret |= pmic_reg_write(p, MAX8997_REG_LDO13CTRL, 0x2c | EN_LDO); 402 403 if (ret) { 404 puts("MAX8997 LDO setting error!\n"); 405 return -1; 406 } 407 408 return 0; 409 } 410 411 static struct mipi_dsim_config dsim_config = { 412 .e_interface = DSIM_VIDEO, 413 .e_virtual_ch = DSIM_VIRTUAL_CH_0, 414 .e_pixel_format = DSIM_24BPP_888, 415 .e_burst_mode = DSIM_BURST_SYNC_EVENT, 416 .e_no_data_lane = DSIM_DATA_LANE_4, 417 .e_byte_clk = DSIM_PLL_OUT_DIV8, 418 .hfp = 1, 419 420 .p = 3, 421 .m = 120, 422 .s = 1, 423 424 /* D-PHY PLL stable time spec :min = 200usec ~ max 400usec */ 425 .pll_stable_time = 500, 426 427 /* escape clk : 10MHz */ 428 .esc_clk = 20 * 1000000, 429 430 /* stop state holding counter after bta change count 0 ~ 0xfff */ 431 .stop_holding_cnt = 0x7ff, 432 /* bta timeout 0 ~ 0xff */ 433 .bta_timeout = 0xff, 434 /* lp rx timeout 0 ~ 0xffff */ 435 .rx_timeout = 0xffff, 436 }; 437 438 static struct exynos_platform_mipi_dsim s6e8ax0_platform_data = { 439 .lcd_panel_info = NULL, 440 .dsim_config = &dsim_config, 441 }; 442 443 static struct mipi_dsim_lcd_device mipi_lcd_device = { 444 .name = "s6e8ax0", 445 .id = -1, 446 .bus_id = 0, 447 .platform_data = (void *)&s6e8ax0_platform_data, 448 }; 449 450 static int mipi_power(void) 451 { 452 int ret = 0; 453 struct pmic *p = get_pmic(); 454 455 if (pmic_probe(p)) 456 return 0; 457 458 /* LDO3 voltage: 1.1v */ 459 ret |= pmic_reg_write(p, MAX8997_REG_LDO3CTRL, 0x6 | EN_LDO); 460 /* LDO4 voltage: 1.8v */ 461 ret |= pmic_reg_write(p, MAX8997_REG_LDO4CTRL, 0x14 | EN_LDO); 462 463 if (ret) { 464 puts("MAX8997 LDO setting error!\n"); 465 return -1; 466 } 467 468 return 0; 469 } 470 471 vidinfo_t panel_info = { 472 .vl_freq = 60, 473 .vl_col = 720, 474 .vl_row = 1280, 475 .vl_width = 720, 476 .vl_height = 1280, 477 .vl_clkp = CONFIG_SYS_HIGH, 478 .vl_hsp = CONFIG_SYS_LOW, 479 .vl_vsp = CONFIG_SYS_LOW, 480 .vl_dp = CONFIG_SYS_LOW, 481 .vl_bpix = 5, /* Bits per pixel, 2^5 = 32 */ 482 483 /* s6e8ax0 Panel infomation */ 484 .vl_hspw = 5, 485 .vl_hbpd = 10, 486 .vl_hfpd = 10, 487 488 .vl_vspw = 2, 489 .vl_vbpd = 1, 490 .vl_vfpd = 13, 491 .vl_cmd_allow_len = 0xf, 492 493 .win_id = 3, 494 .cfg_gpio = NULL, 495 .backlight_on = NULL, 496 .lcd_power_on = NULL, /* lcd_power_on in mipi dsi driver */ 497 .reset_lcd = lcd_reset, 498 .dual_lcd_enabled = 0, 499 500 .init_delay = 0, 501 .power_on_delay = 0, 502 .reset_delay = 0, 503 .interface_mode = FIMD_RGB_INTERFACE, 504 .mipi_enabled = 1, 505 }; 506 507 void init_panel_info(vidinfo_t *vid) 508 { 509 vid->logo_on = 1, 510 vid->resolution = HD_RESOLUTION, 511 vid->rgb_mode = MODE_RGB_P, 512 513 #ifdef CONFIG_TIZEN 514 get_tizen_logo_info(vid); 515 #endif 516 517 if (hwrevision(2)) 518 mipi_lcd_device.reverse_panel = 1; 519 520 strcpy(s6e8ax0_platform_data.lcd_panel_name, mipi_lcd_device.name); 521 s6e8ax0_platform_data.lcd_power = lcd_power; 522 s6e8ax0_platform_data.mipi_power = mipi_power; 523 s6e8ax0_platform_data.phy_enable = set_mipi_phy_ctrl; 524 s6e8ax0_platform_data.lcd_panel_info = (void *)vid; 525 exynos_mipi_dsi_register_lcd_device(&mipi_lcd_device); 526 s6e8ax0_init(); 527 exynos_set_dsim_platform_data(&s6e8ax0_platform_data); 528 529 setenv("lcdinfo", "lcd=s6e8ax0"); 530 } 531