1 /* 2 * Copyright (C) 2011 Samsung Electronics 3 * Heungjun Kim <riverful.kim@samsung.com> 4 * Kyungmin Park <kyungmin.park@samsung.com> 5 * Donghwa Lee <dh09.lee@samsung.com> 6 * 7 * See file CREDITS for list of people who contributed to this 8 * project. 9 * 10 * This program is free software; you can redistribute it and/or 11 * modify it under the terms of the GNU General Public License as 12 * published by the Free Software Foundation; either version 2 of 13 * the License, or (at your option) any later version. 14 * 15 * This program is distributed in the hope that it will be useful, 16 * but WITHOUT ANY WARRANTY; without even the implied warranty of 17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 18 * GNU General Public License for more details. 19 * 20 * You should have received a copy of the GNU General Public License 21 * along with this program; if not, write to the Free Software 22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 23 * MA 02111-1307 USA 24 */ 25 26 #include <common.h> 27 #include <lcd.h> 28 #include <asm/io.h> 29 #include <asm/arch/cpu.h> 30 #include <asm/arch/gpio.h> 31 #include <asm/arch/mmc.h> 32 #include <asm/arch/pinmux.h> 33 #include <asm/arch/clock.h> 34 #include <asm/arch/clk.h> 35 #include <asm/arch/mipi_dsim.h> 36 #include <asm/arch/watchdog.h> 37 #include <asm/arch/power.h> 38 #include <power/pmic.h> 39 #include <usb/s3c_udc.h> 40 #include <power/max8997_pmic.h> 41 #include <libtizen.h> 42 #include <power/max8997_muic.h> 43 #include <power/battery.h> 44 #include <power/max17042_fg.h> 45 #include <usb_mass_storage.h> 46 47 #include "setup.h" 48 49 DECLARE_GLOBAL_DATA_PTR; 50 51 unsigned int board_rev; 52 53 #ifdef CONFIG_REVISION_TAG 54 u32 get_board_rev(void) 55 { 56 return board_rev; 57 } 58 #endif 59 60 static void check_hw_revision(void); 61 62 static int hwrevision(int rev) 63 { 64 return (board_rev & 0xf) == rev; 65 } 66 67 struct s3c_plat_otg_data s5pc210_otg_data; 68 69 int board_init(void) 70 { 71 gd->bd->bi_boot_params = CONFIG_SYS_SPL_ARGS_ADDR; 72 73 check_hw_revision(); 74 printf("HW Revision:\t0x%x\n", board_rev); 75 76 return 0; 77 } 78 79 void i2c_init_board(void) 80 { 81 struct exynos4_gpio_part1 *gpio1 = 82 (struct exynos4_gpio_part1 *)samsung_get_base_gpio_part1(); 83 struct exynos4_gpio_part2 *gpio2 = 84 (struct exynos4_gpio_part2 *)samsung_get_base_gpio_part2(); 85 86 /* I2C_5 -> PMIC */ 87 s5p_gpio_direction_output(&gpio1->b, 7, 1); 88 s5p_gpio_direction_output(&gpio1->b, 6, 1); 89 /* I2C_9 -> FG */ 90 s5p_gpio_direction_output(&gpio2->y4, 0, 1); 91 s5p_gpio_direction_output(&gpio2->y4, 1, 1); 92 } 93 94 static void trats_low_power_mode(void) 95 { 96 struct exynos4_clock *clk = 97 (struct exynos4_clock *)samsung_get_base_clock(); 98 struct exynos4_power *pwr = 99 (struct exynos4_power *)samsung_get_base_power(); 100 101 /* Power down CORE1 */ 102 /* LOCAL_PWR_CFG [1:0] 0x3 EN, 0x0 DIS */ 103 writel(0x0, &pwr->arm_core1_configuration); 104 105 /* Change the APLL frequency */ 106 /* ENABLE (1 enable) | LOCKED (1 locked) */ 107 /* [31] | [29] */ 108 /* FSEL | MDIV | PDIV | SDIV */ 109 /* [27] | [25:16] | [13:8] | [2:0] */ 110 writel(0xa0c80604, &clk->apll_con0); 111 112 /* Change CPU0 clock divider */ 113 /* CORE2_RATIO | APLL_RATIO | PCLK_DBG_RATIO | ATB_RATIO */ 114 /* [30:28] | [26:24] | [22:20] | [18:16] */ 115 /* PERIPH_RATIO | COREM1_RATIO | COREM0_RATIO | CORE_RATIO */ 116 /* [14:12] | [10:8] | [6:4] | [2:0] */ 117 writel(0x00000100, &clk->div_cpu0); 118 119 /* CLK_DIV_STAT_CPU0 - wait until clock gets stable (0 = stable) */ 120 while (readl(&clk->div_stat_cpu0) & 0x1111111) 121 continue; 122 123 /* Change clock divider ratio for DMC */ 124 /* DMCP_RATIO | DMCD_RATIO */ 125 /* [22:20] | [18:16] */ 126 /* DMC_RATIO | DPHY_RATIO | ACP_PCLK_RATIO | ACP_RATIO */ 127 /* [14:12] | [10:8] | [6:4] | [2:0] */ 128 writel(0x13113117, &clk->div_dmc0); 129 130 /* CLK_DIV_STAT_DMC0 - wait until clock gets stable (0 = stable) */ 131 while (readl(&clk->div_stat_dmc0) & 0x11111111) 132 continue; 133 134 /* Turn off unnecessary power domains */ 135 writel(0x0, &pwr->xxti_configuration); /* XXTI */ 136 writel(0x0, &pwr->cam_configuration); /* CAM */ 137 writel(0x0, &pwr->tv_configuration); /* TV */ 138 writel(0x0, &pwr->mfc_configuration); /* MFC */ 139 writel(0x0, &pwr->g3d_configuration); /* G3D */ 140 writel(0x0, &pwr->gps_configuration); /* GPS */ 141 writel(0x0, &pwr->gps_alive_configuration); /* GPS_ALIVE */ 142 143 /* Turn off unnecessary clocks */ 144 writel(0x0, &clk->gate_ip_cam); /* CAM */ 145 writel(0x0, &clk->gate_ip_tv); /* TV */ 146 writel(0x0, &clk->gate_ip_mfc); /* MFC */ 147 writel(0x0, &clk->gate_ip_g3d); /* G3D */ 148 writel(0x0, &clk->gate_ip_image); /* IMAGE */ 149 writel(0x0, &clk->gate_ip_gps); /* GPS */ 150 } 151 152 static int pmic_init_max8997(void) 153 { 154 struct pmic *p = pmic_get("MAX8997_PMIC"); 155 int i = 0, ret = 0; 156 u32 val; 157 158 if (pmic_probe(p)) 159 return -1; 160 161 /* BUCK1 VARM: 1.2V */ 162 val = (1200000 - 650000) / 25000; 163 ret |= pmic_reg_write(p, MAX8997_REG_BUCK1DVS1, val); 164 val = ENBUCK | ACTIVE_DISCHARGE; /* DVS OFF */ 165 ret |= pmic_reg_write(p, MAX8997_REG_BUCK1CTRL, val); 166 167 /* BUCK2 VINT: 1.1V */ 168 val = (1100000 - 650000) / 25000; 169 ret |= pmic_reg_write(p, MAX8997_REG_BUCK2DVS1, val); 170 val = ENBUCK | ACTIVE_DISCHARGE; /* DVS OFF */ 171 ret |= pmic_reg_write(p, MAX8997_REG_BUCK2CTRL, val); 172 173 174 /* BUCK3 G3D: 1.1V - OFF */ 175 ret |= pmic_reg_read(p, MAX8997_REG_BUCK3CTRL, &val); 176 val &= ~ENBUCK; 177 ret |= pmic_reg_write(p, MAX8997_REG_BUCK3CTRL, val); 178 179 val = (1100000 - 750000) / 50000; 180 ret |= pmic_reg_write(p, MAX8997_REG_BUCK3DVS, val); 181 182 /* BUCK4 CAMISP: 1.2V - OFF */ 183 ret |= pmic_reg_read(p, MAX8997_REG_BUCK4CTRL, &val); 184 val &= ~ENBUCK; 185 ret |= pmic_reg_write(p, MAX8997_REG_BUCK4CTRL, val); 186 187 val = (1200000 - 650000) / 25000; 188 ret |= pmic_reg_write(p, MAX8997_REG_BUCK4DVS, val); 189 190 /* BUCK5 VMEM: 1.2V */ 191 val = (1200000 - 650000) / 25000; 192 for (i = 0; i < 8; i++) 193 ret |= pmic_reg_write(p, MAX8997_REG_BUCK5DVS1 + i, val); 194 195 val = ENBUCK | ACTIVE_DISCHARGE; /* DVS OFF */ 196 ret |= pmic_reg_write(p, MAX8997_REG_BUCK5CTRL, val); 197 198 /* BUCK6 CAM AF: 2.8V */ 199 /* No Voltage Setting Register */ 200 /* GNSLCT 3.0X */ 201 val = GNSLCT; 202 ret |= pmic_reg_write(p, MAX8997_REG_BUCK6CTRL, val); 203 204 /* BUCK7 VCC_SUB: 2.0V */ 205 val = (2000000 - 750000) / 50000; 206 ret |= pmic_reg_write(p, MAX8997_REG_BUCK7DVS, val); 207 208 /* LDO1 VADC: 3.3V */ 209 val = max8997_reg_ldo(3300000) | DIS_LDO; /* OFF */ 210 ret |= pmic_reg_write(p, MAX8997_REG_LDO1CTRL, val); 211 212 /* LDO1 Disable active discharging */ 213 ret |= pmic_reg_read(p, MAX8997_REG_LDO1CONFIG, &val); 214 val &= ~LDO_ADE; 215 ret |= pmic_reg_write(p, MAX8997_REG_LDO1CONFIG, val); 216 217 /* LDO2 VALIVE: 1.1V */ 218 val = max8997_reg_ldo(1100000) | EN_LDO; 219 ret |= pmic_reg_write(p, MAX8997_REG_LDO2CTRL, val); 220 221 /* LDO3 VUSB/MIPI: 1.1V */ 222 val = max8997_reg_ldo(1100000) | DIS_LDO; /* OFF */ 223 ret |= pmic_reg_write(p, MAX8997_REG_LDO3CTRL, val); 224 225 /* LDO4 VMIPI: 1.8V */ 226 val = max8997_reg_ldo(1800000) | DIS_LDO; /* OFF */ 227 ret |= pmic_reg_write(p, MAX8997_REG_LDO4CTRL, val); 228 229 /* LDO5 VHSIC: 1.2V */ 230 val = max8997_reg_ldo(1200000) | DIS_LDO; /* OFF */ 231 ret |= pmic_reg_write(p, MAX8997_REG_LDO5CTRL, val); 232 233 /* LDO6 VCC_1.8V_PDA: 1.8V */ 234 val = max8997_reg_ldo(1800000) | EN_LDO; 235 ret |= pmic_reg_write(p, MAX8997_REG_LDO6CTRL, val); 236 237 /* LDO7 CAM_ISP: 1.8V */ 238 val = max8997_reg_ldo(1800000) | DIS_LDO; /* OFF */ 239 ret |= pmic_reg_write(p, MAX8997_REG_LDO7CTRL, val); 240 241 /* LDO8 VDAC/VUSB: 3.3V */ 242 val = max8997_reg_ldo(3300000) | DIS_LDO; /* OFF */ 243 ret |= pmic_reg_write(p, MAX8997_REG_LDO8CTRL, val); 244 245 /* LDO9 VCC_2.8V_PDA: 2.8V */ 246 val = max8997_reg_ldo(2800000) | EN_LDO; 247 ret |= pmic_reg_write(p, MAX8997_REG_LDO9CTRL, val); 248 249 /* LDO10 VPLL: 1.1V */ 250 val = max8997_reg_ldo(1100000) | EN_LDO; 251 ret |= pmic_reg_write(p, MAX8997_REG_LDO10CTRL, val); 252 253 /* LDO11 TOUCH: 2.8V */ 254 val = max8997_reg_ldo(2800000) | DIS_LDO; /* OFF */ 255 ret |= pmic_reg_write(p, MAX8997_REG_LDO11CTRL, val); 256 257 /* LDO12 VTCAM: 1.8V */ 258 val = max8997_reg_ldo(1800000) | DIS_LDO; /* OFF */ 259 ret |= pmic_reg_write(p, MAX8997_REG_LDO12CTRL, val); 260 261 /* LDO13 VCC_3.0_LCD: 3.0V */ 262 val = max8997_reg_ldo(3000000) | DIS_LDO; /* OFF */ 263 ret |= pmic_reg_write(p, MAX8997_REG_LDO13CTRL, val); 264 265 /* LDO14 MOTOR: 3.0V */ 266 val = max8997_reg_ldo(3000000) | DIS_LDO; /* OFF */ 267 ret |= pmic_reg_write(p, MAX8997_REG_LDO14CTRL, val); 268 269 /* LDO15 LED_A: 2.8V */ 270 val = max8997_reg_ldo(2800000) | DIS_LDO; /* OFF */ 271 ret |= pmic_reg_write(p, MAX8997_REG_LDO15CTRL, val); 272 273 /* LDO16 CAM_SENSOR: 1.8V */ 274 val = max8997_reg_ldo(1800000) | DIS_LDO; /* OFF */ 275 ret |= pmic_reg_write(p, MAX8997_REG_LDO16CTRL, val); 276 277 /* LDO17 VTF: 2.8V */ 278 val = max8997_reg_ldo(2800000) | DIS_LDO; /* OFF */ 279 ret |= pmic_reg_write(p, MAX8997_REG_LDO17CTRL, val); 280 281 /* LDO18 TOUCH_LED 3.3V */ 282 val = max8997_reg_ldo(3300000) | DIS_LDO; /* OFF */ 283 ret |= pmic_reg_write(p, MAX8997_REG_LDO18CTRL, val); 284 285 /* LDO21 VDDQ: 1.2V */ 286 val = max8997_reg_ldo(1200000) | EN_LDO; 287 ret |= pmic_reg_write(p, MAX8997_REG_LDO21CTRL, val); 288 289 /* SAFEOUT for both 1 and 2: 4.9V, Active discharge, Enable */ 290 val = (SAFEOUT_4_90V << 0) | (SAFEOUT_4_90V << 2) | 291 ACTDISSAFEO1 | ACTDISSAFEO2 | ENSAFEOUT1 | ENSAFEOUT2; 292 ret |= pmic_reg_write(p, MAX8997_REG_SAFEOUTCTRL, val); 293 294 if (ret) { 295 puts("MAX8997 PMIC setting error!\n"); 296 return -1; 297 } 298 return 0; 299 } 300 301 int power_init_board(void) 302 { 303 int chrg, ret; 304 struct power_battery *pb; 305 struct pmic *p_fg, *p_chrg, *p_muic, *p_bat; 306 307 ret = pmic_init(I2C_5); 308 ret |= pmic_init_max8997(); 309 ret |= power_fg_init(I2C_9); 310 ret |= power_muic_init(I2C_5); 311 ret |= power_bat_init(0); 312 if (ret) 313 return ret; 314 315 p_fg = pmic_get("MAX17042_FG"); 316 if (!p_fg) { 317 puts("MAX17042_FG: Not found\n"); 318 return -ENODEV; 319 } 320 321 p_chrg = pmic_get("MAX8997_PMIC"); 322 if (!p_chrg) { 323 puts("MAX8997_PMIC: Not found\n"); 324 return -ENODEV; 325 } 326 327 p_muic = pmic_get("MAX8997_MUIC"); 328 if (!p_muic) { 329 puts("MAX8997_MUIC: Not found\n"); 330 return -ENODEV; 331 } 332 333 p_bat = pmic_get("BAT_TRATS"); 334 if (!p_bat) { 335 puts("BAT_TRATS: Not found\n"); 336 return -ENODEV; 337 } 338 339 p_fg->parent = p_bat; 340 p_chrg->parent = p_bat; 341 p_muic->parent = p_bat; 342 343 p_bat->low_power_mode = trats_low_power_mode; 344 p_bat->pbat->battery_init(p_bat, p_fg, p_chrg, p_muic); 345 346 pb = p_bat->pbat; 347 chrg = p_muic->chrg->chrg_type(p_muic); 348 debug("CHARGER TYPE: %d\n", chrg); 349 350 if (!p_chrg->chrg->chrg_bat_present(p_chrg)) { 351 puts("No battery detected\n"); 352 return -1; 353 } 354 355 p_fg->fg->fg_battery_check(p_fg, p_bat); 356 357 if (pb->bat->state == CHARGE && chrg == CHARGER_USB) 358 puts("CHARGE Battery !\n"); 359 360 return 0; 361 } 362 363 int dram_init(void) 364 { 365 gd->ram_size = get_ram_size((long *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE) + 366 get_ram_size((long *)PHYS_SDRAM_2, PHYS_SDRAM_2_SIZE) + 367 get_ram_size((long *)PHYS_SDRAM_3, PHYS_SDRAM_3_SIZE) + 368 get_ram_size((long *)PHYS_SDRAM_4, PHYS_SDRAM_4_SIZE); 369 370 return 0; 371 } 372 373 void dram_init_banksize(void) 374 { 375 gd->bd->bi_dram[0].start = PHYS_SDRAM_1; 376 gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; 377 gd->bd->bi_dram[1].start = PHYS_SDRAM_2; 378 gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE; 379 gd->bd->bi_dram[2].start = PHYS_SDRAM_3; 380 gd->bd->bi_dram[2].size = PHYS_SDRAM_3_SIZE; 381 gd->bd->bi_dram[3].start = PHYS_SDRAM_4; 382 gd->bd->bi_dram[3].size = PHYS_SDRAM_4_SIZE; 383 } 384 385 static unsigned int get_hw_revision(void) 386 { 387 struct exynos4_gpio_part1 *gpio = 388 (struct exynos4_gpio_part1 *)samsung_get_base_gpio_part1(); 389 int hwrev = 0; 390 int i; 391 392 /* hw_rev[3:0] == GPE1[3:0] */ 393 for (i = 0; i < 4; i++) { 394 s5p_gpio_cfg_pin(&gpio->e1, i, GPIO_INPUT); 395 s5p_gpio_set_pull(&gpio->e1, i, GPIO_PULL_NONE); 396 } 397 398 udelay(1); 399 400 for (i = 0; i < 4; i++) 401 hwrev |= (s5p_gpio_get_value(&gpio->e1, i) << i); 402 403 debug("hwrev 0x%x\n", hwrev); 404 405 return hwrev; 406 } 407 408 static void check_hw_revision(void) 409 { 410 int hwrev; 411 412 hwrev = get_hw_revision(); 413 414 board_rev |= hwrev; 415 } 416 417 #ifdef CONFIG_DISPLAY_BOARDINFO 418 int checkboard(void) 419 { 420 puts("Board:\tTRATS\n"); 421 return 0; 422 } 423 #endif 424 425 #ifdef CONFIG_GENERIC_MMC 426 int board_mmc_init(bd_t *bis) 427 { 428 struct exynos4_gpio_part2 *gpio = 429 (struct exynos4_gpio_part2 *)samsung_get_base_gpio_part2(); 430 int err; 431 432 /* eMMC_EN: SD_0_CDn: GPK0[2] Output High */ 433 s5p_gpio_direction_output(&gpio->k0, 2, 1); 434 s5p_gpio_set_pull(&gpio->k0, 2, GPIO_PULL_NONE); 435 436 /* 437 * MMC device init 438 * mmc0 : eMMC (8-bit buswidth) 439 * mmc2 : SD card (4-bit buswidth) 440 */ 441 err = exynos_pinmux_config(PERIPH_ID_SDMMC0, PINMUX_FLAG_8BIT_MODE); 442 if (err) 443 debug("SDMMC0 not configured\n"); 444 else 445 err = s5p_mmc_init(0, 8); 446 447 /* T-flash detect */ 448 s5p_gpio_cfg_pin(&gpio->x3, 4, 0xf); 449 s5p_gpio_set_pull(&gpio->x3, 4, GPIO_PULL_UP); 450 451 /* 452 * Check the T-flash detect pin 453 * GPX3[4] T-flash detect pin 454 */ 455 if (!s5p_gpio_get_value(&gpio->x3, 4)) { 456 err = exynos_pinmux_config(PERIPH_ID_SDMMC2, PINMUX_FLAG_NONE); 457 if (err) 458 debug("SDMMC2 not configured\n"); 459 else 460 err = s5p_mmc_init(2, 4); 461 } 462 463 return err; 464 } 465 #endif 466 467 #ifdef CONFIG_USB_GADGET 468 static int s5pc210_phy_control(int on) 469 { 470 int ret = 0; 471 u32 val = 0; 472 struct pmic *p = pmic_get("MAX8997_PMIC"); 473 if (!p) 474 return -ENODEV; 475 476 if (pmic_probe(p)) 477 return -1; 478 479 if (on) { 480 ret |= pmic_set_output(p, MAX8997_REG_SAFEOUTCTRL, 481 ENSAFEOUT1, LDO_ON); 482 ret |= pmic_reg_read(p, MAX8997_REG_LDO3CTRL, &val); 483 ret |= pmic_reg_write(p, MAX8997_REG_LDO3CTRL, EN_LDO | val); 484 485 ret |= pmic_reg_read(p, MAX8997_REG_LDO8CTRL, &val); 486 ret |= pmic_reg_write(p, MAX8997_REG_LDO8CTRL, EN_LDO | val); 487 } else { 488 ret |= pmic_reg_read(p, MAX8997_REG_LDO8CTRL, &val); 489 ret |= pmic_reg_write(p, MAX8997_REG_LDO8CTRL, DIS_LDO | val); 490 491 ret |= pmic_reg_read(p, MAX8997_REG_LDO3CTRL, &val); 492 ret |= pmic_reg_write(p, MAX8997_REG_LDO3CTRL, DIS_LDO | val); 493 ret |= pmic_set_output(p, MAX8997_REG_SAFEOUTCTRL, 494 ENSAFEOUT1, LDO_OFF); 495 } 496 497 if (ret) { 498 puts("MAX8997 LDO setting error!\n"); 499 return -1; 500 } 501 502 return 0; 503 } 504 505 struct s3c_plat_otg_data s5pc210_otg_data = { 506 .phy_control = s5pc210_phy_control, 507 .regs_phy = EXYNOS4_USBPHY_BASE, 508 .regs_otg = EXYNOS4_USBOTG_BASE, 509 .usb_phy_ctrl = EXYNOS4_USBPHY_CONTROL, 510 .usb_flags = PHY0_SLEEP, 511 }; 512 513 void board_usb_init(void) 514 { 515 debug("USB_udc_probe\n"); 516 s3c_udc_probe(&s5pc210_otg_data); 517 } 518 #endif 519 520 static void pmic_reset(void) 521 { 522 struct exynos4_gpio_part2 *gpio = 523 (struct exynos4_gpio_part2 *)samsung_get_base_gpio_part2(); 524 525 s5p_gpio_direction_output(&gpio->x0, 7, 1); 526 s5p_gpio_set_pull(&gpio->x2, 7, GPIO_PULL_NONE); 527 } 528 529 static void board_clock_init(void) 530 { 531 struct exynos4_clock *clk = 532 (struct exynos4_clock *)samsung_get_base_clock(); 533 534 writel(CLK_SRC_CPU_VAL, (unsigned int)&clk->src_cpu); 535 writel(CLK_SRC_TOP0_VAL, (unsigned int)&clk->src_top0); 536 writel(CLK_SRC_FSYS_VAL, (unsigned int)&clk->src_fsys); 537 writel(CLK_SRC_PERIL0_VAL, (unsigned int)&clk->src_peril0); 538 539 writel(CLK_DIV_CPU0_VAL, (unsigned int)&clk->div_cpu0); 540 writel(CLK_DIV_CPU1_VAL, (unsigned int)&clk->div_cpu1); 541 writel(CLK_DIV_DMC0_VAL, (unsigned int)&clk->div_dmc0); 542 writel(CLK_DIV_DMC1_VAL, (unsigned int)&clk->div_dmc1); 543 writel(CLK_DIV_LEFTBUS_VAL, (unsigned int)&clk->div_leftbus); 544 writel(CLK_DIV_RIGHTBUS_VAL, (unsigned int)&clk->div_rightbus); 545 writel(CLK_DIV_TOP_VAL, (unsigned int)&clk->div_top); 546 writel(CLK_DIV_FSYS1_VAL, (unsigned int)&clk->div_fsys1); 547 writel(CLK_DIV_FSYS2_VAL, (unsigned int)&clk->div_fsys2); 548 writel(CLK_DIV_FSYS3_VAL, (unsigned int)&clk->div_fsys3); 549 writel(CLK_DIV_PERIL0_VAL, (unsigned int)&clk->div_peril0); 550 writel(CLK_DIV_PERIL3_VAL, (unsigned int)&clk->div_peril3); 551 552 writel(PLL_LOCKTIME, (unsigned int)&clk->apll_lock); 553 writel(PLL_LOCKTIME, (unsigned int)&clk->mpll_lock); 554 writel(PLL_LOCKTIME, (unsigned int)&clk->epll_lock); 555 writel(PLL_LOCKTIME, (unsigned int)&clk->vpll_lock); 556 writel(APLL_CON1_VAL, (unsigned int)&clk->apll_con1); 557 writel(APLL_CON0_VAL, (unsigned int)&clk->apll_con0); 558 writel(MPLL_CON1_VAL, (unsigned int)&clk->mpll_con1); 559 writel(MPLL_CON0_VAL, (unsigned int)&clk->mpll_con0); 560 writel(EPLL_CON1_VAL, (unsigned int)&clk->epll_con1); 561 writel(EPLL_CON0_VAL, (unsigned int)&clk->epll_con0); 562 writel(VPLL_CON1_VAL, (unsigned int)&clk->vpll_con1); 563 writel(VPLL_CON0_VAL, (unsigned int)&clk->vpll_con0); 564 565 writel(CLK_GATE_IP_CAM_VAL, (unsigned int)&clk->gate_ip_cam); 566 writel(CLK_GATE_IP_VP_VAL, (unsigned int)&clk->gate_ip_tv); 567 writel(CLK_GATE_IP_MFC_VAL, (unsigned int)&clk->gate_ip_mfc); 568 writel(CLK_GATE_IP_G3D_VAL, (unsigned int)&clk->gate_ip_g3d); 569 writel(CLK_GATE_IP_IMAGE_VAL, (unsigned int)&clk->gate_ip_image); 570 writel(CLK_GATE_IP_LCD0_VAL, (unsigned int)&clk->gate_ip_lcd0); 571 writel(CLK_GATE_IP_LCD1_VAL, (unsigned int)&clk->gate_ip_lcd1); 572 writel(CLK_GATE_IP_FSYS_VAL, (unsigned int)&clk->gate_ip_fsys); 573 writel(CLK_GATE_IP_GPS_VAL, (unsigned int)&clk->gate_ip_gps); 574 writel(CLK_GATE_IP_PERIL_VAL, (unsigned int)&clk->gate_ip_peril); 575 writel(CLK_GATE_IP_PERIR_VAL, (unsigned int)&clk->gate_ip_perir); 576 writel(CLK_GATE_BLOCK_VAL, (unsigned int)&clk->gate_block); 577 } 578 579 static void board_power_init(void) 580 { 581 struct exynos4_power *pwr = 582 (struct exynos4_power *)samsung_get_base_power(); 583 584 /* PS HOLD */ 585 writel(EXYNOS4_PS_HOLD_CON_VAL, (unsigned int)&pwr->ps_hold_control); 586 587 /* Set power down */ 588 writel(0, (unsigned int)&pwr->cam_configuration); 589 writel(0, (unsigned int)&pwr->tv_configuration); 590 writel(0, (unsigned int)&pwr->mfc_configuration); 591 writel(0, (unsigned int)&pwr->g3d_configuration); 592 writel(0, (unsigned int)&pwr->lcd1_configuration); 593 writel(0, (unsigned int)&pwr->gps_configuration); 594 writel(0, (unsigned int)&pwr->gps_alive_configuration); 595 596 /* It is necessary to power down core 1 */ 597 /* to successfully boot CPU1 in kernel */ 598 writel(0, (unsigned int)&pwr->arm_core1_configuration); 599 } 600 601 static void board_uart_init(void) 602 { 603 struct exynos4_gpio_part1 *gpio1 = 604 (struct exynos4_gpio_part1 *)samsung_get_base_gpio_part1(); 605 struct exynos4_gpio_part2 *gpio2 = 606 (struct exynos4_gpio_part2 *)samsung_get_base_gpio_part2(); 607 int i; 608 609 /* 610 * UART2 GPIOs 611 * GPA1CON[0] = UART_2_RXD(2) 612 * GPA1CON[1] = UART_2_TXD(2) 613 * GPA1CON[2] = I2C_3_SDA (3) 614 * GPA1CON[3] = I2C_3_SCL (3) 615 */ 616 617 for (i = 0; i < 4; i++) { 618 s5p_gpio_set_pull(&gpio1->a1, i, GPIO_PULL_NONE); 619 s5p_gpio_cfg_pin(&gpio1->a1, i, GPIO_FUNC((i > 1) ? 0x3 : 0x2)); 620 } 621 622 /* UART_SEL GPY4[7] (part2) at EXYNOS4 */ 623 s5p_gpio_set_pull(&gpio2->y4, 7, GPIO_PULL_UP); 624 s5p_gpio_direction_output(&gpio2->y4, 7, 1); 625 } 626 627 int board_early_init_f(void) 628 { 629 wdt_stop(); 630 pmic_reset(); 631 board_clock_init(); 632 board_uart_init(); 633 board_power_init(); 634 635 return 0; 636 } 637 638 void exynos_reset_lcd(void) 639 { 640 struct exynos4_gpio_part2 *gpio2 = 641 (struct exynos4_gpio_part2 *)samsung_get_base_gpio_part2(); 642 643 s5p_gpio_direction_output(&gpio2->y4, 5, 1); 644 udelay(10000); 645 s5p_gpio_direction_output(&gpio2->y4, 5, 0); 646 udelay(10000); 647 s5p_gpio_direction_output(&gpio2->y4, 5, 1); 648 } 649 650 static int lcd_power(void) 651 { 652 int ret = 0; 653 struct pmic *p = pmic_get("MAX8997_PMIC"); 654 if (!p) 655 return -ENODEV; 656 657 if (pmic_probe(p)) 658 return 0; 659 660 /* LDO15 voltage: 2.2v */ 661 ret |= pmic_reg_write(p, MAX8997_REG_LDO15CTRL, 0x1c | EN_LDO); 662 /* LDO13 voltage: 3.0v */ 663 ret |= pmic_reg_write(p, MAX8997_REG_LDO13CTRL, 0x2c | EN_LDO); 664 665 if (ret) { 666 puts("MAX8997 LDO setting error!\n"); 667 return -1; 668 } 669 670 return 0; 671 } 672 673 static struct mipi_dsim_config dsim_config = { 674 .e_interface = DSIM_VIDEO, 675 .e_virtual_ch = DSIM_VIRTUAL_CH_0, 676 .e_pixel_format = DSIM_24BPP_888, 677 .e_burst_mode = DSIM_BURST_SYNC_EVENT, 678 .e_no_data_lane = DSIM_DATA_LANE_4, 679 .e_byte_clk = DSIM_PLL_OUT_DIV8, 680 .hfp = 1, 681 682 .p = 3, 683 .m = 120, 684 .s = 1, 685 686 /* D-PHY PLL stable time spec :min = 200usec ~ max 400usec */ 687 .pll_stable_time = 500, 688 689 /* escape clk : 10MHz */ 690 .esc_clk = 20 * 1000000, 691 692 /* stop state holding counter after bta change count 0 ~ 0xfff */ 693 .stop_holding_cnt = 0x7ff, 694 /* bta timeout 0 ~ 0xff */ 695 .bta_timeout = 0xff, 696 /* lp rx timeout 0 ~ 0xffff */ 697 .rx_timeout = 0xffff, 698 }; 699 700 static struct exynos_platform_mipi_dsim s6e8ax0_platform_data = { 701 .lcd_panel_info = NULL, 702 .dsim_config = &dsim_config, 703 }; 704 705 static struct mipi_dsim_lcd_device mipi_lcd_device = { 706 .name = "s6e8ax0", 707 .id = -1, 708 .bus_id = 0, 709 .platform_data = (void *)&s6e8ax0_platform_data, 710 }; 711 712 static int mipi_power(void) 713 { 714 int ret = 0; 715 struct pmic *p = pmic_get("MAX8997_PMIC"); 716 if (!p) 717 return -ENODEV; 718 719 if (pmic_probe(p)) 720 return 0; 721 722 /* LDO3 voltage: 1.1v */ 723 ret |= pmic_reg_write(p, MAX8997_REG_LDO3CTRL, 0x6 | EN_LDO); 724 /* LDO4 voltage: 1.8v */ 725 ret |= pmic_reg_write(p, MAX8997_REG_LDO4CTRL, 0x14 | EN_LDO); 726 727 if (ret) { 728 puts("MAX8997 LDO setting error!\n"); 729 return -1; 730 } 731 732 return 0; 733 } 734 735 vidinfo_t panel_info = { 736 .vl_freq = 60, 737 .vl_col = 720, 738 .vl_row = 1280, 739 .vl_width = 720, 740 .vl_height = 1280, 741 .vl_clkp = CONFIG_SYS_HIGH, 742 .vl_hsp = CONFIG_SYS_LOW, 743 .vl_vsp = CONFIG_SYS_LOW, 744 .vl_dp = CONFIG_SYS_LOW, 745 .vl_bpix = 5, /* Bits per pixel, 2^5 = 32 */ 746 747 /* s6e8ax0 Panel infomation */ 748 .vl_hspw = 5, 749 .vl_hbpd = 10, 750 .vl_hfpd = 10, 751 752 .vl_vspw = 2, 753 .vl_vbpd = 1, 754 .vl_vfpd = 13, 755 .vl_cmd_allow_len = 0xf, 756 757 .win_id = 3, 758 .dual_lcd_enabled = 0, 759 760 .init_delay = 0, 761 .power_on_delay = 0, 762 .reset_delay = 0, 763 .interface_mode = FIMD_RGB_INTERFACE, 764 .mipi_enabled = 1, 765 }; 766 767 void init_panel_info(vidinfo_t *vid) 768 { 769 vid->logo_on = 1, 770 vid->resolution = HD_RESOLUTION, 771 vid->rgb_mode = MODE_RGB_P, 772 773 #ifdef CONFIG_TIZEN 774 get_tizen_logo_info(vid); 775 #endif 776 777 if (hwrevision(2)) 778 mipi_lcd_device.reverse_panel = 1; 779 780 strcpy(s6e8ax0_platform_data.lcd_panel_name, mipi_lcd_device.name); 781 s6e8ax0_platform_data.lcd_power = lcd_power; 782 s6e8ax0_platform_data.mipi_power = mipi_power; 783 s6e8ax0_platform_data.phy_enable = set_mipi_phy_ctrl; 784 s6e8ax0_platform_data.lcd_panel_info = (void *)vid; 785 exynos_mipi_dsi_register_lcd_device(&mipi_lcd_device); 786 s6e8ax0_init(); 787 exynos_set_dsim_platform_data(&s6e8ax0_platform_data); 788 789 setenv("lcdinfo", "lcd=s6e8ax0"); 790 } 791 792 #ifdef CONFIG_USB_GADGET_MASS_STORAGE 793 static int ums_read_sector(struct ums_device *ums_dev, 794 ulong start, lbaint_t blkcnt, void *buf) 795 { 796 if (ums_dev->mmc->block_dev.block_read(ums_dev->dev_num, 797 start + ums_dev->offset, blkcnt, buf) != blkcnt) 798 return -1; 799 800 return 0; 801 } 802 803 static int ums_write_sector(struct ums_device *ums_dev, 804 ulong start, lbaint_t blkcnt, const void *buf) 805 { 806 if (ums_dev->mmc->block_dev.block_write(ums_dev->dev_num, 807 start + ums_dev->offset, blkcnt, buf) != blkcnt) 808 return -1; 809 810 return 0; 811 } 812 813 static void ums_get_capacity(struct ums_device *ums_dev, 814 long long int *capacity) 815 { 816 long long int tmp_capacity; 817 818 tmp_capacity = (long long int) ((ums_dev->offset + ums_dev->part_size) 819 * SECTOR_SIZE); 820 *capacity = ums_dev->mmc->capacity - tmp_capacity; 821 } 822 823 static struct ums_board_info ums_board = { 824 .read_sector = ums_read_sector, 825 .write_sector = ums_write_sector, 826 .get_capacity = ums_get_capacity, 827 .name = "TRATS UMS disk", 828 .ums_dev = { 829 .mmc = NULL, 830 .dev_num = 0, 831 .offset = 0, 832 .part_size = 0. 833 }, 834 }; 835 836 struct ums_board_info *board_ums_init(unsigned int dev_num, unsigned int offset, 837 unsigned int part_size) 838 { 839 struct mmc *mmc; 840 841 mmc = find_mmc_device(dev_num); 842 if (!mmc) 843 return NULL; 844 845 ums_board.ums_dev.mmc = mmc; 846 ums_board.ums_dev.dev_num = dev_num; 847 ums_board.ums_dev.offset = offset; 848 ums_board.ums_dev.part_size = part_size; 849 850 return &ums_board; 851 } 852 #endif 853