1 /* 2 * Copyright (C) 2011 Samsung Electronics 3 * Heungjun Kim <riverful.kim@samsung.com> 4 * Kyungmin Park <kyungmin.park@samsung.com> 5 * Donghwa Lee <dh09.lee@samsung.com> 6 * 7 * See file CREDITS for list of people who contributed to this 8 * project. 9 * 10 * This program is free software; you can redistribute it and/or 11 * modify it under the terms of the GNU General Public License as 12 * published by the Free Software Foundation; either version 2 of 13 * the License, or (at your option) any later version. 14 * 15 * This program is distributed in the hope that it will be useful, 16 * but WITHOUT ANY WARRANTY; without even the implied warranty of 17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 18 * GNU General Public License for more details. 19 * 20 * You should have received a copy of the GNU General Public License 21 * along with this program; if not, write to the Free Software 22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 23 * MA 02111-1307 USA 24 */ 25 26 #include <common.h> 27 #include <lcd.h> 28 #include <asm/io.h> 29 #include <asm/arch/cpu.h> 30 #include <asm/arch/gpio.h> 31 #include <asm/arch/mmc.h> 32 #include <asm/arch/clock.h> 33 #include <asm/arch/clk.h> 34 #include <asm/arch/mipi_dsim.h> 35 #include <asm/arch/watchdog.h> 36 #include <asm/arch/power.h> 37 #include <power/pmic.h> 38 #include <usb/s3c_udc.h> 39 #include <power/max8997_pmic.h> 40 #include <libtizen.h> 41 #include <power/max8997_muic.h> 42 #include <power/battery.h> 43 #include <power/max17042_fg.h> 44 45 #include "setup.h" 46 47 DECLARE_GLOBAL_DATA_PTR; 48 49 unsigned int board_rev; 50 51 #ifdef CONFIG_REVISION_TAG 52 u32 get_board_rev(void) 53 { 54 return board_rev; 55 } 56 #endif 57 58 static void check_hw_revision(void); 59 60 static int hwrevision(int rev) 61 { 62 return (board_rev & 0xf) == rev; 63 } 64 65 struct s3c_plat_otg_data s5pc210_otg_data; 66 67 int board_init(void) 68 { 69 gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100; 70 71 check_hw_revision(); 72 printf("HW Revision:\t0x%x\n", board_rev); 73 74 return 0; 75 } 76 77 void i2c_init_board(void) 78 { 79 struct exynos4_gpio_part1 *gpio1 = 80 (struct exynos4_gpio_part1 *)samsung_get_base_gpio_part1(); 81 struct exynos4_gpio_part2 *gpio2 = 82 (struct exynos4_gpio_part2 *)samsung_get_base_gpio_part2(); 83 84 /* I2C_5 -> PMIC */ 85 s5p_gpio_direction_output(&gpio1->b, 7, 1); 86 s5p_gpio_direction_output(&gpio1->b, 6, 1); 87 /* I2C_9 -> FG */ 88 s5p_gpio_direction_output(&gpio2->y4, 0, 1); 89 s5p_gpio_direction_output(&gpio2->y4, 1, 1); 90 } 91 92 static void trats_low_power_mode(void) 93 { 94 struct exynos4_clock *clk = 95 (struct exynos4_clock *)samsung_get_base_clock(); 96 struct exynos4_power *pwr = 97 (struct exynos4_power *)samsung_get_base_power(); 98 99 /* Power down CORE1 */ 100 /* LOCAL_PWR_CFG [1:0] 0x3 EN, 0x0 DIS */ 101 writel(0x0, &pwr->arm_core1_configuration); 102 103 /* Change the APLL frequency */ 104 /* ENABLE (1 enable) | LOCKED (1 locked) */ 105 /* [31] | [29] */ 106 /* FSEL | MDIV | PDIV | SDIV */ 107 /* [27] | [25:16] | [13:8] | [2:0] */ 108 writel(0xa0c80604, &clk->apll_con0); 109 110 /* Change CPU0 clock divider */ 111 /* CORE2_RATIO | APLL_RATIO | PCLK_DBG_RATIO | ATB_RATIO */ 112 /* [30:28] | [26:24] | [22:20] | [18:16] */ 113 /* PERIPH_RATIO | COREM1_RATIO | COREM0_RATIO | CORE_RATIO */ 114 /* [14:12] | [10:8] | [6:4] | [2:0] */ 115 writel(0x00000100, &clk->div_cpu0); 116 117 /* CLK_DIV_STAT_CPU0 - wait until clock gets stable (0 = stable) */ 118 while (readl(&clk->div_stat_cpu0) & 0x1111111) 119 continue; 120 121 /* Change clock divider ratio for DMC */ 122 /* DMCP_RATIO | DMCD_RATIO */ 123 /* [22:20] | [18:16] */ 124 /* DMC_RATIO | DPHY_RATIO | ACP_PCLK_RATIO | ACP_RATIO */ 125 /* [14:12] | [10:8] | [6:4] | [2:0] */ 126 writel(0x13113117, &clk->div_dmc0); 127 128 /* CLK_DIV_STAT_DMC0 - wait until clock gets stable (0 = stable) */ 129 while (readl(&clk->div_stat_dmc0) & 0x11111111) 130 continue; 131 132 /* Turn off unnecessary power domains */ 133 writel(0x0, &pwr->xxti_configuration); /* XXTI */ 134 writel(0x0, &pwr->cam_configuration); /* CAM */ 135 writel(0x0, &pwr->tv_configuration); /* TV */ 136 writel(0x0, &pwr->mfc_configuration); /* MFC */ 137 writel(0x0, &pwr->g3d_configuration); /* G3D */ 138 writel(0x0, &pwr->gps_configuration); /* GPS */ 139 writel(0x0, &pwr->gps_alive_configuration); /* GPS_ALIVE */ 140 141 /* Turn off unnecessary clocks */ 142 writel(0x0, &clk->gate_ip_cam); /* CAM */ 143 writel(0x0, &clk->gate_ip_tv); /* TV */ 144 writel(0x0, &clk->gate_ip_mfc); /* MFC */ 145 writel(0x0, &clk->gate_ip_g3d); /* G3D */ 146 writel(0x0, &clk->gate_ip_image); /* IMAGE */ 147 writel(0x0, &clk->gate_ip_gps); /* GPS */ 148 } 149 150 static int pmic_init_max8997(void) 151 { 152 struct pmic *p = pmic_get("MAX8997_PMIC"); 153 int i = 0, ret = 0; 154 u32 val; 155 156 if (pmic_probe(p)) 157 return -1; 158 159 /* BUCK1 VARM: 1.2V */ 160 val = (1200000 - 650000) / 25000; 161 ret |= pmic_reg_write(p, MAX8997_REG_BUCK1DVS1, val); 162 val = ENBUCK | ACTIVE_DISCHARGE; /* DVS OFF */ 163 ret |= pmic_reg_write(p, MAX8997_REG_BUCK1CTRL, val); 164 165 /* BUCK2 VINT: 1.1V */ 166 val = (1100000 - 650000) / 25000; 167 ret |= pmic_reg_write(p, MAX8997_REG_BUCK2DVS1, val); 168 val = ENBUCK | ACTIVE_DISCHARGE; /* DVS OFF */ 169 ret |= pmic_reg_write(p, MAX8997_REG_BUCK2CTRL, val); 170 171 172 /* BUCK3 G3D: 1.1V - OFF */ 173 ret |= pmic_reg_read(p, MAX8997_REG_BUCK3CTRL, &val); 174 val &= ~ENBUCK; 175 ret |= pmic_reg_write(p, MAX8997_REG_BUCK3CTRL, val); 176 177 val = (1100000 - 750000) / 50000; 178 ret |= pmic_reg_write(p, MAX8997_REG_BUCK3DVS, val); 179 180 /* BUCK4 CAMISP: 1.2V - OFF */ 181 ret |= pmic_reg_read(p, MAX8997_REG_BUCK4CTRL, &val); 182 val &= ~ENBUCK; 183 ret |= pmic_reg_write(p, MAX8997_REG_BUCK4CTRL, val); 184 185 val = (1200000 - 650000) / 25000; 186 ret |= pmic_reg_write(p, MAX8997_REG_BUCK4DVS, val); 187 188 /* BUCK5 VMEM: 1.2V */ 189 val = (1200000 - 650000) / 25000; 190 for (i = 0; i < 8; i++) 191 ret |= pmic_reg_write(p, MAX8997_REG_BUCK5DVS1 + i, val); 192 193 val = ENBUCK | ACTIVE_DISCHARGE; /* DVS OFF */ 194 ret |= pmic_reg_write(p, MAX8997_REG_BUCK5CTRL, val); 195 196 /* BUCK6 CAM AF: 2.8V */ 197 /* No Voltage Setting Register */ 198 /* GNSLCT 3.0X */ 199 val = GNSLCT; 200 ret |= pmic_reg_write(p, MAX8997_REG_BUCK6CTRL, val); 201 202 /* BUCK7 VCC_SUB: 2.0V */ 203 val = (2000000 - 750000) / 50000; 204 ret |= pmic_reg_write(p, MAX8997_REG_BUCK7DVS, val); 205 206 /* LDO1 VADC: 3.3V */ 207 val = max8997_reg_ldo(3300000) | DIS_LDO; /* OFF */ 208 ret |= pmic_reg_write(p, MAX8997_REG_LDO1CTRL, val); 209 210 /* LDO1 Disable active discharging */ 211 ret |= pmic_reg_read(p, MAX8997_REG_LDO1CONFIG, &val); 212 val &= ~LDO_ADE; 213 ret |= pmic_reg_write(p, MAX8997_REG_LDO1CONFIG, val); 214 215 /* LDO2 VALIVE: 1.1V */ 216 val = max8997_reg_ldo(1100000) | EN_LDO; 217 ret |= pmic_reg_write(p, MAX8997_REG_LDO2CTRL, val); 218 219 /* LDO3 VUSB/MIPI: 1.1V */ 220 val = max8997_reg_ldo(1100000) | DIS_LDO; /* OFF */ 221 ret |= pmic_reg_write(p, MAX8997_REG_LDO3CTRL, val); 222 223 /* LDO4 VMIPI: 1.8V */ 224 val = max8997_reg_ldo(1800000) | DIS_LDO; /* OFF */ 225 ret |= pmic_reg_write(p, MAX8997_REG_LDO4CTRL, val); 226 227 /* LDO5 VHSIC: 1.2V */ 228 val = max8997_reg_ldo(1200000) | DIS_LDO; /* OFF */ 229 ret |= pmic_reg_write(p, MAX8997_REG_LDO5CTRL, val); 230 231 /* LDO6 VCC_1.8V_PDA: 1.8V */ 232 val = max8997_reg_ldo(1800000) | EN_LDO; 233 ret |= pmic_reg_write(p, MAX8997_REG_LDO6CTRL, val); 234 235 /* LDO7 CAM_ISP: 1.8V */ 236 val = max8997_reg_ldo(1800000) | DIS_LDO; /* OFF */ 237 ret |= pmic_reg_write(p, MAX8997_REG_LDO7CTRL, val); 238 239 /* LDO8 VDAC/VUSB: 3.3V */ 240 val = max8997_reg_ldo(3300000) | DIS_LDO; /* OFF */ 241 ret |= pmic_reg_write(p, MAX8997_REG_LDO8CTRL, val); 242 243 /* LDO9 VCC_2.8V_PDA: 2.8V */ 244 val = max8997_reg_ldo(2800000) | EN_LDO; 245 ret |= pmic_reg_write(p, MAX8997_REG_LDO9CTRL, val); 246 247 /* LDO10 VPLL: 1.1V */ 248 val = max8997_reg_ldo(1100000) | EN_LDO; 249 ret |= pmic_reg_write(p, MAX8997_REG_LDO10CTRL, val); 250 251 /* LDO11 TOUCH: 2.8V */ 252 val = max8997_reg_ldo(2800000) | DIS_LDO; /* OFF */ 253 ret |= pmic_reg_write(p, MAX8997_REG_LDO11CTRL, val); 254 255 /* LDO12 VTCAM: 1.8V */ 256 val = max8997_reg_ldo(1800000) | DIS_LDO; /* OFF */ 257 ret |= pmic_reg_write(p, MAX8997_REG_LDO12CTRL, val); 258 259 /* LDO13 VCC_3.0_LCD: 3.0V */ 260 val = max8997_reg_ldo(3000000) | DIS_LDO; /* OFF */ 261 ret |= pmic_reg_write(p, MAX8997_REG_LDO13CTRL, val); 262 263 /* LDO14 MOTOR: 3.0V */ 264 val = max8997_reg_ldo(3000000) | DIS_LDO; /* OFF */ 265 ret |= pmic_reg_write(p, MAX8997_REG_LDO14CTRL, val); 266 267 /* LDO15 LED_A: 2.8V */ 268 val = max8997_reg_ldo(2800000) | DIS_LDO; /* OFF */ 269 ret |= pmic_reg_write(p, MAX8997_REG_LDO15CTRL, val); 270 271 /* LDO16 CAM_SENSOR: 1.8V */ 272 val = max8997_reg_ldo(1800000) | DIS_LDO; /* OFF */ 273 ret |= pmic_reg_write(p, MAX8997_REG_LDO16CTRL, val); 274 275 /* LDO17 VTF: 2.8V */ 276 val = max8997_reg_ldo(2800000) | DIS_LDO; /* OFF */ 277 ret |= pmic_reg_write(p, MAX8997_REG_LDO17CTRL, val); 278 279 /* LDO18 TOUCH_LED 3.3V */ 280 val = max8997_reg_ldo(3300000) | DIS_LDO; /* OFF */ 281 ret |= pmic_reg_write(p, MAX8997_REG_LDO18CTRL, val); 282 283 /* LDO21 VDDQ: 1.2V */ 284 val = max8997_reg_ldo(1200000) | EN_LDO; 285 ret |= pmic_reg_write(p, MAX8997_REG_LDO21CTRL, val); 286 287 /* SAFEOUT for both 1 and 2: 4.9V, Active discharge, Enable */ 288 val = (SAFEOUT_4_90V << 0) | (SAFEOUT_4_90V << 2) | 289 ACTDISSAFEO1 | ACTDISSAFEO2 | ENSAFEOUT1 | ENSAFEOUT2; 290 ret |= pmic_reg_write(p, MAX8997_REG_SAFEOUTCTRL, val); 291 292 if (ret) { 293 puts("MAX8997 PMIC setting error!\n"); 294 return -1; 295 } 296 return 0; 297 } 298 299 int power_init_board(void) 300 { 301 int chrg, ret; 302 struct power_battery *pb; 303 struct pmic *p_fg, *p_chrg, *p_muic, *p_bat; 304 305 ret = pmic_init(I2C_5); 306 ret |= pmic_init_max8997(); 307 ret |= power_fg_init(I2C_9); 308 ret |= power_muic_init(I2C_5); 309 ret |= power_bat_init(0); 310 if (ret) 311 return ret; 312 313 p_fg = pmic_get("MAX17042_FG"); 314 if (!p_fg) { 315 puts("MAX17042_FG: Not found\n"); 316 return -ENODEV; 317 } 318 319 p_chrg = pmic_get("MAX8997_PMIC"); 320 if (!p_chrg) { 321 puts("MAX8997_PMIC: Not found\n"); 322 return -ENODEV; 323 } 324 325 p_muic = pmic_get("MAX8997_MUIC"); 326 if (!p_muic) { 327 puts("MAX8997_MUIC: Not found\n"); 328 return -ENODEV; 329 } 330 331 p_bat = pmic_get("BAT_TRATS"); 332 if (!p_bat) { 333 puts("BAT_TRATS: Not found\n"); 334 return -ENODEV; 335 } 336 337 p_fg->parent = p_bat; 338 p_chrg->parent = p_bat; 339 p_muic->parent = p_bat; 340 341 p_bat->low_power_mode = trats_low_power_mode; 342 p_bat->pbat->battery_init(p_bat, p_fg, p_chrg, p_muic); 343 344 pb = p_bat->pbat; 345 chrg = p_muic->chrg->chrg_type(p_muic); 346 debug("CHARGER TYPE: %d\n", chrg); 347 348 if (!p_chrg->chrg->chrg_bat_present(p_chrg)) { 349 puts("No battery detected\n"); 350 return -1; 351 } 352 353 p_fg->fg->fg_battery_check(p_fg, p_bat); 354 355 if (pb->bat->state == CHARGE && chrg == CHARGER_USB) 356 puts("CHARGE Battery !\n"); 357 358 return 0; 359 } 360 361 int dram_init(void) 362 { 363 gd->ram_size = get_ram_size((long *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE) + 364 get_ram_size((long *)PHYS_SDRAM_2, PHYS_SDRAM_2_SIZE); 365 366 return 0; 367 } 368 369 void dram_init_banksize(void) 370 { 371 gd->bd->bi_dram[0].start = PHYS_SDRAM_1; 372 gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; 373 gd->bd->bi_dram[1].start = PHYS_SDRAM_2; 374 gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE; 375 } 376 377 static unsigned int get_hw_revision(void) 378 { 379 struct exynos4_gpio_part1 *gpio = 380 (struct exynos4_gpio_part1 *)samsung_get_base_gpio_part1(); 381 int hwrev = 0; 382 int i; 383 384 /* hw_rev[3:0] == GPE1[3:0] */ 385 for (i = 0; i < 4; i++) { 386 s5p_gpio_cfg_pin(&gpio->e1, i, GPIO_INPUT); 387 s5p_gpio_set_pull(&gpio->e1, i, GPIO_PULL_NONE); 388 } 389 390 udelay(1); 391 392 for (i = 0; i < 4; i++) 393 hwrev |= (s5p_gpio_get_value(&gpio->e1, i) << i); 394 395 debug("hwrev 0x%x\n", hwrev); 396 397 return hwrev; 398 } 399 400 static void check_hw_revision(void) 401 { 402 int hwrev; 403 404 hwrev = get_hw_revision(); 405 406 board_rev |= hwrev; 407 } 408 409 #ifdef CONFIG_DISPLAY_BOARDINFO 410 int checkboard(void) 411 { 412 puts("Board:\tTRATS\n"); 413 return 0; 414 } 415 #endif 416 417 #ifdef CONFIG_GENERIC_MMC 418 int board_mmc_init(bd_t *bis) 419 { 420 struct exynos4_gpio_part2 *gpio = 421 (struct exynos4_gpio_part2 *)samsung_get_base_gpio_part2(); 422 int i, err; 423 424 /* eMMC_EN: SD_0_CDn: GPK0[2] Output High */ 425 s5p_gpio_direction_output(&gpio->k0, 2, 1); 426 s5p_gpio_set_pull(&gpio->k0, 2, GPIO_PULL_NONE); 427 428 /* 429 * eMMC GPIO: 430 * SDR 8-bit@48MHz at MMC0 431 * GPK0[0] SD_0_CLK(2) 432 * GPK0[1] SD_0_CMD(2) 433 * GPK0[2] SD_0_CDn -> Not used 434 * GPK0[3:6] SD_0_DATA[0:3](2) 435 * GPK1[3:6] SD_0_DATA[0:3](3) 436 * 437 * DDR 4-bit@26MHz at MMC4 438 * GPK0[0] SD_4_CLK(3) 439 * GPK0[1] SD_4_CMD(3) 440 * GPK0[2] SD_4_CDn -> Not used 441 * GPK0[3:6] SD_4_DATA[0:3](3) 442 * GPK1[3:6] SD_4_DATA[4:7](4) 443 */ 444 for (i = 0; i < 7; i++) { 445 if (i == 2) 446 continue; 447 /* GPK0[0:6] special function 2 */ 448 s5p_gpio_cfg_pin(&gpio->k0, i, 0x2); 449 /* GPK0[0:6] pull disable */ 450 s5p_gpio_set_pull(&gpio->k0, i, GPIO_PULL_NONE); 451 /* GPK0[0:6] drv 4x */ 452 s5p_gpio_set_drv(&gpio->k0, i, GPIO_DRV_4X); 453 } 454 455 for (i = 3; i < 7; i++) { 456 /* GPK1[3:6] special function 3 */ 457 s5p_gpio_cfg_pin(&gpio->k1, i, 0x3); 458 /* GPK1[3:6] pull disable */ 459 s5p_gpio_set_pull(&gpio->k1, i, GPIO_PULL_NONE); 460 /* GPK1[3:6] drv 4x */ 461 s5p_gpio_set_drv(&gpio->k1, i, GPIO_DRV_4X); 462 } 463 464 /* 465 * MMC device init 466 * mmc0 : eMMC (8-bit buswidth) 467 * mmc2 : SD card (4-bit buswidth) 468 */ 469 err = s5p_mmc_init(0, 8); 470 471 /* T-flash detect */ 472 s5p_gpio_cfg_pin(&gpio->x3, 4, 0xf); 473 s5p_gpio_set_pull(&gpio->x3, 4, GPIO_PULL_UP); 474 475 /* 476 * Check the T-flash detect pin 477 * GPX3[4] T-flash detect pin 478 */ 479 if (!s5p_gpio_get_value(&gpio->x3, 4)) { 480 /* 481 * SD card GPIO: 482 * GPK2[0] SD_2_CLK(2) 483 * GPK2[1] SD_2_CMD(2) 484 * GPK2[2] SD_2_CDn -> Not used 485 * GPK2[3:6] SD_2_DATA[0:3](2) 486 */ 487 for (i = 0; i < 7; i++) { 488 if (i == 2) 489 continue; 490 /* GPK2[0:6] special function 2 */ 491 s5p_gpio_cfg_pin(&gpio->k2, i, 0x2); 492 /* GPK2[0:6] pull disable */ 493 s5p_gpio_set_pull(&gpio->k2, i, GPIO_PULL_NONE); 494 /* GPK2[0:6] drv 4x */ 495 s5p_gpio_set_drv(&gpio->k2, i, GPIO_DRV_4X); 496 } 497 err = s5p_mmc_init(2, 4); 498 } 499 500 return err; 501 } 502 #endif 503 504 #ifdef CONFIG_USB_GADGET 505 static int s5pc210_phy_control(int on) 506 { 507 int ret = 0; 508 u32 val = 0; 509 struct pmic *p = pmic_get("MAX8997_PMIC"); 510 if (!p) 511 return -ENODEV; 512 513 if (pmic_probe(p)) 514 return -1; 515 516 if (on) { 517 ret |= pmic_set_output(p, MAX8997_REG_SAFEOUTCTRL, 518 ENSAFEOUT1, LDO_ON); 519 ret |= pmic_reg_read(p, MAX8997_REG_LDO3CTRL, &val); 520 ret |= pmic_reg_write(p, MAX8997_REG_LDO3CTRL, EN_LDO | val); 521 522 ret |= pmic_reg_read(p, MAX8997_REG_LDO8CTRL, &val); 523 ret |= pmic_reg_write(p, MAX8997_REG_LDO8CTRL, EN_LDO | val); 524 } else { 525 ret |= pmic_reg_read(p, MAX8997_REG_LDO8CTRL, &val); 526 ret |= pmic_reg_write(p, MAX8997_REG_LDO8CTRL, DIS_LDO | val); 527 528 ret |= pmic_reg_read(p, MAX8997_REG_LDO3CTRL, &val); 529 ret |= pmic_reg_write(p, MAX8997_REG_LDO3CTRL, DIS_LDO | val); 530 ret |= pmic_set_output(p, MAX8997_REG_SAFEOUTCTRL, 531 ENSAFEOUT1, LDO_OFF); 532 } 533 534 if (ret) { 535 puts("MAX8997 LDO setting error!\n"); 536 return -1; 537 } 538 539 return 0; 540 } 541 542 struct s3c_plat_otg_data s5pc210_otg_data = { 543 .phy_control = s5pc210_phy_control, 544 .regs_phy = EXYNOS4_USBPHY_BASE, 545 .regs_otg = EXYNOS4_USBOTG_BASE, 546 .usb_phy_ctrl = EXYNOS4_USBPHY_CONTROL, 547 .usb_flags = PHY0_SLEEP, 548 }; 549 550 void board_usb_init(void) 551 { 552 debug("USB_udc_probe\n"); 553 s3c_udc_probe(&s5pc210_otg_data); 554 } 555 #endif 556 557 static void pmic_reset(void) 558 { 559 struct exynos4_gpio_part2 *gpio = 560 (struct exynos4_gpio_part2 *)samsung_get_base_gpio_part2(); 561 562 s5p_gpio_direction_output(&gpio->x0, 7, 1); 563 s5p_gpio_set_pull(&gpio->x2, 7, GPIO_PULL_NONE); 564 } 565 566 static void board_clock_init(void) 567 { 568 struct exynos4_clock *clk = 569 (struct exynos4_clock *)samsung_get_base_clock(); 570 571 writel(CLK_SRC_CPU_VAL, (unsigned int)&clk->src_cpu); 572 writel(CLK_SRC_TOP0_VAL, (unsigned int)&clk->src_top0); 573 writel(CLK_SRC_FSYS_VAL, (unsigned int)&clk->src_fsys); 574 writel(CLK_SRC_PERIL0_VAL, (unsigned int)&clk->src_peril0); 575 576 writel(CLK_DIV_CPU0_VAL, (unsigned int)&clk->div_cpu0); 577 writel(CLK_DIV_CPU1_VAL, (unsigned int)&clk->div_cpu1); 578 writel(CLK_DIV_DMC0_VAL, (unsigned int)&clk->div_dmc0); 579 writel(CLK_DIV_DMC1_VAL, (unsigned int)&clk->div_dmc1); 580 writel(CLK_DIV_LEFTBUS_VAL, (unsigned int)&clk->div_leftbus); 581 writel(CLK_DIV_RIGHTBUS_VAL, (unsigned int)&clk->div_rightbus); 582 writel(CLK_DIV_TOP_VAL, (unsigned int)&clk->div_top); 583 writel(CLK_DIV_FSYS1_VAL, (unsigned int)&clk->div_fsys1); 584 writel(CLK_DIV_FSYS2_VAL, (unsigned int)&clk->div_fsys2); 585 writel(CLK_DIV_FSYS3_VAL, (unsigned int)&clk->div_fsys3); 586 writel(CLK_DIV_PERIL0_VAL, (unsigned int)&clk->div_peril0); 587 writel(CLK_DIV_PERIL3_VAL, (unsigned int)&clk->div_peril3); 588 589 writel(PLL_LOCKTIME, (unsigned int)&clk->apll_lock); 590 writel(PLL_LOCKTIME, (unsigned int)&clk->mpll_lock); 591 writel(PLL_LOCKTIME, (unsigned int)&clk->epll_lock); 592 writel(PLL_LOCKTIME, (unsigned int)&clk->vpll_lock); 593 writel(APLL_CON1_VAL, (unsigned int)&clk->apll_con1); 594 writel(APLL_CON0_VAL, (unsigned int)&clk->apll_con0); 595 writel(MPLL_CON1_VAL, (unsigned int)&clk->mpll_con1); 596 writel(MPLL_CON0_VAL, (unsigned int)&clk->mpll_con0); 597 writel(EPLL_CON1_VAL, (unsigned int)&clk->epll_con1); 598 writel(EPLL_CON0_VAL, (unsigned int)&clk->epll_con0); 599 writel(VPLL_CON1_VAL, (unsigned int)&clk->vpll_con1); 600 writel(VPLL_CON0_VAL, (unsigned int)&clk->vpll_con0); 601 602 writel(CLK_GATE_IP_CAM_VAL, (unsigned int)&clk->gate_ip_cam); 603 writel(CLK_GATE_IP_VP_VAL, (unsigned int)&clk->gate_ip_tv); 604 writel(CLK_GATE_IP_MFC_VAL, (unsigned int)&clk->gate_ip_mfc); 605 writel(CLK_GATE_IP_G3D_VAL, (unsigned int)&clk->gate_ip_g3d); 606 writel(CLK_GATE_IP_IMAGE_VAL, (unsigned int)&clk->gate_ip_image); 607 writel(CLK_GATE_IP_LCD0_VAL, (unsigned int)&clk->gate_ip_lcd0); 608 writel(CLK_GATE_IP_LCD1_VAL, (unsigned int)&clk->gate_ip_lcd1); 609 writel(CLK_GATE_IP_FSYS_VAL, (unsigned int)&clk->gate_ip_fsys); 610 writel(CLK_GATE_IP_GPS_VAL, (unsigned int)&clk->gate_ip_gps); 611 writel(CLK_GATE_IP_PERIL_VAL, (unsigned int)&clk->gate_ip_peril); 612 writel(CLK_GATE_IP_PERIR_VAL, (unsigned int)&clk->gate_ip_perir); 613 writel(CLK_GATE_BLOCK_VAL, (unsigned int)&clk->gate_block); 614 } 615 616 static void board_power_init(void) 617 { 618 struct exynos4_power *pwr = 619 (struct exynos4_power *)samsung_get_base_power(); 620 621 /* PS HOLD */ 622 writel(EXYNOS4_PS_HOLD_CON_VAL, (unsigned int)&pwr->ps_hold_control); 623 624 /* Set power down */ 625 writel(0, (unsigned int)&pwr->cam_configuration); 626 writel(0, (unsigned int)&pwr->tv_configuration); 627 writel(0, (unsigned int)&pwr->mfc_configuration); 628 writel(0, (unsigned int)&pwr->g3d_configuration); 629 writel(0, (unsigned int)&pwr->lcd1_configuration); 630 writel(0, (unsigned int)&pwr->gps_configuration); 631 writel(0, (unsigned int)&pwr->gps_alive_configuration); 632 } 633 634 static void board_uart_init(void) 635 { 636 struct exynos4_gpio_part1 *gpio1 = 637 (struct exynos4_gpio_part1 *)samsung_get_base_gpio_part1(); 638 struct exynos4_gpio_part2 *gpio2 = 639 (struct exynos4_gpio_part2 *)samsung_get_base_gpio_part2(); 640 int i; 641 642 /* 643 * UART2 GPIOs 644 * GPA1CON[0] = UART_2_RXD(2) 645 * GPA1CON[1] = UART_2_TXD(2) 646 * GPA1CON[2] = I2C_3_SDA (3) 647 * GPA1CON[3] = I2C_3_SCL (3) 648 */ 649 650 for (i = 0; i < 4; i++) { 651 s5p_gpio_set_pull(&gpio1->a1, i, GPIO_PULL_NONE); 652 s5p_gpio_cfg_pin(&gpio1->a1, i, GPIO_FUNC((i > 1) ? 0x3 : 0x2)); 653 } 654 655 /* UART_SEL GPY4[7] (part2) at EXYNOS4 */ 656 s5p_gpio_set_pull(&gpio2->y4, 7, GPIO_PULL_UP); 657 s5p_gpio_direction_output(&gpio2->y4, 7, 1); 658 } 659 660 int board_early_init_f(void) 661 { 662 wdt_stop(); 663 pmic_reset(); 664 board_clock_init(); 665 board_uart_init(); 666 board_power_init(); 667 668 return 0; 669 } 670 671 static void lcd_reset(void) 672 { 673 struct exynos4_gpio_part2 *gpio2 = 674 (struct exynos4_gpio_part2 *)samsung_get_base_gpio_part2(); 675 676 s5p_gpio_direction_output(&gpio2->y4, 5, 1); 677 udelay(10000); 678 s5p_gpio_direction_output(&gpio2->y4, 5, 0); 679 udelay(10000); 680 s5p_gpio_direction_output(&gpio2->y4, 5, 1); 681 } 682 683 static int lcd_power(void) 684 { 685 int ret = 0; 686 struct pmic *p = pmic_get("MAX8997_PMIC"); 687 if (!p) 688 return -ENODEV; 689 690 if (pmic_probe(p)) 691 return 0; 692 693 /* LDO15 voltage: 2.2v */ 694 ret |= pmic_reg_write(p, MAX8997_REG_LDO15CTRL, 0x1c | EN_LDO); 695 /* LDO13 voltage: 3.0v */ 696 ret |= pmic_reg_write(p, MAX8997_REG_LDO13CTRL, 0x2c | EN_LDO); 697 698 if (ret) { 699 puts("MAX8997 LDO setting error!\n"); 700 return -1; 701 } 702 703 return 0; 704 } 705 706 static struct mipi_dsim_config dsim_config = { 707 .e_interface = DSIM_VIDEO, 708 .e_virtual_ch = DSIM_VIRTUAL_CH_0, 709 .e_pixel_format = DSIM_24BPP_888, 710 .e_burst_mode = DSIM_BURST_SYNC_EVENT, 711 .e_no_data_lane = DSIM_DATA_LANE_4, 712 .e_byte_clk = DSIM_PLL_OUT_DIV8, 713 .hfp = 1, 714 715 .p = 3, 716 .m = 120, 717 .s = 1, 718 719 /* D-PHY PLL stable time spec :min = 200usec ~ max 400usec */ 720 .pll_stable_time = 500, 721 722 /* escape clk : 10MHz */ 723 .esc_clk = 20 * 1000000, 724 725 /* stop state holding counter after bta change count 0 ~ 0xfff */ 726 .stop_holding_cnt = 0x7ff, 727 /* bta timeout 0 ~ 0xff */ 728 .bta_timeout = 0xff, 729 /* lp rx timeout 0 ~ 0xffff */ 730 .rx_timeout = 0xffff, 731 }; 732 733 static struct exynos_platform_mipi_dsim s6e8ax0_platform_data = { 734 .lcd_panel_info = NULL, 735 .dsim_config = &dsim_config, 736 }; 737 738 static struct mipi_dsim_lcd_device mipi_lcd_device = { 739 .name = "s6e8ax0", 740 .id = -1, 741 .bus_id = 0, 742 .platform_data = (void *)&s6e8ax0_platform_data, 743 }; 744 745 static int mipi_power(void) 746 { 747 int ret = 0; 748 struct pmic *p = pmic_get("MAX8997_PMIC"); 749 if (!p) 750 return -ENODEV; 751 752 if (pmic_probe(p)) 753 return 0; 754 755 /* LDO3 voltage: 1.1v */ 756 ret |= pmic_reg_write(p, MAX8997_REG_LDO3CTRL, 0x6 | EN_LDO); 757 /* LDO4 voltage: 1.8v */ 758 ret |= pmic_reg_write(p, MAX8997_REG_LDO4CTRL, 0x14 | EN_LDO); 759 760 if (ret) { 761 puts("MAX8997 LDO setting error!\n"); 762 return -1; 763 } 764 765 return 0; 766 } 767 768 vidinfo_t panel_info = { 769 .vl_freq = 60, 770 .vl_col = 720, 771 .vl_row = 1280, 772 .vl_width = 720, 773 .vl_height = 1280, 774 .vl_clkp = CONFIG_SYS_HIGH, 775 .vl_hsp = CONFIG_SYS_LOW, 776 .vl_vsp = CONFIG_SYS_LOW, 777 .vl_dp = CONFIG_SYS_LOW, 778 .vl_bpix = 5, /* Bits per pixel, 2^5 = 32 */ 779 780 /* s6e8ax0 Panel infomation */ 781 .vl_hspw = 5, 782 .vl_hbpd = 10, 783 .vl_hfpd = 10, 784 785 .vl_vspw = 2, 786 .vl_vbpd = 1, 787 .vl_vfpd = 13, 788 .vl_cmd_allow_len = 0xf, 789 790 .win_id = 3, 791 .cfg_gpio = NULL, 792 .backlight_on = NULL, 793 .lcd_power_on = NULL, /* lcd_power_on in mipi dsi driver */ 794 .reset_lcd = lcd_reset, 795 .dual_lcd_enabled = 0, 796 797 .init_delay = 0, 798 .power_on_delay = 0, 799 .reset_delay = 0, 800 .interface_mode = FIMD_RGB_INTERFACE, 801 .mipi_enabled = 1, 802 }; 803 804 void init_panel_info(vidinfo_t *vid) 805 { 806 vid->logo_on = 1, 807 vid->resolution = HD_RESOLUTION, 808 vid->rgb_mode = MODE_RGB_P, 809 810 #ifdef CONFIG_TIZEN 811 get_tizen_logo_info(vid); 812 #endif 813 814 if (hwrevision(2)) 815 mipi_lcd_device.reverse_panel = 1; 816 817 strcpy(s6e8ax0_platform_data.lcd_panel_name, mipi_lcd_device.name); 818 s6e8ax0_platform_data.lcd_power = lcd_power; 819 s6e8ax0_platform_data.mipi_power = mipi_power; 820 s6e8ax0_platform_data.phy_enable = set_mipi_phy_ctrl; 821 s6e8ax0_platform_data.lcd_panel_info = (void *)vid; 822 exynos_mipi_dsi_register_lcd_device(&mipi_lcd_device); 823 s6e8ax0_init(); 824 exynos_set_dsim_platform_data(&s6e8ax0_platform_data); 825 826 setenv("lcdinfo", "lcd=s6e8ax0"); 827 } 828