1 /* 2 * Copyright (C) 2011 Samsung Electronics 3 * Heungjun Kim <riverful.kim@samsung.com> 4 * Kyungmin Park <kyungmin.park@samsung.com> 5 * Donghwa Lee <dh09.lee@samsung.com> 6 * 7 * SPDX-License-Identifier: GPL-2.0+ 8 */ 9 10 #include <common.h> 11 #include <lcd.h> 12 #include <asm/io.h> 13 #include <asm/arch/cpu.h> 14 #include <asm/arch/gpio.h> 15 #include <asm/arch/mmc.h> 16 #include <asm/arch/pinmux.h> 17 #include <asm/arch/clock.h> 18 #include <asm/arch/clk.h> 19 #include <asm/arch/mipi_dsim.h> 20 #include <asm/arch/watchdog.h> 21 #include <asm/arch/power.h> 22 #include <power/pmic.h> 23 #include <usb/s3c_udc.h> 24 #include <power/max8997_pmic.h> 25 #include <libtizen.h> 26 #include <power/max8997_muic.h> 27 #include <power/battery.h> 28 #include <power/max17042_fg.h> 29 #include <usb_mass_storage.h> 30 31 #include "setup.h" 32 33 DECLARE_GLOBAL_DATA_PTR; 34 35 unsigned int board_rev; 36 37 #ifdef CONFIG_REVISION_TAG 38 u32 get_board_rev(void) 39 { 40 return board_rev; 41 } 42 #endif 43 44 static void check_hw_revision(void); 45 struct s3c_plat_otg_data s5pc210_otg_data; 46 47 int board_init(void) 48 { 49 gd->bd->bi_boot_params = CONFIG_SYS_SPL_ARGS_ADDR; 50 51 check_hw_revision(); 52 printf("HW Revision:\t0x%x\n", board_rev); 53 54 return 0; 55 } 56 57 void i2c_init_board(void) 58 { 59 struct exynos4_gpio_part1 *gpio1 = 60 (struct exynos4_gpio_part1 *)samsung_get_base_gpio_part1(); 61 struct exynos4_gpio_part2 *gpio2 = 62 (struct exynos4_gpio_part2 *)samsung_get_base_gpio_part2(); 63 64 /* I2C_5 -> PMIC */ 65 s5p_gpio_direction_output(&gpio1->b, 7, 1); 66 s5p_gpio_direction_output(&gpio1->b, 6, 1); 67 /* I2C_9 -> FG */ 68 s5p_gpio_direction_output(&gpio2->y4, 0, 1); 69 s5p_gpio_direction_output(&gpio2->y4, 1, 1); 70 } 71 72 static void trats_low_power_mode(void) 73 { 74 struct exynos4_clock *clk = 75 (struct exynos4_clock *)samsung_get_base_clock(); 76 struct exynos4_power *pwr = 77 (struct exynos4_power *)samsung_get_base_power(); 78 79 /* Power down CORE1 */ 80 /* LOCAL_PWR_CFG [1:0] 0x3 EN, 0x0 DIS */ 81 writel(0x0, &pwr->arm_core1_configuration); 82 83 /* Change the APLL frequency */ 84 /* ENABLE (1 enable) | LOCKED (1 locked) */ 85 /* [31] | [29] */ 86 /* FSEL | MDIV | PDIV | SDIV */ 87 /* [27] | [25:16] | [13:8] | [2:0] */ 88 writel(0xa0c80604, &clk->apll_con0); 89 90 /* Change CPU0 clock divider */ 91 /* CORE2_RATIO | APLL_RATIO | PCLK_DBG_RATIO | ATB_RATIO */ 92 /* [30:28] | [26:24] | [22:20] | [18:16] */ 93 /* PERIPH_RATIO | COREM1_RATIO | COREM0_RATIO | CORE_RATIO */ 94 /* [14:12] | [10:8] | [6:4] | [2:0] */ 95 writel(0x00000100, &clk->div_cpu0); 96 97 /* CLK_DIV_STAT_CPU0 - wait until clock gets stable (0 = stable) */ 98 while (readl(&clk->div_stat_cpu0) & 0x1111111) 99 continue; 100 101 /* Change clock divider ratio for DMC */ 102 /* DMCP_RATIO | DMCD_RATIO */ 103 /* [22:20] | [18:16] */ 104 /* DMC_RATIO | DPHY_RATIO | ACP_PCLK_RATIO | ACP_RATIO */ 105 /* [14:12] | [10:8] | [6:4] | [2:0] */ 106 writel(0x13113117, &clk->div_dmc0); 107 108 /* CLK_DIV_STAT_DMC0 - wait until clock gets stable (0 = stable) */ 109 while (readl(&clk->div_stat_dmc0) & 0x11111111) 110 continue; 111 112 /* Turn off unnecessary power domains */ 113 writel(0x0, &pwr->xxti_configuration); /* XXTI */ 114 writel(0x0, &pwr->cam_configuration); /* CAM */ 115 writel(0x0, &pwr->tv_configuration); /* TV */ 116 writel(0x0, &pwr->mfc_configuration); /* MFC */ 117 writel(0x0, &pwr->g3d_configuration); /* G3D */ 118 writel(0x0, &pwr->gps_configuration); /* GPS */ 119 writel(0x0, &pwr->gps_alive_configuration); /* GPS_ALIVE */ 120 121 /* Turn off unnecessary clocks */ 122 writel(0x0, &clk->gate_ip_cam); /* CAM */ 123 writel(0x0, &clk->gate_ip_tv); /* TV */ 124 writel(0x0, &clk->gate_ip_mfc); /* MFC */ 125 writel(0x0, &clk->gate_ip_g3d); /* G3D */ 126 writel(0x0, &clk->gate_ip_image); /* IMAGE */ 127 writel(0x0, &clk->gate_ip_gps); /* GPS */ 128 } 129 130 static int pmic_init_max8997(void) 131 { 132 struct pmic *p = pmic_get("MAX8997_PMIC"); 133 int i = 0, ret = 0; 134 u32 val; 135 136 if (pmic_probe(p)) 137 return -1; 138 139 /* BUCK1 VARM: 1.2V */ 140 val = (1200000 - 650000) / 25000; 141 ret |= pmic_reg_write(p, MAX8997_REG_BUCK1DVS1, val); 142 val = ENBUCK | ACTIVE_DISCHARGE; /* DVS OFF */ 143 ret |= pmic_reg_write(p, MAX8997_REG_BUCK1CTRL, val); 144 145 /* BUCK2 VINT: 1.1V */ 146 val = (1100000 - 650000) / 25000; 147 ret |= pmic_reg_write(p, MAX8997_REG_BUCK2DVS1, val); 148 val = ENBUCK | ACTIVE_DISCHARGE; /* DVS OFF */ 149 ret |= pmic_reg_write(p, MAX8997_REG_BUCK2CTRL, val); 150 151 152 /* BUCK3 G3D: 1.1V - OFF */ 153 ret |= pmic_reg_read(p, MAX8997_REG_BUCK3CTRL, &val); 154 val &= ~ENBUCK; 155 ret |= pmic_reg_write(p, MAX8997_REG_BUCK3CTRL, val); 156 157 val = (1100000 - 750000) / 50000; 158 ret |= pmic_reg_write(p, MAX8997_REG_BUCK3DVS, val); 159 160 /* BUCK4 CAMISP: 1.2V - OFF */ 161 ret |= pmic_reg_read(p, MAX8997_REG_BUCK4CTRL, &val); 162 val &= ~ENBUCK; 163 ret |= pmic_reg_write(p, MAX8997_REG_BUCK4CTRL, val); 164 165 val = (1200000 - 650000) / 25000; 166 ret |= pmic_reg_write(p, MAX8997_REG_BUCK4DVS, val); 167 168 /* BUCK5 VMEM: 1.2V */ 169 val = (1200000 - 650000) / 25000; 170 for (i = 0; i < 8; i++) 171 ret |= pmic_reg_write(p, MAX8997_REG_BUCK5DVS1 + i, val); 172 173 val = ENBUCK | ACTIVE_DISCHARGE; /* DVS OFF */ 174 ret |= pmic_reg_write(p, MAX8997_REG_BUCK5CTRL, val); 175 176 /* BUCK6 CAM AF: 2.8V */ 177 /* No Voltage Setting Register */ 178 /* GNSLCT 3.0X */ 179 val = GNSLCT; 180 ret |= pmic_reg_write(p, MAX8997_REG_BUCK6CTRL, val); 181 182 /* BUCK7 VCC_SUB: 2.0V */ 183 val = (2000000 - 750000) / 50000; 184 ret |= pmic_reg_write(p, MAX8997_REG_BUCK7DVS, val); 185 186 /* LDO1 VADC: 3.3V */ 187 val = max8997_reg_ldo(3300000) | DIS_LDO; /* OFF */ 188 ret |= pmic_reg_write(p, MAX8997_REG_LDO1CTRL, val); 189 190 /* LDO1 Disable active discharging */ 191 ret |= pmic_reg_read(p, MAX8997_REG_LDO1CONFIG, &val); 192 val &= ~LDO_ADE; 193 ret |= pmic_reg_write(p, MAX8997_REG_LDO1CONFIG, val); 194 195 /* LDO2 VALIVE: 1.1V */ 196 val = max8997_reg_ldo(1100000) | EN_LDO; 197 ret |= pmic_reg_write(p, MAX8997_REG_LDO2CTRL, val); 198 199 /* LDO3 VUSB/MIPI: 1.1V */ 200 val = max8997_reg_ldo(1100000) | DIS_LDO; /* OFF */ 201 ret |= pmic_reg_write(p, MAX8997_REG_LDO3CTRL, val); 202 203 /* LDO4 VMIPI: 1.8V */ 204 val = max8997_reg_ldo(1800000) | DIS_LDO; /* OFF */ 205 ret |= pmic_reg_write(p, MAX8997_REG_LDO4CTRL, val); 206 207 /* LDO5 VHSIC: 1.2V */ 208 val = max8997_reg_ldo(1200000) | DIS_LDO; /* OFF */ 209 ret |= pmic_reg_write(p, MAX8997_REG_LDO5CTRL, val); 210 211 /* LDO6 VCC_1.8V_PDA: 1.8V */ 212 val = max8997_reg_ldo(1800000) | EN_LDO; 213 ret |= pmic_reg_write(p, MAX8997_REG_LDO6CTRL, val); 214 215 /* LDO7 CAM_ISP: 1.8V */ 216 val = max8997_reg_ldo(1800000) | DIS_LDO; /* OFF */ 217 ret |= pmic_reg_write(p, MAX8997_REG_LDO7CTRL, val); 218 219 /* LDO8 VDAC/VUSB: 3.3V */ 220 val = max8997_reg_ldo(3300000) | DIS_LDO; /* OFF */ 221 ret |= pmic_reg_write(p, MAX8997_REG_LDO8CTRL, val); 222 223 /* LDO9 VCC_2.8V_PDA: 2.8V */ 224 val = max8997_reg_ldo(2800000) | EN_LDO; 225 ret |= pmic_reg_write(p, MAX8997_REG_LDO9CTRL, val); 226 227 /* LDO10 VPLL: 1.1V */ 228 val = max8997_reg_ldo(1100000) | EN_LDO; 229 ret |= pmic_reg_write(p, MAX8997_REG_LDO10CTRL, val); 230 231 /* LDO11 TOUCH: 2.8V */ 232 val = max8997_reg_ldo(2800000) | DIS_LDO; /* OFF */ 233 ret |= pmic_reg_write(p, MAX8997_REG_LDO11CTRL, val); 234 235 /* LDO12 VTCAM: 1.8V */ 236 val = max8997_reg_ldo(1800000) | DIS_LDO; /* OFF */ 237 ret |= pmic_reg_write(p, MAX8997_REG_LDO12CTRL, val); 238 239 /* LDO13 VCC_3.0_LCD: 3.0V */ 240 val = max8997_reg_ldo(3000000) | DIS_LDO; /* OFF */ 241 ret |= pmic_reg_write(p, MAX8997_REG_LDO13CTRL, val); 242 243 /* LDO14 MOTOR: 3.0V */ 244 val = max8997_reg_ldo(3000000) | DIS_LDO; /* OFF */ 245 ret |= pmic_reg_write(p, MAX8997_REG_LDO14CTRL, val); 246 247 /* LDO15 LED_A: 2.8V */ 248 val = max8997_reg_ldo(2800000) | DIS_LDO; /* OFF */ 249 ret |= pmic_reg_write(p, MAX8997_REG_LDO15CTRL, val); 250 251 /* LDO16 CAM_SENSOR: 1.8V */ 252 val = max8997_reg_ldo(1800000) | DIS_LDO; /* OFF */ 253 ret |= pmic_reg_write(p, MAX8997_REG_LDO16CTRL, val); 254 255 /* LDO17 VTF: 2.8V */ 256 val = max8997_reg_ldo(2800000) | DIS_LDO; /* OFF */ 257 ret |= pmic_reg_write(p, MAX8997_REG_LDO17CTRL, val); 258 259 /* LDO18 TOUCH_LED 3.3V */ 260 val = max8997_reg_ldo(3300000) | DIS_LDO; /* OFF */ 261 ret |= pmic_reg_write(p, MAX8997_REG_LDO18CTRL, val); 262 263 /* LDO21 VDDQ: 1.2V */ 264 val = max8997_reg_ldo(1200000) | EN_LDO; 265 ret |= pmic_reg_write(p, MAX8997_REG_LDO21CTRL, val); 266 267 /* SAFEOUT for both 1 and 2: 4.9V, Active discharge, Enable */ 268 val = (SAFEOUT_4_90V << 0) | (SAFEOUT_4_90V << 2) | 269 ACTDISSAFEO1 | ACTDISSAFEO2 | ENSAFEOUT1 | ENSAFEOUT2; 270 ret |= pmic_reg_write(p, MAX8997_REG_SAFEOUTCTRL, val); 271 272 if (ret) { 273 puts("MAX8997 PMIC setting error!\n"); 274 return -1; 275 } 276 return 0; 277 } 278 279 int power_init_board(void) 280 { 281 int chrg, ret; 282 struct power_battery *pb; 283 struct pmic *p_fg, *p_chrg, *p_muic, *p_bat; 284 285 ret = pmic_init(I2C_5); 286 ret |= pmic_init_max8997(); 287 ret |= power_fg_init(I2C_9); 288 ret |= power_muic_init(I2C_5); 289 ret |= power_bat_init(0); 290 if (ret) 291 return ret; 292 293 p_fg = pmic_get("MAX17042_FG"); 294 if (!p_fg) { 295 puts("MAX17042_FG: Not found\n"); 296 return -ENODEV; 297 } 298 299 p_chrg = pmic_get("MAX8997_PMIC"); 300 if (!p_chrg) { 301 puts("MAX8997_PMIC: Not found\n"); 302 return -ENODEV; 303 } 304 305 p_muic = pmic_get("MAX8997_MUIC"); 306 if (!p_muic) { 307 puts("MAX8997_MUIC: Not found\n"); 308 return -ENODEV; 309 } 310 311 p_bat = pmic_get("BAT_TRATS"); 312 if (!p_bat) { 313 puts("BAT_TRATS: Not found\n"); 314 return -ENODEV; 315 } 316 317 p_fg->parent = p_bat; 318 p_chrg->parent = p_bat; 319 p_muic->parent = p_bat; 320 321 p_bat->low_power_mode = trats_low_power_mode; 322 p_bat->pbat->battery_init(p_bat, p_fg, p_chrg, p_muic); 323 324 pb = p_bat->pbat; 325 chrg = p_muic->chrg->chrg_type(p_muic); 326 debug("CHARGER TYPE: %d\n", chrg); 327 328 if (!p_chrg->chrg->chrg_bat_present(p_chrg)) { 329 puts("No battery detected\n"); 330 return -1; 331 } 332 333 p_fg->fg->fg_battery_check(p_fg, p_bat); 334 335 if (pb->bat->state == CHARGE && chrg == CHARGER_USB) 336 puts("CHARGE Battery !\n"); 337 338 return 0; 339 } 340 341 int dram_init(void) 342 { 343 gd->ram_size = get_ram_size((long *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE) + 344 get_ram_size((long *)PHYS_SDRAM_2, PHYS_SDRAM_2_SIZE) + 345 get_ram_size((long *)PHYS_SDRAM_3, PHYS_SDRAM_3_SIZE) + 346 get_ram_size((long *)PHYS_SDRAM_4, PHYS_SDRAM_4_SIZE); 347 348 return 0; 349 } 350 351 void dram_init_banksize(void) 352 { 353 gd->bd->bi_dram[0].start = PHYS_SDRAM_1; 354 gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; 355 gd->bd->bi_dram[1].start = PHYS_SDRAM_2; 356 gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE; 357 gd->bd->bi_dram[2].start = PHYS_SDRAM_3; 358 gd->bd->bi_dram[2].size = PHYS_SDRAM_3_SIZE; 359 gd->bd->bi_dram[3].start = PHYS_SDRAM_4; 360 gd->bd->bi_dram[3].size = PHYS_SDRAM_4_SIZE; 361 } 362 363 static unsigned int get_hw_revision(void) 364 { 365 struct exynos4_gpio_part1 *gpio = 366 (struct exynos4_gpio_part1 *)samsung_get_base_gpio_part1(); 367 int hwrev = 0; 368 int i; 369 370 /* hw_rev[3:0] == GPE1[3:0] */ 371 for (i = 0; i < 4; i++) { 372 s5p_gpio_cfg_pin(&gpio->e1, i, GPIO_INPUT); 373 s5p_gpio_set_pull(&gpio->e1, i, GPIO_PULL_NONE); 374 } 375 376 udelay(1); 377 378 for (i = 0; i < 4; i++) 379 hwrev |= (s5p_gpio_get_value(&gpio->e1, i) << i); 380 381 debug("hwrev 0x%x\n", hwrev); 382 383 return hwrev; 384 } 385 386 static void check_hw_revision(void) 387 { 388 int hwrev; 389 390 hwrev = get_hw_revision(); 391 392 board_rev |= hwrev; 393 } 394 395 #ifdef CONFIG_DISPLAY_BOARDINFO 396 int checkboard(void) 397 { 398 puts("Board:\tTRATS\n"); 399 return 0; 400 } 401 #endif 402 403 #ifdef CONFIG_GENERIC_MMC 404 int board_mmc_init(bd_t *bis) 405 { 406 struct exynos4_gpio_part2 *gpio = 407 (struct exynos4_gpio_part2 *)samsung_get_base_gpio_part2(); 408 int err; 409 410 /* eMMC_EN: SD_0_CDn: GPK0[2] Output High */ 411 s5p_gpio_direction_output(&gpio->k0, 2, 1); 412 s5p_gpio_set_pull(&gpio->k0, 2, GPIO_PULL_NONE); 413 414 /* 415 * MMC device init 416 * mmc0 : eMMC (8-bit buswidth) 417 * mmc2 : SD card (4-bit buswidth) 418 */ 419 err = exynos_pinmux_config(PERIPH_ID_SDMMC0, PINMUX_FLAG_8BIT_MODE); 420 if (err) 421 debug("SDMMC0 not configured\n"); 422 else 423 err = s5p_mmc_init(0, 8); 424 425 /* T-flash detect */ 426 s5p_gpio_cfg_pin(&gpio->x3, 4, 0xf); 427 s5p_gpio_set_pull(&gpio->x3, 4, GPIO_PULL_UP); 428 429 /* 430 * Check the T-flash detect pin 431 * GPX3[4] T-flash detect pin 432 */ 433 if (!s5p_gpio_get_value(&gpio->x3, 4)) { 434 err = exynos_pinmux_config(PERIPH_ID_SDMMC2, PINMUX_FLAG_NONE); 435 if (err) 436 debug("SDMMC2 not configured\n"); 437 else 438 err = s5p_mmc_init(2, 4); 439 } 440 441 return err; 442 } 443 #endif 444 445 #ifdef CONFIG_USB_GADGET 446 static int s5pc210_phy_control(int on) 447 { 448 int ret = 0; 449 u32 val = 0; 450 struct pmic *p = pmic_get("MAX8997_PMIC"); 451 if (!p) 452 return -ENODEV; 453 454 if (pmic_probe(p)) 455 return -1; 456 457 if (on) { 458 ret |= pmic_set_output(p, MAX8997_REG_SAFEOUTCTRL, 459 ENSAFEOUT1, LDO_ON); 460 ret |= pmic_reg_read(p, MAX8997_REG_LDO3CTRL, &val); 461 ret |= pmic_reg_write(p, MAX8997_REG_LDO3CTRL, EN_LDO | val); 462 463 ret |= pmic_reg_read(p, MAX8997_REG_LDO8CTRL, &val); 464 ret |= pmic_reg_write(p, MAX8997_REG_LDO8CTRL, EN_LDO | val); 465 } else { 466 ret |= pmic_reg_read(p, MAX8997_REG_LDO8CTRL, &val); 467 ret |= pmic_reg_write(p, MAX8997_REG_LDO8CTRL, DIS_LDO | val); 468 469 ret |= pmic_reg_read(p, MAX8997_REG_LDO3CTRL, &val); 470 ret |= pmic_reg_write(p, MAX8997_REG_LDO3CTRL, DIS_LDO | val); 471 ret |= pmic_set_output(p, MAX8997_REG_SAFEOUTCTRL, 472 ENSAFEOUT1, LDO_OFF); 473 } 474 475 if (ret) { 476 puts("MAX8997 LDO setting error!\n"); 477 return -1; 478 } 479 480 return 0; 481 } 482 483 struct s3c_plat_otg_data s5pc210_otg_data = { 484 .phy_control = s5pc210_phy_control, 485 .regs_phy = EXYNOS4_USBPHY_BASE, 486 .regs_otg = EXYNOS4_USBOTG_BASE, 487 .usb_phy_ctrl = EXYNOS4_USBPHY_CONTROL, 488 .usb_flags = PHY0_SLEEP, 489 }; 490 491 void board_usb_init(void) 492 { 493 debug("USB_udc_probe\n"); 494 s3c_udc_probe(&s5pc210_otg_data); 495 } 496 #endif 497 498 static void pmic_reset(void) 499 { 500 struct exynos4_gpio_part2 *gpio = 501 (struct exynos4_gpio_part2 *)samsung_get_base_gpio_part2(); 502 503 s5p_gpio_direction_output(&gpio->x0, 7, 1); 504 s5p_gpio_set_pull(&gpio->x2, 7, GPIO_PULL_NONE); 505 } 506 507 static void board_clock_init(void) 508 { 509 struct exynos4_clock *clk = 510 (struct exynos4_clock *)samsung_get_base_clock(); 511 512 writel(CLK_SRC_CPU_VAL, (unsigned int)&clk->src_cpu); 513 writel(CLK_SRC_TOP0_VAL, (unsigned int)&clk->src_top0); 514 writel(CLK_SRC_FSYS_VAL, (unsigned int)&clk->src_fsys); 515 writel(CLK_SRC_PERIL0_VAL, (unsigned int)&clk->src_peril0); 516 517 writel(CLK_DIV_CPU0_VAL, (unsigned int)&clk->div_cpu0); 518 writel(CLK_DIV_CPU1_VAL, (unsigned int)&clk->div_cpu1); 519 writel(CLK_DIV_DMC0_VAL, (unsigned int)&clk->div_dmc0); 520 writel(CLK_DIV_DMC1_VAL, (unsigned int)&clk->div_dmc1); 521 writel(CLK_DIV_LEFTBUS_VAL, (unsigned int)&clk->div_leftbus); 522 writel(CLK_DIV_RIGHTBUS_VAL, (unsigned int)&clk->div_rightbus); 523 writel(CLK_DIV_TOP_VAL, (unsigned int)&clk->div_top); 524 writel(CLK_DIV_FSYS1_VAL, (unsigned int)&clk->div_fsys1); 525 writel(CLK_DIV_FSYS2_VAL, (unsigned int)&clk->div_fsys2); 526 writel(CLK_DIV_FSYS3_VAL, (unsigned int)&clk->div_fsys3); 527 writel(CLK_DIV_PERIL0_VAL, (unsigned int)&clk->div_peril0); 528 writel(CLK_DIV_PERIL3_VAL, (unsigned int)&clk->div_peril3); 529 530 writel(PLL_LOCKTIME, (unsigned int)&clk->apll_lock); 531 writel(PLL_LOCKTIME, (unsigned int)&clk->mpll_lock); 532 writel(PLL_LOCKTIME, (unsigned int)&clk->epll_lock); 533 writel(PLL_LOCKTIME, (unsigned int)&clk->vpll_lock); 534 writel(APLL_CON1_VAL, (unsigned int)&clk->apll_con1); 535 writel(APLL_CON0_VAL, (unsigned int)&clk->apll_con0); 536 writel(MPLL_CON1_VAL, (unsigned int)&clk->mpll_con1); 537 writel(MPLL_CON0_VAL, (unsigned int)&clk->mpll_con0); 538 writel(EPLL_CON1_VAL, (unsigned int)&clk->epll_con1); 539 writel(EPLL_CON0_VAL, (unsigned int)&clk->epll_con0); 540 writel(VPLL_CON1_VAL, (unsigned int)&clk->vpll_con1); 541 writel(VPLL_CON0_VAL, (unsigned int)&clk->vpll_con0); 542 543 writel(CLK_GATE_IP_CAM_VAL, (unsigned int)&clk->gate_ip_cam); 544 writel(CLK_GATE_IP_VP_VAL, (unsigned int)&clk->gate_ip_tv); 545 writel(CLK_GATE_IP_MFC_VAL, (unsigned int)&clk->gate_ip_mfc); 546 writel(CLK_GATE_IP_G3D_VAL, (unsigned int)&clk->gate_ip_g3d); 547 writel(CLK_GATE_IP_IMAGE_VAL, (unsigned int)&clk->gate_ip_image); 548 writel(CLK_GATE_IP_LCD0_VAL, (unsigned int)&clk->gate_ip_lcd0); 549 writel(CLK_GATE_IP_LCD1_VAL, (unsigned int)&clk->gate_ip_lcd1); 550 writel(CLK_GATE_IP_FSYS_VAL, (unsigned int)&clk->gate_ip_fsys); 551 writel(CLK_GATE_IP_GPS_VAL, (unsigned int)&clk->gate_ip_gps); 552 writel(CLK_GATE_IP_PERIL_VAL, (unsigned int)&clk->gate_ip_peril); 553 writel(CLK_GATE_IP_PERIR_VAL, (unsigned int)&clk->gate_ip_perir); 554 writel(CLK_GATE_BLOCK_VAL, (unsigned int)&clk->gate_block); 555 } 556 557 static void board_power_init(void) 558 { 559 struct exynos4_power *pwr = 560 (struct exynos4_power *)samsung_get_base_power(); 561 562 /* PS HOLD */ 563 writel(EXYNOS4_PS_HOLD_CON_VAL, (unsigned int)&pwr->ps_hold_control); 564 565 /* Set power down */ 566 writel(0, (unsigned int)&pwr->cam_configuration); 567 writel(0, (unsigned int)&pwr->tv_configuration); 568 writel(0, (unsigned int)&pwr->mfc_configuration); 569 writel(0, (unsigned int)&pwr->g3d_configuration); 570 writel(0, (unsigned int)&pwr->lcd1_configuration); 571 writel(0, (unsigned int)&pwr->gps_configuration); 572 writel(0, (unsigned int)&pwr->gps_alive_configuration); 573 574 /* It is necessary to power down core 1 */ 575 /* to successfully boot CPU1 in kernel */ 576 writel(0, (unsigned int)&pwr->arm_core1_configuration); 577 } 578 579 static void board_uart_init(void) 580 { 581 struct exynos4_gpio_part1 *gpio1 = 582 (struct exynos4_gpio_part1 *)samsung_get_base_gpio_part1(); 583 struct exynos4_gpio_part2 *gpio2 = 584 (struct exynos4_gpio_part2 *)samsung_get_base_gpio_part2(); 585 int i; 586 587 /* 588 * UART2 GPIOs 589 * GPA1CON[0] = UART_2_RXD(2) 590 * GPA1CON[1] = UART_2_TXD(2) 591 * GPA1CON[2] = I2C_3_SDA (3) 592 * GPA1CON[3] = I2C_3_SCL (3) 593 */ 594 595 for (i = 0; i < 4; i++) { 596 s5p_gpio_set_pull(&gpio1->a1, i, GPIO_PULL_NONE); 597 s5p_gpio_cfg_pin(&gpio1->a1, i, GPIO_FUNC((i > 1) ? 0x3 : 0x2)); 598 } 599 600 /* UART_SEL GPY4[7] (part2) at EXYNOS4 */ 601 s5p_gpio_set_pull(&gpio2->y4, 7, GPIO_PULL_UP); 602 s5p_gpio_direction_output(&gpio2->y4, 7, 1); 603 } 604 605 int board_early_init_f(void) 606 { 607 wdt_stop(); 608 pmic_reset(); 609 board_clock_init(); 610 board_uart_init(); 611 board_power_init(); 612 613 return 0; 614 } 615 616 void exynos_reset_lcd(void) 617 { 618 struct exynos4_gpio_part2 *gpio2 = 619 (struct exynos4_gpio_part2 *)samsung_get_base_gpio_part2(); 620 621 s5p_gpio_direction_output(&gpio2->y4, 5, 1); 622 udelay(10000); 623 s5p_gpio_direction_output(&gpio2->y4, 5, 0); 624 udelay(10000); 625 s5p_gpio_direction_output(&gpio2->y4, 5, 1); 626 } 627 628 static int lcd_power(void) 629 { 630 int ret = 0; 631 struct pmic *p = pmic_get("MAX8997_PMIC"); 632 if (!p) 633 return -ENODEV; 634 635 if (pmic_probe(p)) 636 return 0; 637 638 /* LDO15 voltage: 2.2v */ 639 ret |= pmic_reg_write(p, MAX8997_REG_LDO15CTRL, 0x1c | EN_LDO); 640 /* LDO13 voltage: 3.0v */ 641 ret |= pmic_reg_write(p, MAX8997_REG_LDO13CTRL, 0x2c | EN_LDO); 642 643 if (ret) { 644 puts("MAX8997 LDO setting error!\n"); 645 return -1; 646 } 647 648 return 0; 649 } 650 651 static struct mipi_dsim_config dsim_config = { 652 .e_interface = DSIM_VIDEO, 653 .e_virtual_ch = DSIM_VIRTUAL_CH_0, 654 .e_pixel_format = DSIM_24BPP_888, 655 .e_burst_mode = DSIM_BURST_SYNC_EVENT, 656 .e_no_data_lane = DSIM_DATA_LANE_4, 657 .e_byte_clk = DSIM_PLL_OUT_DIV8, 658 .hfp = 1, 659 660 .p = 3, 661 .m = 120, 662 .s = 1, 663 664 /* D-PHY PLL stable time spec :min = 200usec ~ max 400usec */ 665 .pll_stable_time = 500, 666 667 /* escape clk : 10MHz */ 668 .esc_clk = 20 * 1000000, 669 670 /* stop state holding counter after bta change count 0 ~ 0xfff */ 671 .stop_holding_cnt = 0x7ff, 672 /* bta timeout 0 ~ 0xff */ 673 .bta_timeout = 0xff, 674 /* lp rx timeout 0 ~ 0xffff */ 675 .rx_timeout = 0xffff, 676 }; 677 678 static struct exynos_platform_mipi_dsim s6e8ax0_platform_data = { 679 .lcd_panel_info = NULL, 680 .dsim_config = &dsim_config, 681 }; 682 683 static struct mipi_dsim_lcd_device mipi_lcd_device = { 684 .name = "s6e8ax0", 685 .id = -1, 686 .bus_id = 0, 687 .platform_data = (void *)&s6e8ax0_platform_data, 688 }; 689 690 static int mipi_power(void) 691 { 692 int ret = 0; 693 struct pmic *p = pmic_get("MAX8997_PMIC"); 694 if (!p) 695 return -ENODEV; 696 697 if (pmic_probe(p)) 698 return 0; 699 700 /* LDO3 voltage: 1.1v */ 701 ret |= pmic_reg_write(p, MAX8997_REG_LDO3CTRL, 0x6 | EN_LDO); 702 /* LDO4 voltage: 1.8v */ 703 ret |= pmic_reg_write(p, MAX8997_REG_LDO4CTRL, 0x14 | EN_LDO); 704 705 if (ret) { 706 puts("MAX8997 LDO setting error!\n"); 707 return -1; 708 } 709 710 return 0; 711 } 712 713 vidinfo_t panel_info = { 714 .vl_freq = 60, 715 .vl_col = 720, 716 .vl_row = 1280, 717 .vl_width = 720, 718 .vl_height = 1280, 719 .vl_clkp = CONFIG_SYS_HIGH, 720 .vl_hsp = CONFIG_SYS_LOW, 721 .vl_vsp = CONFIG_SYS_LOW, 722 .vl_dp = CONFIG_SYS_LOW, 723 .vl_bpix = 5, /* Bits per pixel, 2^5 = 32 */ 724 725 /* s6e8ax0 Panel infomation */ 726 .vl_hspw = 5, 727 .vl_hbpd = 10, 728 .vl_hfpd = 10, 729 730 .vl_vspw = 2, 731 .vl_vbpd = 1, 732 .vl_vfpd = 13, 733 .vl_cmd_allow_len = 0xf, 734 735 .win_id = 3, 736 .dual_lcd_enabled = 0, 737 738 .init_delay = 0, 739 .power_on_delay = 0, 740 .reset_delay = 0, 741 .interface_mode = FIMD_RGB_INTERFACE, 742 .mipi_enabled = 1, 743 }; 744 745 void init_panel_info(vidinfo_t *vid) 746 { 747 vid->logo_on = 1, 748 vid->resolution = HD_RESOLUTION, 749 vid->rgb_mode = MODE_RGB_P, 750 751 #ifdef CONFIG_TIZEN 752 get_tizen_logo_info(vid); 753 #endif 754 mipi_lcd_device.reverse_panel = 1; 755 756 strcpy(s6e8ax0_platform_data.lcd_panel_name, mipi_lcd_device.name); 757 s6e8ax0_platform_data.lcd_power = lcd_power; 758 s6e8ax0_platform_data.mipi_power = mipi_power; 759 s6e8ax0_platform_data.phy_enable = set_mipi_phy_ctrl; 760 s6e8ax0_platform_data.lcd_panel_info = (void *)vid; 761 exynos_mipi_dsi_register_lcd_device(&mipi_lcd_device); 762 s6e8ax0_init(); 763 exynos_set_dsim_platform_data(&s6e8ax0_platform_data); 764 765 setenv("lcdinfo", "lcd=s6e8ax0"); 766 } 767 768 #ifdef CONFIG_USB_GADGET_MASS_STORAGE 769 static int ums_read_sector(struct ums_device *ums_dev, 770 ulong start, lbaint_t blkcnt, void *buf) 771 { 772 if (ums_dev->mmc->block_dev.block_read(ums_dev->dev_num, 773 start + ums_dev->offset, blkcnt, buf) != blkcnt) 774 return -1; 775 776 return 0; 777 } 778 779 static int ums_write_sector(struct ums_device *ums_dev, 780 ulong start, lbaint_t blkcnt, const void *buf) 781 { 782 if (ums_dev->mmc->block_dev.block_write(ums_dev->dev_num, 783 start + ums_dev->offset, blkcnt, buf) != blkcnt) 784 return -1; 785 786 return 0; 787 } 788 789 static void ums_get_capacity(struct ums_device *ums_dev, 790 long long int *capacity) 791 { 792 long long int tmp_capacity; 793 794 tmp_capacity = (long long int) ((ums_dev->offset + ums_dev->part_size) 795 * SECTOR_SIZE); 796 *capacity = ums_dev->mmc->capacity - tmp_capacity; 797 } 798 799 static struct ums_board_info ums_board = { 800 .read_sector = ums_read_sector, 801 .write_sector = ums_write_sector, 802 .get_capacity = ums_get_capacity, 803 .name = "TRATS UMS disk", 804 .ums_dev = { 805 .mmc = NULL, 806 .dev_num = 0, 807 .offset = 0, 808 .part_size = 0. 809 }, 810 }; 811 812 struct ums_board_info *board_ums_init(unsigned int dev_num, unsigned int offset, 813 unsigned int part_size) 814 { 815 struct mmc *mmc; 816 817 mmc = find_mmc_device(dev_num); 818 if (!mmc) 819 return NULL; 820 821 ums_board.ums_dev.mmc = mmc; 822 ums_board.ums_dev.dev_num = dev_num; 823 ums_board.ums_dev.offset = offset; 824 ums_board.ums_dev.part_size = part_size; 825 826 return &ums_board; 827 } 828 #endif 829