1*83d290c5STom Rini // SPDX-License-Identifier: GPL-2.0+ 2e21185baSChander Kashyap /* 3e21185baSChander Kashyap * Copyright (C) 2011 Samsung Electronics 4e21185baSChander Kashyap */ 5e21185baSChander Kashyap 6e21185baSChander Kashyap #include <common.h> 7903fd795SSimon Glass #include <asm/gpio.h> 8e21185baSChander Kashyap #include <asm/io.h> 9e21185baSChander Kashyap #include <netdev.h> 10e21185baSChander Kashyap #include <asm/arch/cpu.h> 11e21185baSChander Kashyap #include <asm/arch/mmc.h> 12198a40b9SRajeshwari Shinde #include <asm/arch/periph.h> 13198a40b9SRajeshwari Shinde #include <asm/arch/pinmux.h> 14e21185baSChander Kashyap #include <asm/arch/sromc.h> 15e21185baSChander Kashyap 16e21185baSChander Kashyap DECLARE_GLOBAL_DATA_PTR; 17e21185baSChander Kashyap 18e21185baSChander Kashyap static void smc9115_pre_init(void) 19e21185baSChander Kashyap { 20e21185baSChander Kashyap u32 smc_bw_conf, smc_bc_conf; 21e21185baSChander Kashyap 22e21185baSChander Kashyap /* gpio configuration GPK0CON */ 23f6ae1ca0SAkshay Saraswat gpio_cfg_pin(EXYNOS4_GPIO_Y00 + CONFIG_ENV_SROM_BANK, S5P_GPIO_FUNC(2)); 24e21185baSChander Kashyap 25e21185baSChander Kashyap /* Ethernet needs bus width of 16 bits */ 26e21185baSChander Kashyap smc_bw_conf = SROMC_DATA16_WIDTH(CONFIG_ENV_SROM_BANK); 27e21185baSChander Kashyap smc_bc_conf = SROMC_BC_TACS(0x0F) | SROMC_BC_TCOS(0x0F) 28e21185baSChander Kashyap | SROMC_BC_TACC(0x0F) | SROMC_BC_TCOH(0x0F) 29e21185baSChander Kashyap | SROMC_BC_TAH(0x0F) | SROMC_BC_TACP(0x0F) 30e21185baSChander Kashyap | SROMC_BC_PMC(0x0F); 31e21185baSChander Kashyap 32e21185baSChander Kashyap /* Select and configure the SROMC bank */ 33e21185baSChander Kashyap s5p_config_sromc(CONFIG_ENV_SROM_BANK, smc_bw_conf, smc_bc_conf); 34e21185baSChander Kashyap } 35e21185baSChander Kashyap 36e21185baSChander Kashyap int board_init(void) 37e21185baSChander Kashyap { 38e21185baSChander Kashyap smc9115_pre_init(); 39e21185baSChander Kashyap 40e21185baSChander Kashyap gd->bd->bi_boot_params = (PHYS_SDRAM_1 + 0x100UL); 41e21185baSChander Kashyap return 0; 42e21185baSChander Kashyap } 43e21185baSChander Kashyap 44e21185baSChander Kashyap int dram_init(void) 45e21185baSChander Kashyap { 46e21185baSChander Kashyap gd->ram_size = get_ram_size((long *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE) 47e21185baSChander Kashyap + get_ram_size((long *)PHYS_SDRAM_2, PHYS_SDRAM_2_SIZE) 48e21185baSChander Kashyap + get_ram_size((long *)PHYS_SDRAM_3, PHYS_SDRAM_3_SIZE) 49e21185baSChander Kashyap + get_ram_size((long *)PHYS_SDRAM_4, PHYS_SDRAM_4_SIZE); 50e21185baSChander Kashyap 51e21185baSChander Kashyap return 0; 52e21185baSChander Kashyap } 53e21185baSChander Kashyap 5476b00acaSSimon Glass int dram_init_banksize(void) 55e21185baSChander Kashyap { 56e21185baSChander Kashyap gd->bd->bi_dram[0].start = PHYS_SDRAM_1; 576b949ba8SMinkyu Kang gd->bd->bi_dram[0].size = get_ram_size((long *)PHYS_SDRAM_1, 589436a0c9SChander Kashyap PHYS_SDRAM_1_SIZE); 59e21185baSChander Kashyap gd->bd->bi_dram[1].start = PHYS_SDRAM_2; 606b949ba8SMinkyu Kang gd->bd->bi_dram[1].size = get_ram_size((long *)PHYS_SDRAM_2, 619436a0c9SChander Kashyap PHYS_SDRAM_2_SIZE); 62e21185baSChander Kashyap gd->bd->bi_dram[2].start = PHYS_SDRAM_3; 636b949ba8SMinkyu Kang gd->bd->bi_dram[2].size = get_ram_size((long *)PHYS_SDRAM_3, 649436a0c9SChander Kashyap PHYS_SDRAM_3_SIZE); 65e21185baSChander Kashyap gd->bd->bi_dram[3].start = PHYS_SDRAM_4; 666b949ba8SMinkyu Kang gd->bd->bi_dram[3].size = get_ram_size((long *)PHYS_SDRAM_4, 679436a0c9SChander Kashyap PHYS_SDRAM_4_SIZE); 6876b00acaSSimon Glass 6976b00acaSSimon Glass return 0; 70e21185baSChander Kashyap } 71e21185baSChander Kashyap 72e21185baSChander Kashyap int board_eth_init(bd_t *bis) 73e21185baSChander Kashyap { 74e21185baSChander Kashyap int rc = 0; 75e21185baSChander Kashyap #ifdef CONFIG_SMC911X 76e21185baSChander Kashyap rc = smc911x_initialize(0, CONFIG_SMC911X_BASE); 77e21185baSChander Kashyap #endif 78e21185baSChander Kashyap return rc; 79e21185baSChander Kashyap } 80e21185baSChander Kashyap 81e21185baSChander Kashyap #ifdef CONFIG_DISPLAY_BOARDINFO 82e21185baSChander Kashyap int checkboard(void) 83e21185baSChander Kashyap { 84e21185baSChander Kashyap printf("\nBoard: SMDKV310\n"); 85e21185baSChander Kashyap return 0; 86e21185baSChander Kashyap } 87e21185baSChander Kashyap #endif 88e21185baSChander Kashyap 894aa2ba3aSMasahiro Yamada #ifdef CONFIG_MMC 90e21185baSChander Kashyap int board_mmc_init(bd_t *bis) 91e21185baSChander Kashyap { 92e21185baSChander Kashyap int i, err; 93e21185baSChander Kashyap 94e21185baSChander Kashyap /* 95e21185baSChander Kashyap * MMC2 SD card GPIO: 96e21185baSChander Kashyap * 97e21185baSChander Kashyap * GPK2[0] SD_2_CLK(2) 98e21185baSChander Kashyap * GPK2[1] SD_2_CMD(2) 99e21185baSChander Kashyap * GPK2[2] SD_2_CDn 100e21185baSChander Kashyap * GPK2[3:6] SD_2_DATA[0:3](2) 101e21185baSChander Kashyap */ 102f6ae1ca0SAkshay Saraswat for (i = EXYNOS4_GPIO_K20; i < EXYNOS4_GPIO_K27; i++) { 103e21185baSChander Kashyap /* GPK2[0:6] special function 2 */ 104f6ae1ca0SAkshay Saraswat gpio_cfg_pin(i, S5P_GPIO_FUNC(0x2)); 105e21185baSChander Kashyap 106e21185baSChander Kashyap /* GPK2[0:6] drv 4x */ 107f6ae1ca0SAkshay Saraswat gpio_set_drv(i, S5P_GPIO_DRV_4X); 108e21185baSChander Kashyap 109e21185baSChander Kashyap /* GPK2[0:1] pull disable */ 110f6ae1ca0SAkshay Saraswat if (i == EXYNOS4_GPIO_K20 || i == EXYNOS4_GPIO_K21) { 111f6ae1ca0SAkshay Saraswat gpio_set_pull(i, S5P_GPIO_PULL_NONE); 112e21185baSChander Kashyap continue; 113e21185baSChander Kashyap } 114e21185baSChander Kashyap 115e21185baSChander Kashyap /* GPK2[2:6] pull up */ 116f6ae1ca0SAkshay Saraswat gpio_set_pull(i, S5P_GPIO_PULL_UP); 117e21185baSChander Kashyap } 118e21185baSChander Kashyap err = s5p_mmc_init(2, 4); 119e21185baSChander Kashyap return err; 120e21185baSChander Kashyap } 121e21185baSChander Kashyap #endif 122198a40b9SRajeshwari Shinde 123198a40b9SRajeshwari Shinde static int board_uart_init(void) 124198a40b9SRajeshwari Shinde { 125198a40b9SRajeshwari Shinde int err; 126198a40b9SRajeshwari Shinde 127198a40b9SRajeshwari Shinde err = exynos_pinmux_config(PERIPH_ID_UART0, PINMUX_FLAG_NONE); 128198a40b9SRajeshwari Shinde if (err) { 129198a40b9SRajeshwari Shinde debug("UART0 not configured\n"); 130198a40b9SRajeshwari Shinde return err; 131198a40b9SRajeshwari Shinde } 132198a40b9SRajeshwari Shinde 133198a40b9SRajeshwari Shinde err = exynos_pinmux_config(PERIPH_ID_UART1, PINMUX_FLAG_NONE); 134198a40b9SRajeshwari Shinde if (err) { 135198a40b9SRajeshwari Shinde debug("UART1 not configured\n"); 136198a40b9SRajeshwari Shinde return err; 137198a40b9SRajeshwari Shinde } 138198a40b9SRajeshwari Shinde 139198a40b9SRajeshwari Shinde err = exynos_pinmux_config(PERIPH_ID_UART2, PINMUX_FLAG_NONE); 140198a40b9SRajeshwari Shinde if (err) { 141198a40b9SRajeshwari Shinde debug("UART2 not configured\n"); 142198a40b9SRajeshwari Shinde return err; 143198a40b9SRajeshwari Shinde } 144198a40b9SRajeshwari Shinde 145198a40b9SRajeshwari Shinde err = exynos_pinmux_config(PERIPH_ID_UART3, PINMUX_FLAG_NONE); 146198a40b9SRajeshwari Shinde if (err) { 147198a40b9SRajeshwari Shinde debug("UART3 not configured\n"); 148198a40b9SRajeshwari Shinde return err; 149198a40b9SRajeshwari Shinde } 150198a40b9SRajeshwari Shinde 151198a40b9SRajeshwari Shinde return 0; 152198a40b9SRajeshwari Shinde } 153198a40b9SRajeshwari Shinde 154198a40b9SRajeshwari Shinde #ifdef CONFIG_BOARD_EARLY_INIT_F 155198a40b9SRajeshwari Shinde int board_early_init_f(void) 156198a40b9SRajeshwari Shinde { 157198a40b9SRajeshwari Shinde int err; 158198a40b9SRajeshwari Shinde err = board_uart_init(); 159198a40b9SRajeshwari Shinde if (err) { 160198a40b9SRajeshwari Shinde debug("UART init failed\n"); 161198a40b9SRajeshwari Shinde return err; 162198a40b9SRajeshwari Shinde } 163198a40b9SRajeshwari Shinde return err; 164198a40b9SRajeshwari Shinde } 165198a40b9SRajeshwari Shinde #endif 166