1 /* 2 * Copyright (C) 2008-2009 Samsung Electronics 3 * Kyungmin Park <kyungmin.park@samsung.com> 4 * 5 * See file CREDITS for list of people who contributed to this 6 * project. 7 * 8 * This program is free software; you can redistribute it and/or 9 * modify it under the terms of the GNU General Public License as 10 * published by the Free Software Foundation; either version 2 of 11 * the License, or (at your option) any later version. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program; if not, write to the Free Software 20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 21 * MA 02111-1307 USA 22 */ 23 24 #include <common.h> 25 #include <linux/mtd/compat.h> 26 #include <linux/mtd/mtd.h> 27 #include <linux/mtd/onenand.h> 28 #include <linux/mtd/samsung_onenand.h> 29 30 #include <onenand_uboot.h> 31 32 #include <asm/io.h> 33 #include <asm/arch/clock.h> 34 35 void onenand_board_init(struct mtd_info *mtd) 36 { 37 struct onenand_chip *this = mtd->priv; 38 struct s5pc100_clock *clk = 39 (struct s5pc100_clock *)samsung_get_base_clock(); 40 struct samsung_onenand *onenand; 41 int value; 42 43 this->base = (void *)S5PC100_ONENAND_BASE; 44 onenand = (struct samsung_onenand *)this->base; 45 46 /* D0 Domain memory clock gating */ 47 value = readl(&clk->gate_d01); 48 value &= ~(1 << 2); /* CLK_ONENANDC */ 49 value |= (1 << 2); 50 writel(value, &clk->gate_d01); 51 52 value = readl(&clk->src0); 53 value &= ~(1 << 24); /* MUX_1nand: 0 from HCLKD0 */ 54 value &= ~(1 << 20); /* MUX_HREF: 0 from FIN_27M */ 55 writel(value, &clk->src0); 56 57 value = readl(&clk->div1); 58 value &= ~(3 << 16); /* PCLKD1_RATIO */ 59 value |= (1 << 16); 60 writel(value, &clk->div1); 61 62 writel(ONENAND_MEM_RESET_COLD, &onenand->mem_reset); 63 64 while (!(readl(&onenand->int_err_stat) & RST_CMP)) 65 continue; 66 67 writel(RST_CMP, &onenand->int_err_ack); 68 69 /* 70 * Access_Clock [2:0] 71 * 166 MHz, 134 Mhz : 3 72 * 100 Mhz, 60 Mhz : 2 73 */ 74 writel(0x3, &onenand->acc_clock); 75 76 writel(INT_ERR_ALL, &onenand->int_err_mask); 77 writel(1 << 0, &onenand->int_pin_en); /* Enable */ 78 79 value = readl(&onenand->int_err_mask); 80 value &= ~RDY_ACT; 81 writel(value, &onenand->int_err_mask); 82 83 s3c_onenand_init(mtd); 84 } 85