1 /*
2  * Copyright (C) 2008-2009 Samsung Electronics
3  * Kyungmin Park <kyungmin.park@samsung.com>
4  *
5  * See file CREDITS for list of people who contributed to this
6  * project.
7  *
8  * This program is free software; you can redistribute it and/or
9  * modify it under the terms of the GNU General Public License as
10  * published by the Free Software Foundation; either version 2 of
11  * the License, or (at your option) any later version.
12  *
13  * This program is distributed in the hope that it will be useful,
14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
16  * GNU General Public License for more details.
17  *
18  * You should have received a copy of the GNU General Public License
19  * along with this program; if not, write to the Free Software
20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21  * MA 02111-1307 USA
22  */
23 
24 #include <common.h>
25 #include <linux/mtd/compat.h>
26 #include <linux/mtd/mtd.h>
27 #include <linux/mtd/onenand.h>
28 #include <linux/mtd/samsung_onenand.h>
29 
30 #include <onenand_uboot.h>
31 
32 #include <asm/io.h>
33 #include <asm/arch/clock.h>
34 
35 void onenand_board_init(struct mtd_info *mtd)
36 {
37 	struct onenand_chip *this = mtd->priv;
38 	struct s5pc100_clock *clk = (struct s5pc100_clock *)S5PC1XX_CLOCK_BASE;
39 	struct samsung_onenand *onenand;
40 	int value;
41 
42 	this->base = (void *)S5PC100_ONENAND_BASE;
43 	onenand = (struct samsung_onenand *)this->base;
44 
45 	/* D0 Domain memory clock gating */
46 	value = readl(&clk->gate_d01);
47 	value &= ~(1 << 2);		/* CLK_ONENANDC */
48 	value |= (1 << 2);
49 	writel(value, &clk->gate_d01);
50 
51 	value = readl(&clk->src0);
52 	value &= ~(1 << 24);		/* MUX_1nand: 0 from HCLKD0 */
53 	value &= ~(1 << 20);		/* MUX_HREF: 0 from FIN_27M */
54 	writel(value, &clk->src0);
55 
56 	value = readl(&clk->div1);
57 	value &= ~(3 << 16);		/* PCLKD1_RATIO */
58 	value |= (1 << 16);
59 	writel(value, &clk->div1);
60 
61 	writel(ONENAND_MEM_RESET_COLD, &onenand->mem_reset);
62 
63 	while (!(readl(&onenand->int_err_stat) & RST_CMP))
64 		continue;
65 
66 	writel(RST_CMP, &onenand->int_err_ack);
67 
68 	/*
69 	 * Access_Clock [2:0]
70 	 * 166 MHz, 134 Mhz : 3
71 	 * 100 Mhz, 60 Mhz  : 2
72 	 */
73 	writel(0x3, &onenand->acc_clock);
74 
75 	writel(INT_ERR_ALL, &onenand->int_err_mask);
76 	writel(1 << 0, &onenand->int_pin_en);	/* Enable */
77 
78 	value = readl(&onenand->int_err_mask);
79 	value &= ~RDY_ACT;
80 	writel(value, &onenand->int_err_mask);
81 
82 	s3c_onenand_init(mtd);
83 }
84