1/* SPDX-License-Identifier: GPL-2.0+ */
2/*
3 * Copyright (C) 2009 Samsung Electronics
4 * Kyungmin Park <kyungmin.park@samsung.com>
5 * Minkyu Kang <mk7.kang@samsung.com>
6 */
7
8#include <config.h>
9#include <asm/arch/cpu.h>
10#include <asm/arch/power.h>
11
12/*
13 * Register usages:
14 *
15 * r5 has zero always
16 */
17
18	.globl lowlevel_init
19lowlevel_init:
20	mov	r9, lr
21
22	/* r5 has always zero */
23	mov	r5, #0
24
25	ldr	r8, =S5PC100_GPIO_BASE
26
27	/* Disable Watchdog */
28	ldr	r0, =S5PC100_WATCHDOG_BASE		@0xEA200000
29	orr	r0, r0, #0x0
30	str	r5, [r0]
31
32	/* setting SRAM */
33	ldr	r0, =S5PC100_SROMC_BASE
34	ldr	r1, =0x9
35	str	r1, [r0]
36
37	/* S5PC100 has 3 groups of interrupt sources */
38	ldr	r0, =S5PC100_VIC0_BASE			@0xE4000000
39	ldr	r1, =S5PC100_VIC1_BASE			@0xE4000000
40	ldr	r2, =S5PC100_VIC2_BASE			@0xE4000000
41
42	/* Disable all interrupts (VIC0, VIC1 and VIC2) */
43	mvn	r3, #0x0
44	str	r3, [r0, #0x14]				@INTENCLEAR
45	str	r3, [r1, #0x14]				@INTENCLEAR
46	str	r3, [r2, #0x14]				@INTENCLEAR
47
48	/* Set all interrupts as IRQ */
49	str	r5, [r0, #0xc]				@INTSELECT
50	str	r5, [r1, #0xc]				@INTSELECT
51	str	r5, [r2, #0xc]				@INTSELECT
52
53	/* Pending Interrupt Clear */
54	str	r5, [r0, #0xf00]			@INTADDRESS
55	str	r5, [r1, #0xf00]			@INTADDRESS
56	str	r5, [r2, #0xf00]			@INTADDRESS
57
58	/* for UART */
59	bl uart_asm_init
60
61	/* for TZPC */
62	bl tzpc_asm_init
63
641:
65	mov	lr, r9
66	mov	pc, lr
67
68/*
69 * system_clock_init: Initialize core clock and bus clock.
70 * void system_clock_init(void)
71 */
72system_clock_init:
73	ldr	r8, =S5PC100_CLOCK_BASE		@ 0xE0100000
74
75	/* Set Clock divider */
76	ldr	r1, =0x00011110
77	str	r1, [r8, #0x304]
78	ldr	r1, =0x1
79	str	r1, [r8, #0x308]
80	ldr	r1, =0x00011301
81	str	r1, [r8, #0x300]
82
83	/* Set Lock Time */
84	ldr	r1, =0xe10			@ Locktime : 0xe10 = 3600
85	str	r1, [r8, #0x000]		@ APLL_LOCK
86	str	r1, [r8, #0x004]		@ MPLL_LOCK
87	str	r1, [r8, #0x008]		@ EPLL_LOCK
88	str	r1, [r8, #0x00C]		@ HPLL_LOCK
89
90	/* APLL_CON */
91	ldr	r1, =0x81bc0400		@ SDIV 0, PDIV 4, MDIV 444 (1332MHz)
92	str	r1, [r8, #0x100]
93	/* MPLL_CON */
94	ldr	r1, =0x80590201		@ SDIV 1, PDIV 2, MDIV 89 (267MHz)
95	str	r1, [r8, #0x104]
96	/* EPLL_CON */
97	ldr	r1, =0x80870303		@ SDIV 3, PDIV 3, MDIV 135 (67.5MHz)
98	str	r1, [r8, #0x108]
99	/* HPLL_CON */
100	ldr	r1, =0x80600603
101	str	r1, [r8, #0x10C]
102
103	/* Set Source Clock */
104	ldr	r1, =0x1111			@ A, M, E, HPLL Muxing
105	str	r1, [r8, #0x200]		@ CLK_SRC0
106
107	ldr	r1, =0x1000001			@ Uart Clock & CLK48M Muxing
108	str	r1, [r8, #0x204]		@ CLK_SRC1
109
110	ldr	r1, =0x9000			@ ARMCLK/4
111	str	r1, [r8, #0x400]		@ CLK_OUT
112
113	/* wait at least 200us to stablize all clock */
114	mov	r2, #0x10000
1151:	subs	r2, r2, #1
116	bne	1b
117
118	mov	pc, lr
119
120/*
121 * uart_asm_init: Initialize UART's pins
122 */
123uart_asm_init:
124	mov	r0, r8
125	ldr	r1, =0x22222222
126	str	r1, [r0, #0x0]			@ GPA0_CON
127	ldr	r1, =0x00022222
128	str	r1, [r0, #0x20]			@ GPA1_CON
129
130	mov	pc, lr
131
132/*
133 * tzpc_asm_init: Initialize TZPC
134 */
135tzpc_asm_init:
136	ldr	r0, =0xE3800000
137	mov	r1, #0x0
138	str	r1, [r0]
139	mov	r1, #0xff
140	str	r1, [r0, #0x804]
141	str	r1, [r0, #0x810]
142
143	ldr	r0, =0xE2800000
144	str	r1, [r0, #0x804]
145	str	r1, [r0, #0x810]
146	str	r1, [r0, #0x81C]
147
148	ldr	r0, =0xE2900000
149	str	r1, [r0, #0x804]
150	str	r1, [r0, #0x810]
151
152	mov	pc, lr
153