1/*
2 * Copyright (C) 2009 Samsung Electronics
3 * Kyungmin Park <kyungmin.park@samsung.com>
4 * Minkyu Kang <mk7.kang@samsung.com>
5 *
6 * SPDX-License-Identifier:	GPL-2.0+
7 */
8
9#include <config.h>
10#include <version.h>
11#include <asm/arch/cpu.h>
12#include <asm/arch/power.h>
13
14/*
15 * Register usages:
16 *
17 * r5 has zero always
18 */
19
20_TEXT_BASE:
21	.word	CONFIG_SYS_TEXT_BASE
22
23	.globl lowlevel_init
24lowlevel_init:
25	mov	r9, lr
26
27	/* r5 has always zero */
28	mov	r5, #0
29
30	ldr	r8, =S5PC100_GPIO_BASE
31
32	/* Disable Watchdog */
33	ldr	r0, =S5PC100_WATCHDOG_BASE		@0xEA200000
34	orr	r0, r0, #0x0
35	str	r5, [r0]
36
37	/* setting SRAM */
38	ldr	r0, =S5PC100_SROMC_BASE
39	ldr	r1, =0x9
40	str	r1, [r0]
41
42	/* S5PC100 has 3 groups of interrupt sources */
43	ldr	r0, =S5PC100_VIC0_BASE			@0xE4000000
44	ldr	r1, =S5PC100_VIC1_BASE			@0xE4000000
45	ldr	r2, =S5PC100_VIC2_BASE			@0xE4000000
46
47	/* Disable all interrupts (VIC0, VIC1 and VIC2) */
48	mvn	r3, #0x0
49	str	r3, [r0, #0x14]				@INTENCLEAR
50	str	r3, [r1, #0x14]				@INTENCLEAR
51	str	r3, [r2, #0x14]				@INTENCLEAR
52
53	/* Set all interrupts as IRQ */
54	str	r5, [r0, #0xc]				@INTSELECT
55	str	r5, [r1, #0xc]				@INTSELECT
56	str	r5, [r2, #0xc]				@INTSELECT
57
58	/* Pending Interrupt Clear */
59	str	r5, [r0, #0xf00]			@INTADDRESS
60	str	r5, [r1, #0xf00]			@INTADDRESS
61	str	r5, [r2, #0xf00]			@INTADDRESS
62
63	/* for UART */
64	bl uart_asm_init
65
66	/* for TZPC */
67	bl tzpc_asm_init
68
691:
70	mov	lr, r9
71	mov	pc, lr
72
73/*
74 * system_clock_init: Initialize core clock and bus clock.
75 * void system_clock_init(void)
76 */
77system_clock_init:
78	ldr	r8, =S5PC100_CLOCK_BASE		@ 0xE0100000
79
80	/* Set Clock divider */
81	ldr	r1, =0x00011110
82	str	r1, [r8, #0x304]
83	ldr	r1, =0x1
84	str	r1, [r8, #0x308]
85	ldr	r1, =0x00011301
86	str	r1, [r8, #0x300]
87
88	/* Set Lock Time */
89	ldr	r1, =0xe10			@ Locktime : 0xe10 = 3600
90	str	r1, [r8, #0x000]		@ APLL_LOCK
91	str	r1, [r8, #0x004]		@ MPLL_LOCK
92	str	r1, [r8, #0x008]		@ EPLL_LOCK
93	str	r1, [r8, #0x00C]		@ HPLL_LOCK
94
95	/* APLL_CON */
96	ldr	r1, =0x81bc0400		@ SDIV 0, PDIV 4, MDIV 444 (1332MHz)
97	str	r1, [r8, #0x100]
98	/* MPLL_CON */
99	ldr	r1, =0x80590201		@ SDIV 1, PDIV 2, MDIV 89 (267MHz)
100	str	r1, [r8, #0x104]
101	/* EPLL_CON */
102	ldr	r1, =0x80870303		@ SDIV 3, PDIV 3, MDIV 135 (67.5MHz)
103	str	r1, [r8, #0x108]
104	/* HPLL_CON */
105	ldr	r1, =0x80600603
106	str	r1, [r8, #0x10C]
107
108	/* Set Source Clock */
109	ldr	r1, =0x1111			@ A, M, E, HPLL Muxing
110	str	r1, [r8, #0x200]		@ CLK_SRC0
111
112	ldr	r1, =0x1000001			@ Uart Clock & CLK48M Muxing
113	str	r1, [r8, #0x204]		@ CLK_SRC1
114
115	ldr	r1, =0x9000			@ ARMCLK/4
116	str	r1, [r8, #0x400]		@ CLK_OUT
117
118	/* wait at least 200us to stablize all clock */
119	mov	r2, #0x10000
1201:	subs	r2, r2, #1
121	bne	1b
122
123	mov	pc, lr
124
125/*
126 * uart_asm_init: Initialize UART's pins
127 */
128uart_asm_init:
129	mov	r0, r8
130	ldr	r1, =0x22222222
131	str	r1, [r0, #0x0]			@ GPA0_CON
132	ldr	r1, =0x00022222
133	str	r1, [r0, #0x20]			@ GPA1_CON
134
135	mov	pc, lr
136
137/*
138 * tzpc_asm_init: Initialize TZPC
139 */
140tzpc_asm_init:
141	ldr	r0, =0xE3800000
142	mov	r1, #0x0
143	str	r1, [r0]
144	mov	r1, #0xff
145	str	r1, [r0, #0x804]
146	str	r1, [r0, #0x810]
147
148	ldr	r0, =0xE2800000
149	str	r1, [r0, #0x804]
150	str	r1, [r0, #0x810]
151	str	r1, [r0, #0x81C]
152
153	ldr	r0, =0xE2900000
154	str	r1, [r0, #0x804]
155	str	r1, [r0, #0x810]
156
157	mov	pc, lr
158