1/*
2 * Copyright (C) 2009 Samsung Electronics
3 * Kyungmin Park <kyungmin.park@samsung.com>
4 * Minkyu Kang <mk7.kang@samsung.com>
5 *
6 * See file CREDITS for list of people who contributed to this
7 * project.
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
22 * MA 02111-1307 USA
23 */
24
25#include <config.h>
26#include <version.h>
27#include <asm/arch/cpu.h>
28#include <asm/arch/power.h>
29
30/*
31 * Register usages:
32 *
33 * r5 has zero always
34 */
35
36_TEXT_BASE:
37	.word	CONFIG_SYS_TEXT_BASE
38
39	.globl lowlevel_init
40lowlevel_init:
41	mov	r9, lr
42
43	/* r5 has always zero */
44	mov	r5, #0
45
46	ldr	r8, =S5PC100_GPIO_BASE
47
48	/* Disable Watchdog */
49	ldr	r0, =S5PC100_WATCHDOG_BASE		@0xEA200000
50	orr	r0, r0, #0x0
51	str	r5, [r0]
52
53	/* setting SRAM */
54	ldr	r0, =S5PC100_SROMC_BASE
55	ldr	r1, =0x9
56	str	r1, [r0]
57
58	/* S5PC100 has 3 groups of interrupt sources */
59	ldr	r0, =S5PC100_VIC0_BASE			@0xE4000000
60	ldr	r1, =S5PC100_VIC1_BASE			@0xE4000000
61	ldr	r2, =S5PC100_VIC2_BASE			@0xE4000000
62
63	/* Disable all interrupts (VIC0, VIC1 and VIC2) */
64	mvn	r3, #0x0
65	str	r3, [r0, #0x14]				@INTENCLEAR
66	str	r3, [r1, #0x14]				@INTENCLEAR
67	str	r3, [r2, #0x14]				@INTENCLEAR
68
69	/* Set all interrupts as IRQ */
70	str	r5, [r0, #0xc]				@INTSELECT
71	str	r5, [r1, #0xc]				@INTSELECT
72	str	r5, [r2, #0xc]				@INTSELECT
73
74	/* Pending Interrupt Clear */
75	str	r5, [r0, #0xf00]			@INTADDRESS
76	str	r5, [r1, #0xf00]			@INTADDRESS
77	str	r5, [r2, #0xf00]			@INTADDRESS
78
79	/* for UART */
80	bl uart_asm_init
81
82	/* for TZPC */
83	bl tzpc_asm_init
84
851:
86	mov	lr, r9
87	mov	pc, lr
88
89/*
90 * system_clock_init: Initialize core clock and bus clock.
91 * void system_clock_init(void)
92 */
93system_clock_init:
94	ldr	r8, =S5PC100_CLOCK_BASE		@ 0xE0100000
95
96	/* Set Clock divider */
97	ldr	r1, =0x00011110
98	str	r1, [r8, #0x304]
99	ldr	r1, =0x1
100	str	r1, [r8, #0x308]
101	ldr	r1, =0x00011301
102	str	r1, [r8, #0x300]
103
104	/* Set Lock Time */
105	ldr	r1, =0xe10			@ Locktime : 0xe10 = 3600
106	str	r1, [r8, #0x000]		@ APLL_LOCK
107	str	r1, [r8, #0x004]		@ MPLL_LOCK
108	str	r1, [r8, #0x008]		@ EPLL_LOCK
109	str	r1, [r8, #0x00C]		@ HPLL_LOCK
110
111	/* APLL_CON */
112	ldr	r1, =0x81bc0400		@ SDIV 0, PDIV 4, MDIV 444 (1332MHz)
113	str	r1, [r8, #0x100]
114	/* MPLL_CON */
115	ldr	r1, =0x80590201		@ SDIV 1, PDIV 2, MDIV 89 (267MHz)
116	str	r1, [r8, #0x104]
117	/* EPLL_CON */
118	ldr	r1, =0x80870303		@ SDIV 3, PDIV 3, MDIV 135 (67.5MHz)
119	str	r1, [r8, #0x108]
120	/* HPLL_CON */
121	ldr	r1, =0x80600603
122	str	r1, [r8, #0x10C]
123
124	/* Set Source Clock */
125	ldr	r1, =0x1111			@ A, M, E, HPLL Muxing
126	str	r1, [r8, #0x200]		@ CLK_SRC0
127
128	ldr	r1, =0x1000001			@ Uart Clock & CLK48M Muxing
129	str	r1, [r8, #0x204]		@ CLK_SRC1
130
131	ldr	r1, =0x9000			@ ARMCLK/4
132	str	r1, [r8, #0x400]		@ CLK_OUT
133
134	/* wait at least 200us to stablize all clock */
135	mov	r2, #0x10000
1361:	subs	r2, r2, #1
137	bne	1b
138
139	mov	pc, lr
140
141/*
142 * uart_asm_init: Initialize UART's pins
143 */
144uart_asm_init:
145	mov	r0, r8
146	ldr	r1, =0x22222222
147	str	r1, [r0, #0x0]			@ GPA0_CON
148	ldr	r1, =0x00022222
149	str	r1, [r0, #0x20]			@ GPA1_CON
150
151	mov	pc, lr
152
153/*
154 * tzpc_asm_init: Initialize TZPC
155 */
156tzpc_asm_init:
157	ldr	r0, =0xE3800000
158	mov	r1, #0x0
159	str	r1, [r0]
160	mov	r1, #0xff
161	str	r1, [r0, #0x804]
162	str	r1, [r0, #0x810]
163
164	ldr	r0, =0xE2800000
165	str	r1, [r0, #0x804]
166	str	r1, [r0, #0x810]
167	str	r1, [r0, #0x81C]
168
169	ldr	r0, =0xE2900000
170	str	r1, [r0, #0x804]
171	str	r1, [r0, #0x810]
172
173	mov	pc, lr
174