1/*
2 * Copyright (C) 2009 Samsung Electronics
3 * Kyungmin Park <kyungmin.park@samsung.com>
4 * Minkyu Kang <mk7.kang@samsung.com>
5 *
6 * See file CREDITS for list of people who contributed to this
7 * project.
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
22 * MA 02111-1307 USA
23 */
24
25#include <config.h>
26#include <version.h>
27#include <asm/arch/cpu.h>
28#include <asm/arch/power.h>
29
30/*
31 * Register usages:
32 *
33 * r5 has zero always
34 */
35
36_TEXT_BASE:
37	.word	CONFIG_SYS_TEXT_BASE
38
39	.globl lowlevel_init
40lowlevel_init:
41	mov	r9, lr
42
43	/* r5 has always zero */
44	mov	r5, #0
45
46	ldr	r8, =S5PC100_GPIO_BASE
47
48	/* Disable Watchdog */
49	ldr	r0, =S5PC100_WATCHDOG_BASE		@0xEA200000
50	orr	r0, r0, #0x0
51	str	r5, [r0]
52
53#ifndef CONFIG_ONENAND_IPL
54	/* setting SRAM */
55	ldr	r0, =S5PC100_SROMC_BASE
56	ldr	r1, =0x9
57	str	r1, [r0]
58#endif
59
60	/* S5PC100 has 3 groups of interrupt sources */
61	ldr	r0, =S5PC100_VIC0_BASE			@0xE4000000
62	ldr	r1, =S5PC100_VIC1_BASE			@0xE4000000
63	ldr	r2, =S5PC100_VIC2_BASE			@0xE4000000
64
65	/* Disable all interrupts (VIC0, VIC1 and VIC2) */
66	mvn	r3, #0x0
67	str	r3, [r0, #0x14]				@INTENCLEAR
68	str	r3, [r1, #0x14]				@INTENCLEAR
69	str	r3, [r2, #0x14]				@INTENCLEAR
70
71#ifndef CONFIG_ONENAND_IPL
72	/* Set all interrupts as IRQ */
73	str	r5, [r0, #0xc]				@INTSELECT
74	str	r5, [r1, #0xc]				@INTSELECT
75	str	r5, [r2, #0xc]				@INTSELECT
76
77	/* Pending Interrupt Clear */
78	str	r5, [r0, #0xf00]			@INTADDRESS
79	str	r5, [r1, #0xf00]			@INTADDRESS
80	str	r5, [r2, #0xf00]			@INTADDRESS
81#endif
82
83#ifndef CONFIG_ONENAND_IPL
84	/* for UART */
85	bl uart_asm_init
86
87	/* for TZPC */
88	bl tzpc_asm_init
89#endif
90
91#ifdef CONFIG_ONENAND_IPL
92	/* init system clock */
93	bl	system_clock_init
94
95	bl	mem_ctrl_asm_init
96
97	/* Wakeup support. Don't know if it's going to be used, untested. */
98	ldr	r0, =S5PC100_RST_STAT
99	ldr	r1, [r0]
100	bic	r1, r1, #0xfffffff7
101	cmp	r1, #0x8
102	beq	wakeup_reset
103#endif
104
1051:
106	mov	lr, r9
107	mov	pc, lr
108
109#ifdef CONFIG_ONENAND_IPL
110wakeup_reset:
111
112	/* Clear wakeup status register */
113	ldr	r0, =S5PC100_WAKEUP_STAT
114	ldr	r1, [r0]
115	str	r1, [r0]
116
117	/* Load return address and jump to kernel */
118	ldr	r0, =S5PC100_INFORM0
119
120	/* r1 = physical address of s5pc100_cpu_resume function */
121	ldr	r1, [r0]
122
123	/* Jump to kernel (sleep.S) */
124	mov	pc, r1
125	nop
126	nop
127#endif
128
129/*
130 * system_clock_init: Initialize core clock and bus clock.
131 * void system_clock_init(void)
132 */
133system_clock_init:
134	ldr	r8, =S5PC100_CLOCK_BASE		@ 0xE0100000
135
136	/* Set Clock divider */
137	ldr	r1, =0x00011110
138	str	r1, [r8, #0x304]
139	ldr	r1, =0x1
140	str	r1, [r8, #0x308]
141	ldr	r1, =0x00011301
142	str	r1, [r8, #0x300]
143
144	/* Set Lock Time */
145	ldr	r1, =0xe10			@ Locktime : 0xe10 = 3600
146	str	r1, [r8, #0x000]		@ APLL_LOCK
147	str	r1, [r8, #0x004]		@ MPLL_LOCK
148	str	r1, [r8, #0x008]		@ EPLL_LOCK
149	str	r1, [r8, #0x00C]		@ HPLL_LOCK
150
151	/* APLL_CON */
152	ldr	r1, =0x81bc0400		@ SDIV 0, PDIV 4, MDIV 444 (1332MHz)
153	str	r1, [r8, #0x100]
154	/* MPLL_CON */
155	ldr	r1, =0x80590201		@ SDIV 1, PDIV 2, MDIV 89 (267MHz)
156	str	r1, [r8, #0x104]
157	/* EPLL_CON */
158	ldr	r1, =0x80870303		@ SDIV 3, PDIV 3, MDIV 135 (67.5MHz)
159	str	r1, [r8, #0x108]
160	/* HPLL_CON */
161	ldr	r1, =0x80600603
162	str	r1, [r8, #0x10C]
163
164	/* Set Source Clock */
165	ldr	r1, =0x1111			@ A, M, E, HPLL Muxing
166	str	r1, [r8, #0x200]		@ CLK_SRC0
167
168	ldr	r1, =0x1000001			@ Uart Clock & CLK48M Muxing
169	str	r1, [r8, #0x204]		@ CLK_SRC1
170
171	ldr	r1, =0x9000			@ ARMCLK/4
172	str	r1, [r8, #0x400]		@ CLK_OUT
173
174	/* wait at least 200us to stablize all clock */
175	mov	r2, #0x10000
1761:	subs	r2, r2, #1
177	bne	1b
178
179	mov	pc, lr
180
181#ifndef CONFIG_ONENAND_IPL
182/*
183 * uart_asm_init: Initialize UART's pins
184 */
185uart_asm_init:
186	mov	r0, r8
187	ldr	r1, =0x22222222
188	str	r1, [r0, #0x0]			@ GPA0_CON
189	ldr	r1, =0x00022222
190	str	r1, [r0, #0x20]			@ GPA1_CON
191
192	mov	pc, lr
193
194/*
195 * tzpc_asm_init: Initialize TZPC
196 */
197tzpc_asm_init:
198	ldr	r0, =0xE3800000
199	mov	r1, #0x0
200	str	r1, [r0]
201	mov	r1, #0xff
202	str	r1, [r0, #0x804]
203	str	r1, [r0, #0x810]
204
205	ldr	r0, =0xE2800000
206	str	r1, [r0, #0x804]
207	str	r1, [r0, #0x810]
208	str	r1, [r0, #0x81C]
209
210	ldr	r0, =0xE2900000
211	str	r1, [r0, #0x804]
212	str	r1, [r0, #0x810]
213
214	mov	pc, lr
215#endif
216