1/*
2 * Copyright (C) 2009 Samsung Electronics
3 * Kyungmin Park <kyungmin.park@samsung.com>
4 * Minkyu Kang <mk7.kang@samsung.com>
5 *
6 * SPDX-License-Identifier:	GPL-2.0+
7 */
8
9#include <config.h>
10#include <version.h>
11#include <asm/arch/cpu.h>
12#include <asm/arch/power.h>
13
14/*
15 * Register usages:
16 *
17 * r5 has zero always
18 */
19
20	.globl lowlevel_init
21lowlevel_init:
22	mov	r9, lr
23
24	/* r5 has always zero */
25	mov	r5, #0
26
27	ldr	r8, =S5PC100_GPIO_BASE
28
29	/* Disable Watchdog */
30	ldr	r0, =S5PC100_WATCHDOG_BASE		@0xEA200000
31	orr	r0, r0, #0x0
32	str	r5, [r0]
33
34	/* setting SRAM */
35	ldr	r0, =S5PC100_SROMC_BASE
36	ldr	r1, =0x9
37	str	r1, [r0]
38
39	/* S5PC100 has 3 groups of interrupt sources */
40	ldr	r0, =S5PC100_VIC0_BASE			@0xE4000000
41	ldr	r1, =S5PC100_VIC1_BASE			@0xE4000000
42	ldr	r2, =S5PC100_VIC2_BASE			@0xE4000000
43
44	/* Disable all interrupts (VIC0, VIC1 and VIC2) */
45	mvn	r3, #0x0
46	str	r3, [r0, #0x14]				@INTENCLEAR
47	str	r3, [r1, #0x14]				@INTENCLEAR
48	str	r3, [r2, #0x14]				@INTENCLEAR
49
50	/* Set all interrupts as IRQ */
51	str	r5, [r0, #0xc]				@INTSELECT
52	str	r5, [r1, #0xc]				@INTSELECT
53	str	r5, [r2, #0xc]				@INTSELECT
54
55	/* Pending Interrupt Clear */
56	str	r5, [r0, #0xf00]			@INTADDRESS
57	str	r5, [r1, #0xf00]			@INTADDRESS
58	str	r5, [r2, #0xf00]			@INTADDRESS
59
60	/* for UART */
61	bl uart_asm_init
62
63	/* for TZPC */
64	bl tzpc_asm_init
65
661:
67	mov	lr, r9
68	mov	pc, lr
69
70/*
71 * system_clock_init: Initialize core clock and bus clock.
72 * void system_clock_init(void)
73 */
74system_clock_init:
75	ldr	r8, =S5PC100_CLOCK_BASE		@ 0xE0100000
76
77	/* Set Clock divider */
78	ldr	r1, =0x00011110
79	str	r1, [r8, #0x304]
80	ldr	r1, =0x1
81	str	r1, [r8, #0x308]
82	ldr	r1, =0x00011301
83	str	r1, [r8, #0x300]
84
85	/* Set Lock Time */
86	ldr	r1, =0xe10			@ Locktime : 0xe10 = 3600
87	str	r1, [r8, #0x000]		@ APLL_LOCK
88	str	r1, [r8, #0x004]		@ MPLL_LOCK
89	str	r1, [r8, #0x008]		@ EPLL_LOCK
90	str	r1, [r8, #0x00C]		@ HPLL_LOCK
91
92	/* APLL_CON */
93	ldr	r1, =0x81bc0400		@ SDIV 0, PDIV 4, MDIV 444 (1332MHz)
94	str	r1, [r8, #0x100]
95	/* MPLL_CON */
96	ldr	r1, =0x80590201		@ SDIV 1, PDIV 2, MDIV 89 (267MHz)
97	str	r1, [r8, #0x104]
98	/* EPLL_CON */
99	ldr	r1, =0x80870303		@ SDIV 3, PDIV 3, MDIV 135 (67.5MHz)
100	str	r1, [r8, #0x108]
101	/* HPLL_CON */
102	ldr	r1, =0x80600603
103	str	r1, [r8, #0x10C]
104
105	/* Set Source Clock */
106	ldr	r1, =0x1111			@ A, M, E, HPLL Muxing
107	str	r1, [r8, #0x200]		@ CLK_SRC0
108
109	ldr	r1, =0x1000001			@ Uart Clock & CLK48M Muxing
110	str	r1, [r8, #0x204]		@ CLK_SRC1
111
112	ldr	r1, =0x9000			@ ARMCLK/4
113	str	r1, [r8, #0x400]		@ CLK_OUT
114
115	/* wait at least 200us to stablize all clock */
116	mov	r2, #0x10000
1171:	subs	r2, r2, #1
118	bne	1b
119
120	mov	pc, lr
121
122/*
123 * uart_asm_init: Initialize UART's pins
124 */
125uart_asm_init:
126	mov	r0, r8
127	ldr	r1, =0x22222222
128	str	r1, [r0, #0x0]			@ GPA0_CON
129	ldr	r1, =0x00022222
130	str	r1, [r0, #0x20]			@ GPA1_CON
131
132	mov	pc, lr
133
134/*
135 * tzpc_asm_init: Initialize TZPC
136 */
137tzpc_asm_init:
138	ldr	r0, =0xE3800000
139	mov	r1, #0x0
140	str	r1, [r0]
141	mov	r1, #0xff
142	str	r1, [r0, #0x804]
143	str	r1, [r0, #0x810]
144
145	ldr	r0, =0xE2800000
146	str	r1, [r0, #0x804]
147	str	r1, [r0, #0x810]
148	str	r1, [r0, #0x81C]
149
150	ldr	r0, =0xE2900000
151	str	r1, [r0, #0x804]
152	str	r1, [r0, #0x810]
153
154	mov	pc, lr
155