1 /* 2 * Copyright (C) 2014 Samsung Electronics 3 * Przemyslaw Marczak <p.marczak@samsung.com> 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8 #ifndef __ODROIDU3_SETUP__ 9 #define __ODROIDU3_SETUP__ 10 11 /* A/M PLL_CON0 */ 12 #define SDIV(x) ((x) & 0x7) 13 #define PDIV(x) (((x) & 0x3f) << 8) 14 #define MDIV(x) (((x) & 0x3ff) << 16) 15 #define FSEL(x) (((x) & 0x1) << 27) 16 #define PLL_LOCKED_BIT (0x1 << 29) 17 #define PLL_ENABLE(x) (((x) & 0x1) << 31) 18 19 /* CLK_SRC_CPU */ 20 #define MUX_APLL_SEL(x) ((x) & 0x1) 21 #define MUX_CORE_SEL(x) (((x) & 0x1) << 16) 22 #define MUX_HPM_SEL(x) (((x) & 0x1) << 20) 23 #define MUX_MPLL_USER_SEL_C(x) (((x) & 0x1) << 24) 24 25 #define MUX_STAT_CHANGING 0x100 26 27 /* CLK_MUX_STAT_CPU */ 28 #define APLL_SEL(x) ((x) & 0x7) 29 #define CORE_SEL(x) (((x) & 0x7) << 16) 30 #define HPM_SEL(x) (((x) & 0x7) << 20) 31 #define MPLL_USER_SEL_C(x) (((x) & 0x7) << 24) 32 #define MUX_STAT_CPU_CHANGING (APLL_SEL(MUX_STAT_CHANGING) | \ 33 CORE_SEL(MUX_STAT_CHANGING) | \ 34 HPM_SEL(MUX_STAT_CHANGING) | \ 35 MPLL_USER_SEL_C(MUX_STAT_CHANGING)) 36 37 /* CLK_DIV_CPU0 */ 38 #define CORE_RATIO(x) ((x) & 0x7) 39 #define COREM0_RATIO(x) (((x) & 0x7) << 4) 40 #define COREM1_RATIO(x) (((x) & 0x7) << 8) 41 #define PERIPH_RATIO(x) (((x) & 0x7) << 12) 42 #define ATB_RATIO(x) (((x) & 0x7) << 16) 43 #define PCLK_DBG_RATIO(x) (((x) & 0x7) << 20) 44 #define APLL_RATIO(x) (((x) & 0x7) << 24) 45 #define CORE2_RATIO(x) (((x) & 0x7) << 28) 46 47 /* CLK_DIV_STAT_CPU0 */ 48 #define DIV_CORE(x) ((x) & 0x1) 49 #define DIV_COREM0(x) (((x) & 0x1) << 4) 50 #define DIV_COREM1(x) (((x) & 0x1) << 8) 51 #define DIV_PERIPH(x) (((x) & 0x1) << 12) 52 #define DIV_ATB(x) (((x) & 0x1) << 16) 53 #define DIV_PCLK_DBG(x) (((x) & 0x1) << 20) 54 #define DIV_APLL(x) (((x) & 0x1) << 24) 55 #define DIV_CORE2(x) (((x) & 0x1) << 28) 56 57 #define DIV_STAT_CHANGING 0x1 58 #define DIV_STAT_CPU0_CHANGING (DIV_CORE(DIV_STAT_CHANGING) | \ 59 DIV_COREM0(DIV_STAT_CHANGING) | \ 60 DIV_COREM1(DIV_STAT_CHANGING) | \ 61 DIV_PERIPH(DIV_STAT_CHANGING) | \ 62 DIV_ATB(DIV_STAT_CHANGING) | \ 63 DIV_PCLK_DBG(DIV_STAT_CHANGING) | \ 64 DIV_APLL(DIV_STAT_CHANGING) | \ 65 DIV_CORE2(DIV_STAT_CHANGING)) 66 67 /* CLK_DIV_CPU1 */ 68 #define COPY_RATIO(x) ((x) & 0x7) 69 #define HPM_RATIO(x) (((x) & 0x7) << 4) 70 #define CORES_RATIO(x) (((x) & 0x7) << 8) 71 72 /* CLK_DIV_STAT_CPU1 */ 73 #define DIV_COPY(x) ((x) & 0x7) 74 #define DIV_HPM(x) (((x) & 0x1) << 4) 75 #define DIV_CORES(x) (((x) & 0x1) << 8) 76 77 #define DIV_STAT_CPU1_CHANGING (DIV_COPY(DIV_STAT_CHANGING) | \ 78 DIV_HPM(DIV_STAT_CHANGING) | \ 79 DIV_CORES(DIV_STAT_CHANGING)) 80 81 /* CLK_SRC_DMC */ 82 #define MUX_C2C_SEL(x) ((x) & 0x1) 83 #define MUX_DMC_BUS_SEL(x) (((x) & 0x1) << 4) 84 #define MUX_DPHY_SEL(x) (((x) & 0x1) << 8) 85 #define MUX_MPLL_SEL(x) (((x) & 0x1) << 12) 86 #define MUX_PWI_SEL(x) (((x) & 0xf) << 16) 87 #define MUX_G2D_ACP0_SEL(x) (((x) & 0x1) << 20) 88 #define MUX_G2D_ACP1_SEL(x) (((x) & 0x1) << 24) 89 #define MUX_G2D_ACP_SEL(x) (((x) & 0x1) << 28) 90 91 /* CLK_MUX_STAT_DMC */ 92 #define C2C_SEL(x) (((x)) & 0x7) 93 #define DMC_BUS_SEL(x) (((x) & 0x7) << 4) 94 #define DPHY_SEL(x) (((x) & 0x7) << 8) 95 #define MPLL_SEL(x) (((x) & 0x7) << 12) 96 /* #define PWI_SEL(x) (((x) & 0xf) << 16) - Reserved */ 97 #define G2D_ACP0_SEL(x) (((x) & 0x7) << 20) 98 #define G2D_ACP1_SEL(x) (((x) & 0x7) << 24) 99 #define G2D_ACP_SEL(x) (((x) & 0x7) << 28) 100 101 #define MUX_STAT_DMC_CHANGING (C2C_SEL(MUX_STAT_CHANGING) | \ 102 DMC_BUS_SEL(MUX_STAT_CHANGING) | \ 103 DPHY_SEL(MUX_STAT_CHANGING) | \ 104 MPLL_SEL(MUX_STAT_CHANGING) |\ 105 G2D_ACP0_SEL(MUX_STAT_CHANGING) | \ 106 G2D_ACP1_SEL(MUX_STAT_CHANGING) | \ 107 G2D_ACP_SEL(MUX_STAT_CHANGING)) 108 109 /* CLK_DIV_DMC0 */ 110 #define ACP_RATIO(x) ((x) & 0x7) 111 #define ACP_PCLK_RATIO(x) (((x) & 0x7) << 4) 112 #define DPHY_RATIO(x) (((x) & 0x7) << 8) 113 #define DMC_RATIO(x) (((x) & 0x7) << 12) 114 #define DMCD_RATIO(x) (((x) & 0x7) << 16) 115 #define DMCP_RATIO(x) (((x) & 0x7) << 20) 116 117 /* CLK_DIV_STAT_DMC0 */ 118 #define DIV_ACP(x) ((x) & 0x1) 119 #define DIV_ACP_PCLK(x) (((x) & 0x1) << 4) 120 #define DIV_DPHY(x) (((x) & 0x1) << 8) 121 #define DIV_DMC(x) (((x) & 0x1) << 12) 122 #define DIV_DMCD(x) (((x) & 0x1) << 16) 123 #define DIV_DMCP(x) (((x) & 0x1) << 20) 124 125 #define DIV_STAT_DMC0_CHANGING (DIV_ACP(DIV_STAT_CHANGING) | \ 126 DIV_ACP_PCLK(DIV_STAT_CHANGING) | \ 127 DIV_DPHY(DIV_STAT_CHANGING) | \ 128 DIV_DMC(DIV_STAT_CHANGING) | \ 129 DIV_DMCD(DIV_STAT_CHANGING) | \ 130 DIV_DMCP(DIV_STAT_CHANGING)) 131 132 /* CLK_DIV_DMC1 */ 133 #define G2D_ACP_RATIO(x) ((x) & 0xf) 134 #define C2C_RATIO(x) (((x) & 0x7) << 4) 135 #define PWI_RATIO(x) (((x) & 0xf) << 8) 136 #define C2C_ACLK_RATIO(x) (((x) & 0x7) << 12) 137 #define DVSEM_RATIO(x) (((x) & 0x7f) << 16) 138 #define DPM_RATIO(x) (((x) & 0x7f) << 24) 139 140 /* CLK_DIV_STAT_DMC1 */ 141 #define DIV_G2D_ACP(x) ((x) & 0x1) 142 #define DIV_C2C(x) (((x) & 0x1) << 4) 143 #define DIV_PWI(x) (((x) & 0x1) << 8) 144 #define DIV_C2C_ACLK(x) (((x) & 0x1) << 12) 145 #define DIV_DVSEM(x) (((x) & 0x1) << 16) 146 #define DIV_DPM(x) (((x) & 0x1) << 24) 147 148 #define DIV_STAT_DMC1_CHANGING (DIV_G2D_ACP(DIV_STAT_CHANGING) | \ 149 DIV_C2C(DIV_STAT_CHANGING) | \ 150 DIV_PWI(DIV_STAT_CHANGING) | \ 151 DIV_C2C_ACLK(DIV_STAT_CHANGING) | \ 152 DIV_DVSEM(DIV_STAT_CHANGING) | \ 153 DIV_DPM(DIV_STAT_CHANGING)) 154 155 /* Set CLK_SRC_PERIL0 */ 156 #define UART4_SEL(x) (((x) & 0xf) << 16) 157 #define UART3_SEL(x) (((x) & 0xf) << 12) 158 #define UART2_SEL(x) (((x) & 0xf) << 8) 159 #define UART1_SEL(x) (((x) & 0xf) << 4) 160 #define UART0_SEL(x) ((x) & 0xf) 161 162 /* Set CLK_DIV_PERIL0 */ 163 #define UART4_RATIO(x) (((x) & 0xf) << 16) 164 #define UART3_RATIO(x) (((x) & 0xf) << 12) 165 #define UART2_RATIO(x) (((x) & 0xf) << 8) 166 #define UART1_RATIO(x) (((x) & 0xf) << 4) 167 #define UART0_RATIO(x) ((x) & 0xf) 168 169 /* Set CLK_DIV_STAT_PERIL0 */ 170 #define DIV_UART4(x) (((x) & 0x1) << 16) 171 #define DIV_UART3(x) (((x) & 0x1) << 12) 172 #define DIV_UART2(x) (((x) & 0x1) << 8) 173 #define DIV_UART1(x) (((x) & 0x1) << 4) 174 #define DIV_UART0(x) ((x) & 0x1) 175 176 #define DIV_STAT_PERIL0_CHANGING (DIV_UART4(DIV_STAT_CHANGING) | \ 177 DIV_UART3(DIV_STAT_CHANGING) | \ 178 DIV_UART2(DIV_STAT_CHANGING) | \ 179 DIV_UART1(DIV_STAT_CHANGING) | \ 180 DIV_UART0(DIV_STAT_CHANGING)) 181 182 /* CLK_DIV_FSYS1 */ 183 #define MMC0_RATIO(x) ((x) & 0xf) 184 #define MMC0_PRE_RATIO(x) (((x) & 0xff) << 8) 185 #define MMC1_RATIO(x) (((x) & 0xf) << 16) 186 #define MMC1_PRE_RATIO(x) (((x) & 0xff) << 24) 187 188 /* CLK_DIV_STAT_FSYS1 */ 189 #define DIV_MMC0(x) ((x) & 1) 190 #define DIV_MMC0_PRE(x) (((x) & 1) << 8) 191 #define DIV_MMC1(x) (((x) & 1) << 16) 192 #define DIV_MMC1_PRE(x) (((x) & 1) << 24) 193 194 #define DIV_STAT_FSYS1_CHANGING (DIV_MMC0(DIV_STAT_CHANGING) | \ 195 DIV_MMC0_PRE(DIV_STAT_CHANGING) | \ 196 DIV_MMC1(DIV_STAT_CHANGING) | \ 197 DIV_MMC1_PRE(DIV_STAT_CHANGING)) 198 199 /* CLK_DIV_FSYS2 */ 200 #define MMC2_RATIO(x) ((x) & 0xf) 201 #define MMC2_PRE_RATIO(x) (((x) & 0xff) << 8) 202 #define MMC3_RATIO(x) (((x) & 0xf) << 16) 203 #define MMC3_PRE_RATIO(x) (((x) & 0xff) << 24) 204 205 /* CLK_DIV_STAT_FSYS2 */ 206 #define DIV_MMC2(x) ((x) & 0x1) 207 #define DIV_MMC2_PRE(x) (((x) & 0x1) << 8) 208 #define DIV_MMC3(x) (((x) & 0x1) << 16) 209 #define DIV_MMC3_PRE(x) (((x) & 0x1) << 24) 210 211 #define DIV_STAT_FSYS2_CHANGING (DIV_MMC2(DIV_STAT_CHANGING) | \ 212 DIV_MMC2_PRE(DIV_STAT_CHANGING) | \ 213 DIV_MMC3(DIV_STAT_CHANGING) | \ 214 DIV_MMC3_PRE(DIV_STAT_CHANGING)) 215 216 /* CLK_DIV_FSYS3 */ 217 #define MMC4_RATIO(x) ((x) & 0x7) 218 #define MMC4_PRE_RATIO(x) (((x) & 0xff) << 8) 219 220 /* CLK_DIV_STAT_FSYS3 */ 221 #define DIV_MMC4(x) ((x) & 0x1) 222 #define DIV_MMC4_PRE(x) (((x) & 0x1) << 8) 223 224 #define DIV_STAT_FSYS3_CHANGING (DIV_MMC4(DIV_STAT_CHANGING) | \ 225 DIV_MMC4_PRE(DIV_STAT_CHANGING)) 226 227 /* XCL205 GPIO config - Odroid U3 */ 228 #define XCL205_GPIO_BASE EXYNOS4X12_GPIO_PART1_BASE 229 #define XCL205_EN_GPIO_OFFSET 0x20 /* GPA1 */ 230 #define XCL205_EN_GPIO_PIN 1 231 #define XCL205_EN_GPIO_CON (XCL205_GPIO_BASE + \ 232 XCL205_EN_GPIO_OFFSET) 233 #define XCL205_EN_GPIO_CON_CFG (S5P_GPIO_OUTPUT << \ 234 4 * XCL205_EN_GPIO_PIN) 235 #define XCL205_EN_GPIO_DAT_CFG (0x1 << XCL205_EN_GPIO_PIN) 236 #define XCL205_EN_GPIO_PUD_CFG (S5P_GPIO_PULL_UP << \ 237 2 * XCL205_EN_GPIO_PIN) 238 #define XCL205_EN_GPIO_DRV_CFG (S5P_GPIO_DRV_4X << \ 239 2 * XCL205_EN_GPIO_PIN) 240 241 #define XCL205_STATE_GPIO_OFFSET 0x80 /* GPC1 */ 242 #define XCL205_STATE_GPIO_PIN 2 243 #define XCL205_STATE_GPIO_CON (XCL205_GPIO_BASE + \ 244 XCL205_STATE_GPIO_OFFSET) 245 #define XCL205_STATE_GPIO_DAT XCL205_STATE_GPIO_CON + 0x4 246 #define XCL205_STATE_GPIO_CON_CFG (S5P_GPIO_INPUT << \ 247 4 * XCL205_STATE_GPIO_PIN) 248 #define XCL205_STATE_GPIO_PUD_CFG (S5P_GPIO_PULL_NONE << \ 249 2 * XCL205_STATE_GPIO_PIN) 250 251 #ifdef CONFIG_BOARD_TYPES 252 extern void sdelay(unsigned long); 253 #endif 254 255 #endif /*__ODROIDU3_SETUP__ */ 256