1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Copyright (C) 2014 Samsung Electronics 4 * Przemyslaw Marczak <p.marczak@samsung.com> 5 */ 6 7 #ifndef __ODROIDU3_SETUP__ 8 #define __ODROIDU3_SETUP__ 9 10 /* A/M PLL_CON0 */ 11 #define SDIV(x) ((x) & 0x7) 12 #define PDIV(x) (((x) & 0x3f) << 8) 13 #define MDIV(x) (((x) & 0x3ff) << 16) 14 #define FSEL(x) (((x) & 0x1) << 27) 15 #define PLL_LOCKED_BIT (0x1 << 29) 16 #define PLL_ENABLE(x) (((x) & 0x1) << 31) 17 18 /* CLK_SRC_CPU */ 19 #define MUX_APLL_SEL(x) ((x) & 0x1) 20 #define MUX_CORE_SEL(x) (((x) & 0x1) << 16) 21 #define MUX_HPM_SEL(x) (((x) & 0x1) << 20) 22 #define MUX_MPLL_USER_SEL_C(x) (((x) & 0x1) << 24) 23 24 #define MUX_STAT_CHANGING 0x100 25 26 /* CLK_MUX_STAT_CPU */ 27 #define APLL_SEL(x) ((x) & 0x7) 28 #define CORE_SEL(x) (((x) & 0x7) << 16) 29 #define HPM_SEL(x) (((x) & 0x7) << 20) 30 #define MPLL_USER_SEL_C(x) (((x) & 0x7) << 24) 31 #define MUX_STAT_CPU_CHANGING (APLL_SEL(MUX_STAT_CHANGING) | \ 32 CORE_SEL(MUX_STAT_CHANGING) | \ 33 HPM_SEL(MUX_STAT_CHANGING) | \ 34 MPLL_USER_SEL_C(MUX_STAT_CHANGING)) 35 36 /* CLK_DIV_CPU0 */ 37 #define CORE_RATIO(x) ((x) & 0x7) 38 #define COREM0_RATIO(x) (((x) & 0x7) << 4) 39 #define COREM1_RATIO(x) (((x) & 0x7) << 8) 40 #define PERIPH_RATIO(x) (((x) & 0x7) << 12) 41 #define ATB_RATIO(x) (((x) & 0x7) << 16) 42 #define PCLK_DBG_RATIO(x) (((x) & 0x7) << 20) 43 #define APLL_RATIO(x) (((x) & 0x7) << 24) 44 #define CORE2_RATIO(x) (((x) & 0x7) << 28) 45 46 /* CLK_DIV_STAT_CPU0 */ 47 #define DIV_CORE(x) ((x) & 0x1) 48 #define DIV_COREM0(x) (((x) & 0x1) << 4) 49 #define DIV_COREM1(x) (((x) & 0x1) << 8) 50 #define DIV_PERIPH(x) (((x) & 0x1) << 12) 51 #define DIV_ATB(x) (((x) & 0x1) << 16) 52 #define DIV_PCLK_DBG(x) (((x) & 0x1) << 20) 53 #define DIV_APLL(x) (((x) & 0x1) << 24) 54 #define DIV_CORE2(x) (((x) & 0x1) << 28) 55 56 #define DIV_STAT_CHANGING 0x1 57 #define DIV_STAT_CPU0_CHANGING (DIV_CORE(DIV_STAT_CHANGING) | \ 58 DIV_COREM0(DIV_STAT_CHANGING) | \ 59 DIV_COREM1(DIV_STAT_CHANGING) | \ 60 DIV_PERIPH(DIV_STAT_CHANGING) | \ 61 DIV_ATB(DIV_STAT_CHANGING) | \ 62 DIV_PCLK_DBG(DIV_STAT_CHANGING) | \ 63 DIV_APLL(DIV_STAT_CHANGING) | \ 64 DIV_CORE2(DIV_STAT_CHANGING)) 65 66 /* CLK_DIV_CPU1 */ 67 #define COPY_RATIO(x) ((x) & 0x7) 68 #define HPM_RATIO(x) (((x) & 0x7) << 4) 69 #define CORES_RATIO(x) (((x) & 0x7) << 8) 70 71 /* CLK_DIV_STAT_CPU1 */ 72 #define DIV_COPY(x) ((x) & 0x7) 73 #define DIV_HPM(x) (((x) & 0x1) << 4) 74 #define DIV_CORES(x) (((x) & 0x1) << 8) 75 76 #define DIV_STAT_CPU1_CHANGING (DIV_COPY(DIV_STAT_CHANGING) | \ 77 DIV_HPM(DIV_STAT_CHANGING) | \ 78 DIV_CORES(DIV_STAT_CHANGING)) 79 80 /* CLK_SRC_DMC */ 81 #define MUX_C2C_SEL(x) ((x) & 0x1) 82 #define MUX_DMC_BUS_SEL(x) (((x) & 0x1) << 4) 83 #define MUX_DPHY_SEL(x) (((x) & 0x1) << 8) 84 #define MUX_MPLL_SEL(x) (((x) & 0x1) << 12) 85 #define MUX_PWI_SEL(x) (((x) & 0xf) << 16) 86 #define MUX_G2D_ACP0_SEL(x) (((x) & 0x1) << 20) 87 #define MUX_G2D_ACP1_SEL(x) (((x) & 0x1) << 24) 88 #define MUX_G2D_ACP_SEL(x) (((x) & 0x1) << 28) 89 90 /* CLK_MUX_STAT_DMC */ 91 #define C2C_SEL(x) (((x)) & 0x7) 92 #define DMC_BUS_SEL(x) (((x) & 0x7) << 4) 93 #define DPHY_SEL(x) (((x) & 0x7) << 8) 94 #define MPLL_SEL(x) (((x) & 0x7) << 12) 95 /* #define PWI_SEL(x) (((x) & 0xf) << 16) - Reserved */ 96 #define G2D_ACP0_SEL(x) (((x) & 0x7) << 20) 97 #define G2D_ACP1_SEL(x) (((x) & 0x7) << 24) 98 #define G2D_ACP_SEL(x) (((x) & 0x7) << 28) 99 100 #define MUX_STAT_DMC_CHANGING (C2C_SEL(MUX_STAT_CHANGING) | \ 101 DMC_BUS_SEL(MUX_STAT_CHANGING) | \ 102 DPHY_SEL(MUX_STAT_CHANGING) | \ 103 MPLL_SEL(MUX_STAT_CHANGING) |\ 104 G2D_ACP0_SEL(MUX_STAT_CHANGING) | \ 105 G2D_ACP1_SEL(MUX_STAT_CHANGING) | \ 106 G2D_ACP_SEL(MUX_STAT_CHANGING)) 107 108 /* CLK_DIV_DMC0 */ 109 #define ACP_RATIO(x) ((x) & 0x7) 110 #define ACP_PCLK_RATIO(x) (((x) & 0x7) << 4) 111 #define DPHY_RATIO(x) (((x) & 0x7) << 8) 112 #define DMC_RATIO(x) (((x) & 0x7) << 12) 113 #define DMCD_RATIO(x) (((x) & 0x7) << 16) 114 #define DMCP_RATIO(x) (((x) & 0x7) << 20) 115 116 /* CLK_DIV_STAT_DMC0 */ 117 #define DIV_ACP(x) ((x) & 0x1) 118 #define DIV_ACP_PCLK(x) (((x) & 0x1) << 4) 119 #define DIV_DPHY(x) (((x) & 0x1) << 8) 120 #define DIV_DMC(x) (((x) & 0x1) << 12) 121 #define DIV_DMCD(x) (((x) & 0x1) << 16) 122 #define DIV_DMCP(x) (((x) & 0x1) << 20) 123 124 #define DIV_STAT_DMC0_CHANGING (DIV_ACP(DIV_STAT_CHANGING) | \ 125 DIV_ACP_PCLK(DIV_STAT_CHANGING) | \ 126 DIV_DPHY(DIV_STAT_CHANGING) | \ 127 DIV_DMC(DIV_STAT_CHANGING) | \ 128 DIV_DMCD(DIV_STAT_CHANGING) | \ 129 DIV_DMCP(DIV_STAT_CHANGING)) 130 131 /* CLK_DIV_DMC1 */ 132 #define G2D_ACP_RATIO(x) ((x) & 0xf) 133 #define C2C_RATIO(x) (((x) & 0x7) << 4) 134 #define PWI_RATIO(x) (((x) & 0xf) << 8) 135 #define C2C_ACLK_RATIO(x) (((x) & 0x7) << 12) 136 #define DVSEM_RATIO(x) (((x) & 0x7f) << 16) 137 #define DPM_RATIO(x) (((x) & 0x7f) << 24) 138 139 /* CLK_DIV_STAT_DMC1 */ 140 #define DIV_G2D_ACP(x) ((x) & 0x1) 141 #define DIV_C2C(x) (((x) & 0x1) << 4) 142 #define DIV_PWI(x) (((x) & 0x1) << 8) 143 #define DIV_C2C_ACLK(x) (((x) & 0x1) << 12) 144 #define DIV_DVSEM(x) (((x) & 0x1) << 16) 145 #define DIV_DPM(x) (((x) & 0x1) << 24) 146 147 #define DIV_STAT_DMC1_CHANGING (DIV_G2D_ACP(DIV_STAT_CHANGING) | \ 148 DIV_C2C(DIV_STAT_CHANGING) | \ 149 DIV_PWI(DIV_STAT_CHANGING) | \ 150 DIV_C2C_ACLK(DIV_STAT_CHANGING) | \ 151 DIV_DVSEM(DIV_STAT_CHANGING) | \ 152 DIV_DPM(DIV_STAT_CHANGING)) 153 154 /* Set CLK_SRC_PERIL0 */ 155 #define UART4_SEL(x) (((x) & 0xf) << 16) 156 #define UART3_SEL(x) (((x) & 0xf) << 12) 157 #define UART2_SEL(x) (((x) & 0xf) << 8) 158 #define UART1_SEL(x) (((x) & 0xf) << 4) 159 #define UART0_SEL(x) ((x) & 0xf) 160 161 /* Set CLK_DIV_PERIL0 */ 162 #define UART4_RATIO(x) (((x) & 0xf) << 16) 163 #define UART3_RATIO(x) (((x) & 0xf) << 12) 164 #define UART2_RATIO(x) (((x) & 0xf) << 8) 165 #define UART1_RATIO(x) (((x) & 0xf) << 4) 166 #define UART0_RATIO(x) ((x) & 0xf) 167 168 /* Set CLK_DIV_STAT_PERIL0 */ 169 #define DIV_UART4(x) (((x) & 0x1) << 16) 170 #define DIV_UART3(x) (((x) & 0x1) << 12) 171 #define DIV_UART2(x) (((x) & 0x1) << 8) 172 #define DIV_UART1(x) (((x) & 0x1) << 4) 173 #define DIV_UART0(x) ((x) & 0x1) 174 175 #define DIV_STAT_PERIL0_CHANGING (DIV_UART4(DIV_STAT_CHANGING) | \ 176 DIV_UART3(DIV_STAT_CHANGING) | \ 177 DIV_UART2(DIV_STAT_CHANGING) | \ 178 DIV_UART1(DIV_STAT_CHANGING) | \ 179 DIV_UART0(DIV_STAT_CHANGING)) 180 181 /* CLK_DIV_FSYS1 */ 182 #define MMC0_RATIO(x) ((x) & 0xf) 183 #define MMC0_PRE_RATIO(x) (((x) & 0xff) << 8) 184 #define MMC1_RATIO(x) (((x) & 0xf) << 16) 185 #define MMC1_PRE_RATIO(x) (((x) & 0xff) << 24) 186 187 /* CLK_DIV_STAT_FSYS1 */ 188 #define DIV_MMC0(x) ((x) & 1) 189 #define DIV_MMC0_PRE(x) (((x) & 1) << 8) 190 #define DIV_MMC1(x) (((x) & 1) << 16) 191 #define DIV_MMC1_PRE(x) (((x) & 1) << 24) 192 193 #define DIV_STAT_FSYS1_CHANGING (DIV_MMC0(DIV_STAT_CHANGING) | \ 194 DIV_MMC0_PRE(DIV_STAT_CHANGING) | \ 195 DIV_MMC1(DIV_STAT_CHANGING) | \ 196 DIV_MMC1_PRE(DIV_STAT_CHANGING)) 197 198 /* CLK_DIV_FSYS2 */ 199 #define MMC2_RATIO(x) ((x) & 0xf) 200 #define MMC2_PRE_RATIO(x) (((x) & 0xff) << 8) 201 #define MMC3_RATIO(x) (((x) & 0xf) << 16) 202 #define MMC3_PRE_RATIO(x) (((x) & 0xff) << 24) 203 204 /* CLK_DIV_STAT_FSYS2 */ 205 #define DIV_MMC2(x) ((x) & 0x1) 206 #define DIV_MMC2_PRE(x) (((x) & 0x1) << 8) 207 #define DIV_MMC3(x) (((x) & 0x1) << 16) 208 #define DIV_MMC3_PRE(x) (((x) & 0x1) << 24) 209 210 #define DIV_STAT_FSYS2_CHANGING (DIV_MMC2(DIV_STAT_CHANGING) | \ 211 DIV_MMC2_PRE(DIV_STAT_CHANGING) | \ 212 DIV_MMC3(DIV_STAT_CHANGING) | \ 213 DIV_MMC3_PRE(DIV_STAT_CHANGING)) 214 215 /* CLK_DIV_FSYS3 */ 216 #define MMC4_RATIO(x) ((x) & 0x7) 217 #define MMC4_PRE_RATIO(x) (((x) & 0xff) << 8) 218 219 /* CLK_DIV_STAT_FSYS3 */ 220 #define DIV_MMC4(x) ((x) & 0x1) 221 #define DIV_MMC4_PRE(x) (((x) & 0x1) << 8) 222 223 #define DIV_STAT_FSYS3_CHANGING (DIV_MMC4(DIV_STAT_CHANGING) | \ 224 DIV_MMC4_PRE(DIV_STAT_CHANGING)) 225 226 /* XCL205 GPIO config - Odroid U3 */ 227 #define XCL205_GPIO_BASE EXYNOS4X12_GPIO_PART1_BASE 228 #define XCL205_EN_GPIO_OFFSET 0x20 /* GPA1 */ 229 #define XCL205_EN_GPIO_PIN 1 230 #define XCL205_EN_GPIO_CON (XCL205_GPIO_BASE + \ 231 XCL205_EN_GPIO_OFFSET) 232 #define XCL205_EN_GPIO_CON_CFG (S5P_GPIO_OUTPUT << \ 233 4 * XCL205_EN_GPIO_PIN) 234 #define XCL205_EN_GPIO_DAT_CFG (0x1 << XCL205_EN_GPIO_PIN) 235 #define XCL205_EN_GPIO_PUD_CFG (S5P_GPIO_PULL_UP << \ 236 2 * XCL205_EN_GPIO_PIN) 237 #define XCL205_EN_GPIO_DRV_CFG (S5P_GPIO_DRV_4X << \ 238 2 * XCL205_EN_GPIO_PIN) 239 240 #define XCL205_STATE_GPIO_OFFSET 0x80 /* GPC1 */ 241 #define XCL205_STATE_GPIO_PIN 2 242 #define XCL205_STATE_GPIO_CON (XCL205_GPIO_BASE + \ 243 XCL205_STATE_GPIO_OFFSET) 244 #define XCL205_STATE_GPIO_DAT XCL205_STATE_GPIO_CON + 0x4 245 #define XCL205_STATE_GPIO_CON_CFG (S5P_GPIO_INPUT << \ 246 4 * XCL205_STATE_GPIO_PIN) 247 #define XCL205_STATE_GPIO_PUD_CFG (S5P_GPIO_PULL_NONE << \ 248 2 * XCL205_STATE_GPIO_PIN) 249 250 #ifdef CONFIG_BOARD_TYPES 251 extern void sdelay(unsigned long); 252 #endif 253 254 #endif /*__ODROIDU3_SETUP__ */ 255