1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Copyright (C) 2014 Samsung Electronics 4 * Przemyslaw Marczak <p.marczak@samsung.com> 5 */ 6 7 #include <common.h> 8 #include <asm/arch/pinmux.h> 9 #include <asm/arch/power.h> 10 #include <asm/arch/clock.h> 11 #include <asm/arch/gpio.h> 12 #include <asm/gpio.h> 13 #include <asm/arch/cpu.h> 14 #include <dm.h> 15 #include <power/pmic.h> 16 #include <power/regulator.h> 17 #include <power/max77686_pmic.h> 18 #include <errno.h> 19 #include <mmc.h> 20 #include <usb.h> 21 #include <usb/dwc2_udc.h> 22 #include <samsung/misc.h> 23 #include "setup.h" 24 25 DECLARE_GLOBAL_DATA_PTR; 26 27 #ifdef CONFIG_BOARD_TYPES 28 /* Odroid board types */ 29 enum { 30 ODROID_TYPE_U3, 31 ODROID_TYPE_X2, 32 ODROID_TYPES, 33 }; 34 35 void set_board_type(void) 36 { 37 /* Set GPA1 pin 1 to HI - enable XCL205 output */ 38 writel(XCL205_EN_GPIO_CON_CFG, XCL205_EN_GPIO_CON); 39 writel(XCL205_EN_GPIO_DAT_CFG, XCL205_EN_GPIO_CON + 0x4); 40 writel(XCL205_EN_GPIO_PUD_CFG, XCL205_EN_GPIO_CON + 0x8); 41 writel(XCL205_EN_GPIO_DRV_CFG, XCL205_EN_GPIO_CON + 0xc); 42 43 /* Set GPC1 pin 2 to IN - check XCL205 output state */ 44 writel(XCL205_STATE_GPIO_CON_CFG, XCL205_STATE_GPIO_CON); 45 writel(XCL205_STATE_GPIO_PUD_CFG, XCL205_STATE_GPIO_CON + 0x8); 46 47 /* XCL205 - needs some latch time */ 48 sdelay(200000); 49 50 /* Check GPC1 pin2 - LED supplied by XCL205 - X2 only */ 51 if (readl(XCL205_STATE_GPIO_DAT) & (1 << XCL205_STATE_GPIO_PIN)) 52 gd->board_type = ODROID_TYPE_X2; 53 else 54 gd->board_type = ODROID_TYPE_U3; 55 } 56 57 const char *get_board_type(void) 58 { 59 const char *board_type[] = {"u3", "x2"}; 60 61 return board_type[gd->board_type]; 62 } 63 #endif 64 65 #ifdef CONFIG_SET_DFU_ALT_INFO 66 char *get_dfu_alt_system(char *interface, char *devstr) 67 { 68 return env_get("dfu_alt_system"); 69 } 70 71 char *get_dfu_alt_boot(char *interface, char *devstr) 72 { 73 struct mmc *mmc; 74 char *alt_boot; 75 int dev_num; 76 77 dev_num = simple_strtoul(devstr, NULL, 10); 78 79 mmc = find_mmc_device(dev_num); 80 if (!mmc) 81 return NULL; 82 83 if (mmc_init(mmc)) 84 return NULL; 85 86 alt_boot = IS_SD(mmc) ? CONFIG_DFU_ALT_BOOT_SD : 87 CONFIG_DFU_ALT_BOOT_EMMC; 88 89 return alt_boot; 90 } 91 #endif 92 93 static void board_clock_init(void) 94 { 95 unsigned int set, clr, clr_src_cpu, clr_pll_con0, clr_src_dmc; 96 struct exynos4x12_clock *clk = (struct exynos4x12_clock *) 97 samsung_get_base_clock(); 98 99 /* 100 * CMU_CPU clocks src to MPLL 101 * Bit values: 0 ; 1 102 * MUX_APLL_SEL: FIN_PLL ; FOUT_APLL 103 * MUX_CORE_SEL: MOUT_APLL ; SCLK_MPLL 104 * MUX_HPM_SEL: MOUT_APLL ; SCLK_MPLL_USER_C 105 * MUX_MPLL_USER_SEL_C: FIN_PLL ; SCLK_MPLL 106 */ 107 clr_src_cpu = MUX_APLL_SEL(1) | MUX_CORE_SEL(1) | 108 MUX_HPM_SEL(1) | MUX_MPLL_USER_SEL_C(1); 109 set = MUX_APLL_SEL(0) | MUX_CORE_SEL(1) | MUX_HPM_SEL(1) | 110 MUX_MPLL_USER_SEL_C(1); 111 112 clrsetbits_le32(&clk->src_cpu, clr_src_cpu, set); 113 114 /* Wait for mux change */ 115 while (readl(&clk->mux_stat_cpu) & MUX_STAT_CPU_CHANGING) 116 continue; 117 118 /* Set APLL to 1000MHz */ 119 clr_pll_con0 = SDIV(7) | PDIV(63) | MDIV(1023) | FSEL(1); 120 set = SDIV(0) | PDIV(3) | MDIV(125) | FSEL(1); 121 122 clrsetbits_le32(&clk->apll_con0, clr_pll_con0, set); 123 124 /* Wait for PLL to be locked */ 125 while (!(readl(&clk->apll_con0) & PLL_LOCKED_BIT)) 126 continue; 127 128 /* Set CMU_CPU clocks src to APLL */ 129 set = MUX_APLL_SEL(1) | MUX_CORE_SEL(0) | MUX_HPM_SEL(0) | 130 MUX_MPLL_USER_SEL_C(1); 131 clrsetbits_le32(&clk->src_cpu, clr_src_cpu, set); 132 133 /* Wait for mux change */ 134 while (readl(&clk->mux_stat_cpu) & MUX_STAT_CPU_CHANGING) 135 continue; 136 137 set = CORE_RATIO(0) | COREM0_RATIO(2) | COREM1_RATIO(5) | 138 PERIPH_RATIO(0) | ATB_RATIO(4) | PCLK_DBG_RATIO(1) | 139 APLL_RATIO(0) | CORE2_RATIO(0); 140 /* 141 * Set dividers for MOUTcore = 1000 MHz 142 * coreout = MOUT / (ratio + 1) = 1000 MHz (0) 143 * corem0 = armclk / (ratio + 1) = 333 MHz (2) 144 * corem1 = armclk / (ratio + 1) = 166 MHz (5) 145 * periph = armclk / (ratio + 1) = 1000 MHz (0) 146 * atbout = MOUT / (ratio + 1) = 200 MHz (4) 147 * pclkdbgout = atbout / (ratio + 1) = 100 MHz (1) 148 * sclkapll = MOUTapll / (ratio + 1) = 1000 MHz (0) 149 * core2out = core_out / (ratio + 1) = 1000 MHz (0) (armclk) 150 */ 151 clr = CORE_RATIO(7) | COREM0_RATIO(7) | COREM1_RATIO(7) | 152 PERIPH_RATIO(7) | ATB_RATIO(7) | PCLK_DBG_RATIO(7) | 153 APLL_RATIO(7) | CORE2_RATIO(7); 154 155 clrsetbits_le32(&clk->div_cpu0, clr, set); 156 157 /* Wait for divider ready status */ 158 while (readl(&clk->div_stat_cpu0) & DIV_STAT_CPU0_CHANGING) 159 continue; 160 161 /* 162 * For MOUThpm = 1000 MHz (MOUTapll) 163 * doutcopy = MOUThpm / (ratio + 1) = 200 (4) 164 * sclkhpm = doutcopy / (ratio + 1) = 200 (4) 165 * cores_out = armclk / (ratio + 1) = 200 (4) 166 */ 167 clr = COPY_RATIO(7) | HPM_RATIO(7) | CORES_RATIO(7); 168 set = COPY_RATIO(4) | HPM_RATIO(4) | CORES_RATIO(4); 169 170 clrsetbits_le32(&clk->div_cpu1, clr, set); 171 172 /* Wait for divider ready status */ 173 while (readl(&clk->div_stat_cpu1) & DIV_STAT_CPU1_CHANGING) 174 continue; 175 176 /* 177 * Set CMU_DMC clocks src to APLL 178 * Bit values: 0 ; 1 179 * MUX_C2C_SEL: SCLKMPLL ; SCLKAPLL 180 * MUX_DMC_BUS_SEL: SCLKMPLL ; SCLKAPLL 181 * MUX_DPHY_SEL: SCLKMPLL ; SCLKAPLL 182 * MUX_MPLL_SEL: FINPLL ; MOUT_MPLL_FOUT 183 * MUX_PWI_SEL: 0110 (MPLL); 0111 (EPLL); 1000 (VPLL); 0(XXTI) 184 * MUX_G2D_ACP0_SEL: SCLKMPLL ; SCLKAPLL 185 * MUX_G2D_ACP1_SEL: SCLKEPLL ; SCLKVPLL 186 * MUX_G2D_ACP_SEL: OUT_ACP0 ; OUT_ACP1 187 */ 188 clr_src_dmc = MUX_C2C_SEL(1) | MUX_DMC_BUS_SEL(1) | 189 MUX_DPHY_SEL(1) | MUX_MPLL_SEL(1) | 190 MUX_PWI_SEL(15) | MUX_G2D_ACP0_SEL(1) | 191 MUX_G2D_ACP1_SEL(1) | MUX_G2D_ACP_SEL(1); 192 set = MUX_C2C_SEL(1) | MUX_DMC_BUS_SEL(1) | MUX_DPHY_SEL(1) | 193 MUX_MPLL_SEL(0) | MUX_PWI_SEL(0) | MUX_G2D_ACP0_SEL(1) | 194 MUX_G2D_ACP1_SEL(1) | MUX_G2D_ACP_SEL(1); 195 196 clrsetbits_le32(&clk->src_dmc, clr_src_dmc, set); 197 198 /* Wait for mux change */ 199 while (readl(&clk->mux_stat_dmc) & MUX_STAT_DMC_CHANGING) 200 continue; 201 202 /* Set MPLL to 800MHz */ 203 set = SDIV(0) | PDIV(3) | MDIV(100) | FSEL(0) | PLL_ENABLE(1); 204 205 clrsetbits_le32(&clk->mpll_con0, clr_pll_con0, set); 206 207 /* Wait for PLL to be locked */ 208 while (!(readl(&clk->mpll_con0) & PLL_LOCKED_BIT)) 209 continue; 210 211 /* Switch back CMU_DMC mux */ 212 set = MUX_C2C_SEL(0) | MUX_DMC_BUS_SEL(0) | MUX_DPHY_SEL(0) | 213 MUX_MPLL_SEL(1) | MUX_PWI_SEL(8) | MUX_G2D_ACP0_SEL(0) | 214 MUX_G2D_ACP1_SEL(0) | MUX_G2D_ACP_SEL(0); 215 216 clrsetbits_le32(&clk->src_dmc, clr_src_dmc, set); 217 218 /* Wait for mux change */ 219 while (readl(&clk->mux_stat_dmc) & MUX_STAT_DMC_CHANGING) 220 continue; 221 222 /* CLK_DIV_DMC0 */ 223 clr = ACP_RATIO(7) | ACP_PCLK_RATIO(7) | DPHY_RATIO(7) | 224 DMC_RATIO(7) | DMCD_RATIO(7) | DMCP_RATIO(7); 225 /* 226 * For: 227 * MOUTdmc = 800 MHz 228 * MOUTdphy = 800 MHz 229 * 230 * aclk_acp = MOUTdmc / (ratio + 1) = 200 (3) 231 * pclk_acp = aclk_acp / (ratio + 1) = 100 (1) 232 * sclk_dphy = MOUTdphy / (ratio + 1) = 400 (1) 233 * sclk_dmc = MOUTdmc / (ratio + 1) = 400 (1) 234 * aclk_dmcd = sclk_dmc / (ratio + 1) = 200 (1) 235 * aclk_dmcp = aclk_dmcd / (ratio + 1) = 100 (1) 236 */ 237 set = ACP_RATIO(3) | ACP_PCLK_RATIO(1) | DPHY_RATIO(1) | 238 DMC_RATIO(1) | DMCD_RATIO(1) | DMCP_RATIO(1); 239 240 clrsetbits_le32(&clk->div_dmc0, clr, set); 241 242 /* Wait for divider ready status */ 243 while (readl(&clk->div_stat_dmc0) & DIV_STAT_DMC0_CHANGING) 244 continue; 245 246 /* CLK_DIV_DMC1 */ 247 clr = G2D_ACP_RATIO(15) | C2C_RATIO(7) | PWI_RATIO(15) | 248 C2C_ACLK_RATIO(7) | DVSEM_RATIO(127) | DPM_RATIO(127); 249 /* 250 * For: 251 * MOUTg2d = 800 MHz 252 * MOUTc2c = 800 Mhz 253 * MOUTpwi = 108 MHz 254 * 255 * sclk_g2d_acp = MOUTg2d / (ratio + 1) = 200 (3) 256 * sclk_c2c = MOUTc2c / (ratio + 1) = 400 (1) 257 * aclk_c2c = sclk_c2c / (ratio + 1) = 200 (1) 258 * sclk_pwi = MOUTpwi / (ratio + 1) = 18 (5) 259 */ 260 set = G2D_ACP_RATIO(3) | C2C_RATIO(1) | PWI_RATIO(5) | 261 C2C_ACLK_RATIO(1) | DVSEM_RATIO(1) | DPM_RATIO(1); 262 263 clrsetbits_le32(&clk->div_dmc1, clr, set); 264 265 /* Wait for divider ready status */ 266 while (readl(&clk->div_stat_dmc1) & DIV_STAT_DMC1_CHANGING) 267 continue; 268 269 /* CLK_SRC_PERIL0 */ 270 clr = UART0_SEL(15) | UART1_SEL(15) | UART2_SEL(15) | 271 UART3_SEL(15) | UART4_SEL(15); 272 /* 273 * Set CLK_SRC_PERIL0 clocks src to MPLL 274 * src values: 0(XXTI); 1(XusbXTI); 2(SCLK_HDMI24M); 3(SCLK_USBPHY0); 275 * 5(SCLK_HDMIPHY); 6(SCLK_MPLL_USER_T); 7(SCLK_EPLL); 276 * 8(SCLK_VPLL) 277 * 278 * Set all to SCLK_MPLL_USER_T 279 */ 280 set = UART0_SEL(6) | UART1_SEL(6) | UART2_SEL(6) | UART3_SEL(6) | 281 UART4_SEL(6); 282 283 clrsetbits_le32(&clk->src_peril0, clr, set); 284 285 /* CLK_DIV_PERIL0 */ 286 clr = UART0_RATIO(15) | UART1_RATIO(15) | UART2_RATIO(15) | 287 UART3_RATIO(15) | UART4_RATIO(15); 288 /* 289 * For MOUTuart0-4: 800MHz 290 * 291 * SCLK_UARTx = MOUTuartX / (ratio + 1) = 100 (7) 292 */ 293 set = UART0_RATIO(7) | UART1_RATIO(7) | UART2_RATIO(7) | 294 UART3_RATIO(7) | UART4_RATIO(7); 295 296 clrsetbits_le32(&clk->div_peril0, clr, set); 297 298 while (readl(&clk->div_stat_peril0) & DIV_STAT_PERIL0_CHANGING) 299 continue; 300 301 /* CLK_DIV_FSYS1 */ 302 clr = MMC0_RATIO(15) | MMC0_PRE_RATIO(255) | MMC1_RATIO(15) | 303 MMC1_PRE_RATIO(255); 304 /* 305 * For MOUTmmc0-3 = 800 MHz (MPLL) 306 * 307 * DOUTmmc1 = MOUTmmc1 / (ratio + 1) = 100 (7) 308 * sclk_mmc1 = DOUTmmc1 / (ratio + 1) = 50 (1) 309 * DOUTmmc0 = MOUTmmc0 / (ratio + 1) = 100 (7) 310 * sclk_mmc0 = DOUTmmc0 / (ratio + 1) = 50 (1) 311 */ 312 set = MMC0_RATIO(7) | MMC0_PRE_RATIO(1) | MMC1_RATIO(7) | 313 MMC1_PRE_RATIO(1); 314 315 clrsetbits_le32(&clk->div_fsys1, clr, set); 316 317 /* Wait for divider ready status */ 318 while (readl(&clk->div_stat_fsys1) & DIV_STAT_FSYS1_CHANGING) 319 continue; 320 321 /* CLK_DIV_FSYS2 */ 322 clr = MMC2_RATIO(15) | MMC2_PRE_RATIO(255) | MMC3_RATIO(15) | 323 MMC3_PRE_RATIO(255); 324 /* 325 * For MOUTmmc0-3 = 800 MHz (MPLL) 326 * 327 * DOUTmmc3 = MOUTmmc3 / (ratio + 1) = 100 (7) 328 * sclk_mmc3 = DOUTmmc3 / (ratio + 1) = 50 (1) 329 * DOUTmmc2 = MOUTmmc2 / (ratio + 1) = 100 (7) 330 * sclk_mmc2 = DOUTmmc2 / (ratio + 1) = 50 (1) 331 */ 332 set = MMC2_RATIO(7) | MMC2_PRE_RATIO(1) | MMC3_RATIO(7) | 333 MMC3_PRE_RATIO(1); 334 335 clrsetbits_le32(&clk->div_fsys2, clr, set); 336 337 /* Wait for divider ready status */ 338 while (readl(&clk->div_stat_fsys2) & DIV_STAT_FSYS2_CHANGING) 339 continue; 340 341 /* CLK_DIV_FSYS3 */ 342 clr = MMC4_RATIO(15) | MMC4_PRE_RATIO(255); 343 /* 344 * For MOUTmmc4 = 800 MHz (MPLL) 345 * 346 * DOUTmmc4 = MOUTmmc4 / (ratio + 1) = 100 (7) 347 * sclk_mmc4 = DOUTmmc4 / (ratio + 1) = 100 (0) 348 */ 349 set = MMC4_RATIO(7) | MMC4_PRE_RATIO(0); 350 351 clrsetbits_le32(&clk->div_fsys3, clr, set); 352 353 /* Wait for divider ready status */ 354 while (readl(&clk->div_stat_fsys3) & DIV_STAT_FSYS3_CHANGING) 355 continue; 356 357 return; 358 } 359 360 static void board_gpio_init(void) 361 { 362 /* eMMC Reset Pin */ 363 gpio_request(EXYNOS4X12_GPIO_K12, "eMMC Reset"); 364 365 gpio_cfg_pin(EXYNOS4X12_GPIO_K12, S5P_GPIO_FUNC(0x1)); 366 gpio_set_pull(EXYNOS4X12_GPIO_K12, S5P_GPIO_PULL_NONE); 367 gpio_set_drv(EXYNOS4X12_GPIO_K12, S5P_GPIO_DRV_4X); 368 369 /* Enable FAN (Odroid U3) */ 370 gpio_request(EXYNOS4X12_GPIO_D00, "FAN Control"); 371 372 gpio_set_pull(EXYNOS4X12_GPIO_D00, S5P_GPIO_PULL_UP); 373 gpio_set_drv(EXYNOS4X12_GPIO_D00, S5P_GPIO_DRV_4X); 374 gpio_direction_output(EXYNOS4X12_GPIO_D00, 1); 375 376 /* OTG Vbus output (Odroid U3+) */ 377 gpio_request(EXYNOS4X12_GPIO_L20, "OTG Vbus"); 378 379 gpio_set_pull(EXYNOS4X12_GPIO_L20, S5P_GPIO_PULL_NONE); 380 gpio_set_drv(EXYNOS4X12_GPIO_L20, S5P_GPIO_DRV_4X); 381 gpio_direction_output(EXYNOS4X12_GPIO_L20, 0); 382 383 /* OTG INT (Odroid U3+) */ 384 gpio_request(EXYNOS4X12_GPIO_X31, "OTG INT"); 385 386 gpio_set_pull(EXYNOS4X12_GPIO_X31, S5P_GPIO_PULL_UP); 387 gpio_set_drv(EXYNOS4X12_GPIO_X31, S5P_GPIO_DRV_4X); 388 gpio_direction_input(EXYNOS4X12_GPIO_X31); 389 390 /* Blue LED (Odroid X2/U2/U3) */ 391 gpio_request(EXYNOS4X12_GPIO_C10, "Blue LED"); 392 393 gpio_direction_output(EXYNOS4X12_GPIO_C10, 0); 394 395 #ifdef CONFIG_CMD_USB 396 /* USB3503A Reference frequency */ 397 gpio_request(EXYNOS4X12_GPIO_X30, "USB3503A RefFreq"); 398 399 /* USB3503A Connect */ 400 gpio_request(EXYNOS4X12_GPIO_X34, "USB3503A Connect"); 401 402 /* USB3503A Reset */ 403 gpio_request(EXYNOS4X12_GPIO_X35, "USB3503A Reset"); 404 #endif 405 } 406 407 int exynos_early_init_f(void) 408 { 409 board_clock_init(); 410 411 return 0; 412 } 413 414 int exynos_init(void) 415 { 416 board_gpio_init(); 417 418 return 0; 419 } 420 421 int exynos_power_init(void) 422 { 423 const char *mmc_regulators[] = { 424 "VDDQ_EMMC_1.8V", 425 "VDDQ_EMMC_2.8V", 426 "TFLASH_2.8V", 427 NULL, 428 }; 429 430 if (regulator_list_autoset(mmc_regulators, NULL, true)) 431 pr_err("Unable to init all mmc regulators\n"); 432 433 return 0; 434 } 435 436 #ifdef CONFIG_USB_GADGET 437 static int s5pc210_phy_control(int on) 438 { 439 struct udevice *dev; 440 int ret; 441 442 ret = regulator_get_by_platname("VDD_UOTG_3.0V", &dev); 443 if (ret) { 444 pr_err("Regulator get error: %d\n", ret); 445 return ret; 446 } 447 448 if (on) 449 return regulator_set_mode(dev, OPMODE_ON); 450 else 451 return regulator_set_mode(dev, OPMODE_LPM); 452 } 453 454 struct dwc2_plat_otg_data s5pc210_otg_data = { 455 .phy_control = s5pc210_phy_control, 456 .regs_phy = EXYNOS4X12_USBPHY_BASE, 457 .regs_otg = EXYNOS4X12_USBOTG_BASE, 458 .usb_phy_ctrl = EXYNOS4X12_USBPHY_CONTROL, 459 .usb_flags = PHY0_SLEEP, 460 }; 461 #endif 462 463 #if defined(CONFIG_USB_GADGET) || defined(CONFIG_CMD_USB) 464 465 int board_usb_init(int index, enum usb_init_type init) 466 { 467 #ifdef CONFIG_CMD_USB 468 struct udevice *dev; 469 int ret; 470 471 /* Set Ref freq 0 => 24MHz, 1 => 26MHz*/ 472 /* Odroid Us have it at 24MHz, Odroid Xs at 26MHz */ 473 if (gd->board_type == ODROID_TYPE_U3) 474 gpio_direction_output(EXYNOS4X12_GPIO_X30, 0); 475 else 476 gpio_direction_output(EXYNOS4X12_GPIO_X30, 1); 477 478 /* Disconnect, Reset, Connect */ 479 gpio_direction_output(EXYNOS4X12_GPIO_X34, 0); 480 gpio_direction_output(EXYNOS4X12_GPIO_X35, 0); 481 gpio_direction_output(EXYNOS4X12_GPIO_X35, 1); 482 gpio_direction_output(EXYNOS4X12_GPIO_X34, 1); 483 484 /* Power off and on BUCK8 for LAN9730 */ 485 debug("LAN9730 - Turning power buck 8 OFF and ON.\n"); 486 487 ret = regulator_get_by_platname("VCC_P3V3_2.85V", &dev); 488 if (ret) { 489 pr_err("Regulator get error: %d\n", ret); 490 return ret; 491 } 492 493 ret = regulator_set_enable(dev, true); 494 if (ret) { 495 pr_err("Regulator %s enable setting error: %d\n", dev->name, ret); 496 return ret; 497 } 498 499 ret = regulator_set_value(dev, 750000); 500 if (ret) { 501 pr_err("Regulator %s value setting error: %d\n", dev->name, ret); 502 return ret; 503 } 504 505 ret = regulator_set_value(dev, 3300000); 506 if (ret) { 507 pr_err("Regulator %s value setting error: %d\n", dev->name, ret); 508 return ret; 509 } 510 #endif 511 debug("USB_udc_probe\n"); 512 return dwc2_udc_probe(&s5pc210_otg_data); 513 } 514 #endif 515