1/*
2 * Memory Setup stuff - taken from blob memsetup.S
3 *
4 * Copyright (C) 2009 Samsung Electronics
5 * Kyungmin Park <kyungmin.park@samsung.com>
6 *
7 * SPDX-License-Identifier:	GPL-2.0+
8 */
9
10#include <config.h>
11#include <version.h>
12#include <asm/arch/cpu.h>
13#include <asm/arch/clock.h>
14#include <asm/arch/power.h>
15
16/*
17 * Register usages:
18 *
19 * r5 has zero always
20 * r7 has S5PC100 GPIO base, 0xE0300000
21 * r8 has real GPIO base, 0xE0300000, 0xE0200000 at S5PC100, S5PC110 repectively
22 * r9 has Mobile DDR size, 1 means 1GiB, 2 means 2GiB and so on
23 */
24
25_TEXT_BASE:
26	.word	CONFIG_SYS_TEXT_BASE
27
28	.globl lowlevel_init
29lowlevel_init:
30	mov	r11, lr
31
32	/* r5 has always zero */
33	mov	r5, #0
34
35	ldr	r7, =S5PC100_GPIO_BASE
36	ldr	r8, =S5PC100_GPIO_BASE
37	/* Read CPU ID */
38	ldr	r2, =S5PC110_PRO_ID
39	ldr	r0, [r2]
40	mov	r1, #0x00010000
41	and	r0, r0, r1
42	cmp	r0, r5
43	beq	100f
44	ldr	r8, =S5PC110_GPIO_BASE
45100:
46	/* Turn on KEY_LED_ON [GPJ4(1)] XMSMWEN */
47	cmp	r7, r8
48	beq	skip_check_didle			@ Support C110 only
49
50	ldr	r0, =S5PC110_RST_STAT
51	ldr	r1, [r0]
52	and	r1, r1, #0x000D0000
53	cmp	r1, #(0x1 << 19)			@ DEEPIDLE_WAKEUP
54	beq	didle_wakeup
55	cmp	r7, r8
56
57skip_check_didle:
58	addeq	r0, r8, #0x280				@ S5PC100_GPIO_J4
59	addne	r0, r8, #0x2C0				@ S5PC110_GPIO_J4
60	ldr	r1, [r0, #0x0]				@ GPIO_CON_OFFSET
61	bic	r1, r1, #(0xf << 4)			@ 1 * 4-bit
62	orr	r1, r1, #(0x1 << 4)
63	str	r1, [r0, #0x0]				@ GPIO_CON_OFFSET
64
65	ldr	r1, [r0, #0x4]				@ GPIO_DAT_OFFSET
66	bic	r1, r1, #(1 << 1)
67	str	r1, [r0, #0x4]				@ GPIO_DAT_OFFSET
68
69	/* Don't setup at s5pc100 */
70	beq	100f
71
72	/*
73	 * Initialize Async Register Setting for EVT1
74	 * Because we are setting EVT1 as the default value of EVT0,
75	 * setting EVT0 as well does not make things worse.
76	 * Thus, for the simplicity, we set for EVT0, too
77	 *
78	 * The "Async Registers" are:
79	 *	0xE0F0_0000
80	 *	0xE1F0_0000
81	 *	0xF180_0000
82	 *	0xF190_0000
83	 *	0xF1A0_0000
84	 *	0xF1B0_0000
85	 *	0xF1C0_0000
86	 *	0xF1D0_0000
87	 *	0xF1E0_0000
88	 *	0xF1F0_0000
89	 *	0xFAF0_0000
90	 */
91	ldr     r0, =0xe0f00000
92	ldr     r1, [r0]
93	bic     r1, r1, #0x1
94	str     r1, [r0]
95
96	ldr     r0, =0xe1f00000
97	ldr     r1, [r0]
98	bic     r1, r1, #0x1
99	str     r1, [r0]
100
101	ldr     r0, =0xf1800000
102	ldr     r1, [r0]
103	bic     r1, r1, #0x1
104	str     r1, [r0]
105
106	ldr     r0, =0xf1900000
107	ldr     r1, [r0]
108	bic     r1, r1, #0x1
109	str     r1, [r0]
110
111	ldr     r0, =0xf1a00000
112	ldr     r1, [r0]
113	bic     r1, r1, #0x1
114	str     r1, [r0]
115
116	ldr     r0, =0xf1b00000
117	ldr     r1, [r0]
118	bic     r1, r1, #0x1
119	str     r1, [r0]
120
121	ldr     r0, =0xf1c00000
122	ldr     r1, [r0]
123	bic     r1, r1, #0x1
124	str     r1, [r0]
125
126	ldr     r0, =0xf1d00000
127	ldr     r1, [r0]
128	bic     r1, r1, #0x1
129	str     r1, [r0]
130
131	ldr     r0, =0xf1e00000
132	ldr     r1, [r0]
133	bic     r1, r1, #0x1
134	str     r1, [r0]
135
136	ldr     r0, =0xf1f00000
137	ldr     r1, [r0]
138	bic     r1, r1, #0x1
139	str     r1, [r0]
140
141	ldr     r0, =0xfaf00000
142	ldr     r1, [r0]
143	bic     r1, r1, #0x1
144	str     r1, [r0]
145
146	/*
147	 * Diable ABB block to reduce sleep current at low temperature
148	 * Note that it's hidden register setup don't modify it
149	 */
150	ldr	r0, =0xE010C300
151	ldr	r1, =0x00800000
152	str	r1, [r0]
153
154100:
155	/* IO retension release */
156	ldreq	r0, =S5PC100_OTHERS			@ 0xE0108200
157	ldrne	r0, =S5PC110_OTHERS			@ 0xE010E000
158	ldr	r1, [r0]
159	ldreq	r2, =(1 << 31)				@ IO_RET_REL
160	ldrne	r2, =((1 << 31) | (1 << 30) | (1 << 29) | (1 << 28))
161	orr	r1, r1, r2
162	/* Do not release retention here for S5PC110 */
163	streq	r1, [r0]
164
165	/* Disable Watchdog */
166	ldreq	r0, =S5PC100_WATCHDOG_BASE		@ 0xEA200000
167	ldrne	r0, =S5PC110_WATCHDOG_BASE		@ 0xE2700000
168	str	r5, [r0]
169
170	/* setting SRAM */
171	ldreq	r0, =S5PC100_SROMC_BASE
172	ldrne	r0, =S5PC110_SROMC_BASE
173	ldr	r1, =0x9
174	str	r1, [r0]
175
176	/* S5PC100 has 3 groups of interrupt sources */
177	ldreq	r0, =S5PC100_VIC0_BASE			@ 0xE4000000
178	ldrne	r0, =S5PC110_VIC0_BASE			@ 0xF2000000
179	add	r1, r0, #0x00100000
180	add	r2, r0, #0x00200000
181
182	/* Disable all interrupts (VIC0, VIC1 and VIC2) */
183	mvn	r3, #0x0
184	str	r3, [r0, #0x14]				@ INTENCLEAR
185	str	r3, [r1, #0x14]				@ INTENCLEAR
186	str	r3, [r2, #0x14]				@ INTENCLEAR
187
188	/* Set all interrupts as IRQ */
189	str	r5, [r0, #0xc]				@ INTSELECT
190	str	r5, [r1, #0xc]				@ INTSELECT
191	str	r5, [r2, #0xc]				@ INTSELECT
192
193	/* Pending Interrupt Clear */
194	str	r5, [r0, #0xf00]			@ INTADDRESS
195	str	r5, [r1, #0xf00]			@ INTADDRESS
196	str	r5, [r2, #0xf00]			@ INTADDRESS
197
198	/* for UART */
199	bl	uart_asm_init
200
201	bl	internal_ram_init
202
203	cmp	r7, r8
204	/* Clear wakeup status register */
205	ldreq	r0, =S5PC100_WAKEUP_STAT
206	ldrne	r0, =S5PC110_WAKEUP_STAT
207	ldr	r1, [r0]
208	str	r1, [r0]
209
210	/* IO retension release */
211	ldreq	r0, =S5PC100_OTHERS			@ 0xE0108200
212	ldrne	r0, =S5PC110_OTHERS			@ 0xE010E000
213	ldr	r1, [r0]
214	ldreq	r2, =(1 << 31)				@ IO_RET_REL
215	ldrne	r2, =((1 << 31) | (1 << 30) | (1 << 29) | (1 << 28))
216	orr	r1, r1, r2
217	str	r1, [r0]
218
219	b	1f
220
221didle_wakeup:
222	/* Wait when APLL is locked */
223	ldr	r0, =0xE0100100			@ S5PC110_APLL_CON
224lockloop:
225	ldr	r1, [r0]
226	and	r1, r1, #(1 << 29)
227	cmp	r1, #(1 << 29)
228	bne	lockloop
229
230	ldr	r0, =S5PC110_INFORM0
231	ldr	r1, [r0]
232	mov	pc, r1
233	nop
234	nop
235	nop
236	nop
237	nop
238
2391:
240	mov	lr, r11
241	mov	pc, lr
242
243/*
244 * system_clock_init: Initialize core clock and bus clock.
245 * void system_clock_init(void)
246 */
247system_clock_init:
248	ldr	r0, =S5PC110_CLOCK_BASE		@ 0xE0100000
249
250	/* Check S5PC100 */
251	cmp	r7, r8
252	bne	110f
253100:
254	/* Set Lock Time */
255	ldr	r1, =0xe10			@ Locktime : 0xe10 = 3600
256	str	r1, [r0, #0x000]		@ S5PC100_APLL_LOCK
257	str	r1, [r0, #0x004]		@ S5PC100_MPLL_LOCK
258	str	r1, [r0, #0x008]		@ S5PC100_EPLL_LOCK
259	str	r1, [r0, #0x00C]		@ S5PC100_HPLL_LOCK
260
261	/* S5P_APLL_CON */
262	ldr	r1, =0x81bc0400		@ SDIV 0, PDIV 4, MDIV 444 (1333MHz)
263	str	r1, [r0, #0x100]
264	/* S5P_MPLL_CON */
265	ldr	r1, =0x80590201		@ SDIV 1, PDIV 2, MDIV 89 (267MHz)
266	str	r1, [r0, #0x104]
267	/* S5P_EPLL_CON */
268	ldr	r1, =0x80870303		@ SDIV 3, PDIV 3, MDIV 135 (67.5MHz)
269	str	r1, [r0, #0x108]
270	/* S5P_HPLL_CON */
271	ldr	r1, =0x80600603		@ SDIV 3, PDIV 6, MDIV 96
272	str	r1, [r0, #0x10C]
273
274	ldr     r1, [r0, #0x300]
275	ldr     r2, =0x00003fff
276	bic     r1, r1, r2
277	ldr     r2, =0x00011301
278
279	orr	r1, r1, r2
280	str	r1, [r0, #0x300]
281	ldr     r1, [r0, #0x304]
282	ldr     r2, =0x00011110
283	orr     r1, r1, r2
284	str     r1, [r0, #0x304]
285	ldr     r1, =0x00000001
286	str     r1, [r0, #0x308]
287
288	/* Set Source Clock */
289	ldr	r1, =0x00001111			@ A, M, E, HPLL Muxing
290	str	r1, [r0, #0x200]		@ S5PC1XX_CLK_SRC0
291
292	b	200f
293110:
294	ldr	r0, =0xE010C000			@ S5PC110_PWR_CFG
295
296	/* Set OSC_FREQ value */
297	ldr	r1, =0xf
298	str	r1, [r0, #0x100]		@ S5PC110_OSC_FREQ
299
300	/* Set MTC_STABLE value */
301	ldr	r1, =0xffffffff
302	str	r1, [r0, #0x110]		@ S5PC110_MTC_STABLE
303
304	/* Set CLAMP_STABLE value */
305	ldr	r1, =0x3ff03ff
306	str	r1, [r0, #0x114]		@ S5PC110_CLAMP_STABLE
307
308	ldr	r0, =S5PC110_CLOCK_BASE		@ 0xE0100000
309
310	/* Set Clock divider */
311	ldr	r1, =0x14131330			@ 1:1:4:4, 1:4:5
312	str	r1, [r0, #0x300]
313	ldr	r1, =0x11110111			@ UART[3210]: MMC[3210]
314	str	r1, [r0, #0x310]
315
316	/* Set Lock Time */
317	ldr	r1, =0x2cf			@ Locktime : 30us
318	str	r1, [r0, #0x000]		@ S5PC110_APLL_LOCK
319	ldr	r1, =0xe10			@ Locktime : 0xe10 = 3600
320	str	r1, [r0, #0x008]		@ S5PC110_MPLL_LOCK
321	str	r1, [r0, #0x010]		@ S5PC110_EPLL_LOCK
322	str	r1, [r0, #0x020]		@ S5PC110_VPLL_LOCK
323
324	/* S5PC110_APLL_CON */
325	ldr	r1, =0x80C80601			@ 800MHz
326	str	r1, [r0, #0x100]
327	/* S5PC110_MPLL_CON */
328	ldr	r1, =0x829B0C01			@ 667MHz
329	str	r1, [r0, #0x108]
330	/* S5PC110_EPLL_CON */
331	ldr	r1, =0x80600602			@  96MHz VSEL 0 P 6 M 96 S 2
332	str	r1, [r0, #0x110]
333	/* S5PC110_VPLL_CON */
334	ldr	r1, =0x806C0603			@  54MHz
335	str	r1, [r0, #0x120]
336
337	/* Set Source Clock */
338	ldr	r1, =0x10001111			@ A, M, E, VPLL Muxing
339	str	r1, [r0, #0x200]		@ S5PC1XX_CLK_SRC0
340
341	/* OneDRAM(DMC0) clock setting */
342	ldr	r1, =0x01000000			@ ONEDRAM_SEL[25:24] 1 SCLKMPLL
343	str	r1, [r0, #0x218]		@ S5PC110_CLK_SRC6
344	ldr	r1, =0x30000000			@ ONEDRAM_RATIO[31:28] 3 + 1
345	str	r1, [r0, #0x318]		@ S5PC110_CLK_DIV6
346
347	/* XCLKOUT = XUSBXTI 24MHz */
348	add	r2, r0, #0xE000			@ S5PC110_OTHERS
349	ldr     r1, [r2]
350	orr	r1, r1, #(0x3 << 8)		@ CLKOUT[9:8] 3 XUSBXTI
351	str	r1, [r2]
352
353	/* CLK_IP0 */
354	ldr	r1, =0x8fefeeb			@ DMC[1:0] PDMA0[3] IMEM[5]
355	str	r1, [r0, #0x460]		@ S5PC110_CLK_IP0
356
357	/* CLK_IP1 */
358	ldr	r1, =0xe9fdf0f9			@ FIMD[0] USBOTG[16]
359						@ NANDXL[24]
360	str	r1, [r0, #0x464]		@ S5PC110_CLK_IP1
361
362	/* CLK_IP2 */
363	ldr	r1, =0xf75f7fc			@ CORESIGHT[8] MODEM[9]
364						@ HOSTIF[10] HSMMC0[16]
365						@ HSMMC2[18] VIC[27:24]
366	str	r1, [r0, #0x468]		@ S5PC110_CLK_IP2
367
368	/* CLK_IP3 */
369	ldr	r1, =0x8eff038c			@ I2C[8:6]
370						@ SYSTIMER[16] UART0[17]
371						@ UART1[18] UART2[19]
372						@ UART3[20] WDT[22]
373						@ PWM[23] GPIO[26] SYSCON[27]
374	str	r1, [r0, #0x46c]		@ S5PC110_CLK_IP3
375
376	/* CLK_IP4 */
377	ldr	r1, =0xfffffff1			@ CHIP_ID[0] TZPC[8:5]
378	str	r1, [r0, #0x470]		@ S5PC110_CLK_IP3
379
380200:
381	/* wait at least 200us to stablize all clock */
382	mov	r2, #0x10000
3831:	subs	r2, r2, #1
384	bne	1b
385
386	mov	pc, lr
387
388internal_ram_init:
389	ldreq	r0, =0xE3800000
390	ldrne	r0, =0xF1500000
391	ldr	r1, =0x0
392	str	r1, [r0]
393
394	mov	pc, lr
395
396/*
397 * uart_asm_init: Initialize UART's pins
398 */
399uart_asm_init:
400	/* set GPIO to enable UART0-UART4 */
401	mov	r0, r8
402	ldr	r1, =0x22222222
403	str	r1, [r0, #0x0]			@ S5PC100_GPIO_A0_OFFSET
404	ldr	r1, =0x00002222
405	str	r1, [r0, #0x20]			@ S5PC100_GPIO_A1_OFFSET
406
407	/* Check S5PC100 */
408	cmp	r7, r8
409	bne	110f
410
411	/* UART_SEL GPK0[5] at S5PC100 */
412	add	r0, r8, #0x2A0			@ S5PC100_GPIO_K0_OFFSET
413	ldr	r1, [r0, #0x0]			@ S5PC1XX_GPIO_CON_OFFSET
414	bic	r1, r1, #(0xf << 20)		@ 20 = 5 * 4-bit
415	orr	r1, r1, #(0x1 << 20)		@ Output
416	str	r1, [r0, #0x0]			@ S5PC1XX_GPIO_CON_OFFSET
417
418	ldr	r1, [r0, #0x8]			@ S5PC1XX_GPIO_PULL_OFFSET
419	bic	r1, r1, #(0x3 << 10)		@ 10 = 5 * 2-bit
420	orr	r1, r1, #(0x2 << 10)		@ Pull-up enabled
421	str	r1, [r0, #0x8]			@ S5PC1XX_GPIO_PULL_OFFSET
422
423	ldr	r1, [r0, #0x4]			@ S5PC1XX_GPIO_DAT_OFFSET
424	orr	r1, r1, #(1 << 5)		@ 5 = 5 * 1-bit
425	str	r1, [r0, #0x4]			@ S5PC1XX_GPIO_DAT_OFFSET
426
427	b	200f
428110:
429	/*
430	 * Note that the following address
431	 * 0xE020'0360 is reserved address at S5PC100
432	 */
433	/* UART_SEL MP0_5[7] at S5PC110 */
434	add	r0, r8, #0x360			@ S5PC110_GPIO_MP0_5_OFFSET
435	ldr	r1, [r0, #0x0]			@ S5PC1XX_GPIO_CON_OFFSET
436	bic	r1, r1, #(0xf << 28)		@ 28 = 7 * 4-bit
437	orr	r1, r1, #(0x1 << 28)		@ Output
438	str	r1, [r0, #0x0]			@ S5PC1XX_GPIO_CON_OFFSET
439
440	ldr	r1, [r0, #0x8]			@ S5PC1XX_GPIO_PULL_OFFSET
441	bic	r1, r1, #(0x3 << 14)		@ 14 = 7 * 2-bit
442	orr	r1, r1, #(0x2 << 14)		@ Pull-up enabled
443	str	r1, [r0, #0x8]			@ S5PC1XX_GPIO_PULL_OFFSET
444
445	ldr	r1, [r0, #0x4]			@ S5PC1XX_GPIO_DAT_OFFSET
446	orr	r1, r1, #(1 << 7)		@ 7 = 7 * 1-bit
447	str	r1, [r0, #0x4]			@ S5PC1XX_GPIO_DAT_OFFSET
448200:
449	mov	pc, lr
450