1/*
2 * Memory Setup stuff - taken from blob memsetup.S
3 *
4 * Copyright (C) 2009 Samsung Electronics
5 * Kyungmin Park <kyungmin.park@samsung.com>
6 *
7 * SPDX-License-Identifier:	GPL-2.0+
8 */
9
10#include <config.h>
11#include <version.h>
12#include <asm/arch/cpu.h>
13#include <asm/arch/clock.h>
14#include <asm/arch/power.h>
15
16/*
17 * Register usages:
18 *
19 * r5 has zero always
20 * r7 has S5PC100 GPIO base, 0xE0300000
21 * r8 has real GPIO base, 0xE0300000, 0xE0200000 at S5PC100, S5PC110 repectively
22 * r9 has Mobile DDR size, 1 means 1GiB, 2 means 2GiB and so on
23 */
24
25	.globl lowlevel_init
26lowlevel_init:
27	mov	r11, lr
28
29	/* r5 has always zero */
30	mov	r5, #0
31
32	ldr	r7, =S5PC100_GPIO_BASE
33	ldr	r8, =S5PC100_GPIO_BASE
34	/* Read CPU ID */
35	ldr	r2, =S5PC110_PRO_ID
36	ldr	r0, [r2]
37	mov	r1, #0x00010000
38	and	r0, r0, r1
39	cmp	r0, r5
40	beq	100f
41	ldr	r8, =S5PC110_GPIO_BASE
42100:
43	/* Turn on KEY_LED_ON [GPJ4(1)] XMSMWEN */
44	cmp	r7, r8
45	beq	skip_check_didle			@ Support C110 only
46
47	ldr	r0, =S5PC110_RST_STAT
48	ldr	r1, [r0]
49	and	r1, r1, #0x000D0000
50	cmp	r1, #(0x1 << 19)			@ DEEPIDLE_WAKEUP
51	beq	didle_wakeup
52	cmp	r7, r8
53
54skip_check_didle:
55	addeq	r0, r8, #0x280				@ S5PC100_GPIO_J4
56	addne	r0, r8, #0x2C0				@ S5PC110_GPIO_J4
57	ldr	r1, [r0, #0x0]				@ GPIO_CON_OFFSET
58	bic	r1, r1, #(0xf << 4)			@ 1 * 4-bit
59	orr	r1, r1, #(0x1 << 4)
60	str	r1, [r0, #0x0]				@ GPIO_CON_OFFSET
61
62	ldr	r1, [r0, #0x4]				@ GPIO_DAT_OFFSET
63	bic	r1, r1, #(1 << 1)
64	str	r1, [r0, #0x4]				@ GPIO_DAT_OFFSET
65
66	/* Don't setup at s5pc100 */
67	beq	100f
68
69	/*
70	 * Initialize Async Register Setting for EVT1
71	 * Because we are setting EVT1 as the default value of EVT0,
72	 * setting EVT0 as well does not make things worse.
73	 * Thus, for the simplicity, we set for EVT0, too
74	 *
75	 * The "Async Registers" are:
76	 *	0xE0F0_0000
77	 *	0xE1F0_0000
78	 *	0xF180_0000
79	 *	0xF190_0000
80	 *	0xF1A0_0000
81	 *	0xF1B0_0000
82	 *	0xF1C0_0000
83	 *	0xF1D0_0000
84	 *	0xF1E0_0000
85	 *	0xF1F0_0000
86	 *	0xFAF0_0000
87	 */
88	ldr     r0, =0xe0f00000
89	ldr     r1, [r0]
90	bic     r1, r1, #0x1
91	str     r1, [r0]
92
93	ldr     r0, =0xe1f00000
94	ldr     r1, [r0]
95	bic     r1, r1, #0x1
96	str     r1, [r0]
97
98	ldr     r0, =0xf1800000
99	ldr     r1, [r0]
100	bic     r1, r1, #0x1
101	str     r1, [r0]
102
103	ldr     r0, =0xf1900000
104	ldr     r1, [r0]
105	bic     r1, r1, #0x1
106	str     r1, [r0]
107
108	ldr     r0, =0xf1a00000
109	ldr     r1, [r0]
110	bic     r1, r1, #0x1
111	str     r1, [r0]
112
113	ldr     r0, =0xf1b00000
114	ldr     r1, [r0]
115	bic     r1, r1, #0x1
116	str     r1, [r0]
117
118	ldr     r0, =0xf1c00000
119	ldr     r1, [r0]
120	bic     r1, r1, #0x1
121	str     r1, [r0]
122
123	ldr     r0, =0xf1d00000
124	ldr     r1, [r0]
125	bic     r1, r1, #0x1
126	str     r1, [r0]
127
128	ldr     r0, =0xf1e00000
129	ldr     r1, [r0]
130	bic     r1, r1, #0x1
131	str     r1, [r0]
132
133	ldr     r0, =0xf1f00000
134	ldr     r1, [r0]
135	bic     r1, r1, #0x1
136	str     r1, [r0]
137
138	ldr     r0, =0xfaf00000
139	ldr     r1, [r0]
140	bic     r1, r1, #0x1
141	str     r1, [r0]
142
143	/*
144	 * Diable ABB block to reduce sleep current at low temperature
145	 * Note that it's hidden register setup don't modify it
146	 */
147	ldr	r0, =0xE010C300
148	ldr	r1, =0x00800000
149	str	r1, [r0]
150
151100:
152	/* IO retension release */
153	ldreq	r0, =S5PC100_OTHERS			@ 0xE0108200
154	ldrne	r0, =S5PC110_OTHERS			@ 0xE010E000
155	ldr	r1, [r0]
156	ldreq	r2, =(1 << 31)				@ IO_RET_REL
157	ldrne	r2, =((1 << 31) | (1 << 30) | (1 << 29) | (1 << 28))
158	orr	r1, r1, r2
159	/* Do not release retention here for S5PC110 */
160	streq	r1, [r0]
161
162	/* Disable Watchdog */
163	ldreq	r0, =S5PC100_WATCHDOG_BASE		@ 0xEA200000
164	ldrne	r0, =S5PC110_WATCHDOG_BASE		@ 0xE2700000
165	str	r5, [r0]
166
167	/* setting SRAM */
168	ldreq	r0, =S5PC100_SROMC_BASE
169	ldrne	r0, =S5PC110_SROMC_BASE
170	ldr	r1, =0x9
171	str	r1, [r0]
172
173	/* S5PC100 has 3 groups of interrupt sources */
174	ldreq	r0, =S5PC100_VIC0_BASE			@ 0xE4000000
175	ldrne	r0, =S5PC110_VIC0_BASE			@ 0xF2000000
176	add	r1, r0, #0x00100000
177	add	r2, r0, #0x00200000
178
179	/* Disable all interrupts (VIC0, VIC1 and VIC2) */
180	mvn	r3, #0x0
181	str	r3, [r0, #0x14]				@ INTENCLEAR
182	str	r3, [r1, #0x14]				@ INTENCLEAR
183	str	r3, [r2, #0x14]				@ INTENCLEAR
184
185	/* Set all interrupts as IRQ */
186	str	r5, [r0, #0xc]				@ INTSELECT
187	str	r5, [r1, #0xc]				@ INTSELECT
188	str	r5, [r2, #0xc]				@ INTSELECT
189
190	/* Pending Interrupt Clear */
191	str	r5, [r0, #0xf00]			@ INTADDRESS
192	str	r5, [r1, #0xf00]			@ INTADDRESS
193	str	r5, [r2, #0xf00]			@ INTADDRESS
194
195	/* for UART */
196	bl	uart_asm_init
197
198	bl	internal_ram_init
199
200	cmp	r7, r8
201	/* Clear wakeup status register */
202	ldreq	r0, =S5PC100_WAKEUP_STAT
203	ldrne	r0, =S5PC110_WAKEUP_STAT
204	ldr	r1, [r0]
205	str	r1, [r0]
206
207	/* IO retension release */
208	ldreq	r0, =S5PC100_OTHERS			@ 0xE0108200
209	ldrne	r0, =S5PC110_OTHERS			@ 0xE010E000
210	ldr	r1, [r0]
211	ldreq	r2, =(1 << 31)				@ IO_RET_REL
212	ldrne	r2, =((1 << 31) | (1 << 30) | (1 << 29) | (1 << 28))
213	orr	r1, r1, r2
214	str	r1, [r0]
215
216	b	1f
217
218didle_wakeup:
219	/* Wait when APLL is locked */
220	ldr	r0, =0xE0100100			@ S5PC110_APLL_CON
221lockloop:
222	ldr	r1, [r0]
223	and	r1, r1, #(1 << 29)
224	cmp	r1, #(1 << 29)
225	bne	lockloop
226
227	ldr	r0, =S5PC110_INFORM0
228	ldr	r1, [r0]
229	mov	pc, r1
230	nop
231	nop
232	nop
233	nop
234	nop
235
2361:
237	mov	lr, r11
238	mov	pc, lr
239
240/*
241 * system_clock_init: Initialize core clock and bus clock.
242 * void system_clock_init(void)
243 */
244system_clock_init:
245	ldr	r0, =S5PC110_CLOCK_BASE		@ 0xE0100000
246
247	/* Check S5PC100 */
248	cmp	r7, r8
249	bne	110f
250100:
251	/* Set Lock Time */
252	ldr	r1, =0xe10			@ Locktime : 0xe10 = 3600
253	str	r1, [r0, #0x000]		@ S5PC100_APLL_LOCK
254	str	r1, [r0, #0x004]		@ S5PC100_MPLL_LOCK
255	str	r1, [r0, #0x008]		@ S5PC100_EPLL_LOCK
256	str	r1, [r0, #0x00C]		@ S5PC100_HPLL_LOCK
257
258	/* S5P_APLL_CON */
259	ldr	r1, =0x81bc0400		@ SDIV 0, PDIV 4, MDIV 444 (1333MHz)
260	str	r1, [r0, #0x100]
261	/* S5P_MPLL_CON */
262	ldr	r1, =0x80590201		@ SDIV 1, PDIV 2, MDIV 89 (267MHz)
263	str	r1, [r0, #0x104]
264	/* S5P_EPLL_CON */
265	ldr	r1, =0x80870303		@ SDIV 3, PDIV 3, MDIV 135 (67.5MHz)
266	str	r1, [r0, #0x108]
267	/* S5P_HPLL_CON */
268	ldr	r1, =0x80600603		@ SDIV 3, PDIV 6, MDIV 96
269	str	r1, [r0, #0x10C]
270
271	ldr     r1, [r0, #0x300]
272	ldr     r2, =0x00003fff
273	bic     r1, r1, r2
274	ldr     r2, =0x00011301
275
276	orr	r1, r1, r2
277	str	r1, [r0, #0x300]
278	ldr     r1, [r0, #0x304]
279	ldr     r2, =0x00011110
280	orr     r1, r1, r2
281	str     r1, [r0, #0x304]
282	ldr     r1, =0x00000001
283	str     r1, [r0, #0x308]
284
285	/* Set Source Clock */
286	ldr	r1, =0x00001111			@ A, M, E, HPLL Muxing
287	str	r1, [r0, #0x200]		@ S5PC1XX_CLK_SRC0
288
289	b	200f
290110:
291	ldr	r0, =0xE010C000			@ S5PC110_PWR_CFG
292
293	/* Set OSC_FREQ value */
294	ldr	r1, =0xf
295	str	r1, [r0, #0x100]		@ S5PC110_OSC_FREQ
296
297	/* Set MTC_STABLE value */
298	ldr	r1, =0xffffffff
299	str	r1, [r0, #0x110]		@ S5PC110_MTC_STABLE
300
301	/* Set CLAMP_STABLE value */
302	ldr	r1, =0x3ff03ff
303	str	r1, [r0, #0x114]		@ S5PC110_CLAMP_STABLE
304
305	ldr	r0, =S5PC110_CLOCK_BASE		@ 0xE0100000
306
307	/* Set Clock divider */
308	ldr	r1, =0x14131330			@ 1:1:4:4, 1:4:5
309	str	r1, [r0, #0x300]
310	ldr	r1, =0x11110111			@ UART[3210]: MMC[3210]
311	str	r1, [r0, #0x310]
312
313	/* Set Lock Time */
314	ldr	r1, =0x2cf			@ Locktime : 30us
315	str	r1, [r0, #0x000]		@ S5PC110_APLL_LOCK
316	ldr	r1, =0xe10			@ Locktime : 0xe10 = 3600
317	str	r1, [r0, #0x008]		@ S5PC110_MPLL_LOCK
318	str	r1, [r0, #0x010]		@ S5PC110_EPLL_LOCK
319	str	r1, [r0, #0x020]		@ S5PC110_VPLL_LOCK
320
321	/* S5PC110_APLL_CON */
322	ldr	r1, =0x80C80601			@ 800MHz
323	str	r1, [r0, #0x100]
324	/* S5PC110_MPLL_CON */
325	ldr	r1, =0x829B0C01			@ 667MHz
326	str	r1, [r0, #0x108]
327	/* S5PC110_EPLL_CON */
328	ldr	r1, =0x80600602			@  96MHz VSEL 0 P 6 M 96 S 2
329	str	r1, [r0, #0x110]
330	/* S5PC110_VPLL_CON */
331	ldr	r1, =0x806C0603			@  54MHz
332	str	r1, [r0, #0x120]
333
334	/* Set Source Clock */
335	ldr	r1, =0x10001111			@ A, M, E, VPLL Muxing
336	str	r1, [r0, #0x200]		@ S5PC1XX_CLK_SRC0
337
338	/* OneDRAM(DMC0) clock setting */
339	ldr	r1, =0x01000000			@ ONEDRAM_SEL[25:24] 1 SCLKMPLL
340	str	r1, [r0, #0x218]		@ S5PC110_CLK_SRC6
341	ldr	r1, =0x30000000			@ ONEDRAM_RATIO[31:28] 3 + 1
342	str	r1, [r0, #0x318]		@ S5PC110_CLK_DIV6
343
344	/* XCLKOUT = XUSBXTI 24MHz */
345	add	r2, r0, #0xE000			@ S5PC110_OTHERS
346	ldr     r1, [r2]
347	orr	r1, r1, #(0x3 << 8)		@ CLKOUT[9:8] 3 XUSBXTI
348	str	r1, [r2]
349
350	/* CLK_IP0 */
351	ldr	r1, =0x8fefeeb			@ DMC[1:0] PDMA0[3] IMEM[5]
352	str	r1, [r0, #0x460]		@ S5PC110_CLK_IP0
353
354	/* CLK_IP1 */
355	ldr	r1, =0xe9fdf0f9			@ FIMD[0] USBOTG[16]
356						@ NANDXL[24]
357	str	r1, [r0, #0x464]		@ S5PC110_CLK_IP1
358
359	/* CLK_IP2 */
360	ldr	r1, =0xf75f7fc			@ CORESIGHT[8] MODEM[9]
361						@ HOSTIF[10] HSMMC0[16]
362						@ HSMMC2[18] VIC[27:24]
363	str	r1, [r0, #0x468]		@ S5PC110_CLK_IP2
364
365	/* CLK_IP3 */
366	ldr	r1, =0x8eff038c			@ I2C[8:6]
367						@ SYSTIMER[16] UART0[17]
368						@ UART1[18] UART2[19]
369						@ UART3[20] WDT[22]
370						@ PWM[23] GPIO[26] SYSCON[27]
371	str	r1, [r0, #0x46c]		@ S5PC110_CLK_IP3
372
373	/* CLK_IP4 */
374	ldr	r1, =0xfffffff1			@ CHIP_ID[0] TZPC[8:5]
375	str	r1, [r0, #0x470]		@ S5PC110_CLK_IP3
376
377200:
378	/* wait at least 200us to stablize all clock */
379	mov	r2, #0x10000
3801:	subs	r2, r2, #1
381	bne	1b
382
383	mov	pc, lr
384
385internal_ram_init:
386	ldreq	r0, =0xE3800000
387	ldrne	r0, =0xF1500000
388	ldr	r1, =0x0
389	str	r1, [r0]
390
391	mov	pc, lr
392
393/*
394 * uart_asm_init: Initialize UART's pins
395 */
396uart_asm_init:
397	/* set GPIO to enable UART0-UART4 */
398	mov	r0, r8
399	ldr	r1, =0x22222222
400	str	r1, [r0, #0x0]			@ S5PC100_GPIO_A0_OFFSET
401	ldr	r1, =0x00002222
402	str	r1, [r0, #0x20]			@ S5PC100_GPIO_A1_OFFSET
403
404	/* Check S5PC100 */
405	cmp	r7, r8
406	bne	110f
407
408	/* UART_SEL GPK0[5] at S5PC100 */
409	add	r0, r8, #0x2A0			@ S5PC100_GPIO_K0_OFFSET
410	ldr	r1, [r0, #0x0]			@ S5PC1XX_GPIO_CON_OFFSET
411	bic	r1, r1, #(0xf << 20)		@ 20 = 5 * 4-bit
412	orr	r1, r1, #(0x1 << 20)		@ Output
413	str	r1, [r0, #0x0]			@ S5PC1XX_GPIO_CON_OFFSET
414
415	ldr	r1, [r0, #0x8]			@ S5PC1XX_GPIO_PULL_OFFSET
416	bic	r1, r1, #(0x3 << 10)		@ 10 = 5 * 2-bit
417	orr	r1, r1, #(0x2 << 10)		@ Pull-up enabled
418	str	r1, [r0, #0x8]			@ S5PC1XX_GPIO_PULL_OFFSET
419
420	ldr	r1, [r0, #0x4]			@ S5PC1XX_GPIO_DAT_OFFSET
421	orr	r1, r1, #(1 << 5)		@ 5 = 5 * 1-bit
422	str	r1, [r0, #0x4]			@ S5PC1XX_GPIO_DAT_OFFSET
423
424	b	200f
425110:
426	/*
427	 * Note that the following address
428	 * 0xE020'0360 is reserved address at S5PC100
429	 */
430	/* UART_SEL MP0_5[7] at S5PC110 */
431	add	r0, r8, #0x360			@ S5PC110_GPIO_MP0_5_OFFSET
432	ldr	r1, [r0, #0x0]			@ S5PC1XX_GPIO_CON_OFFSET
433	bic	r1, r1, #(0xf << 28)		@ 28 = 7 * 4-bit
434	orr	r1, r1, #(0x1 << 28)		@ Output
435	str	r1, [r0, #0x0]			@ S5PC1XX_GPIO_CON_OFFSET
436
437	ldr	r1, [r0, #0x8]			@ S5PC1XX_GPIO_PULL_OFFSET
438	bic	r1, r1, #(0x3 << 14)		@ 14 = 7 * 2-bit
439	orr	r1, r1, #(0x2 << 14)		@ Pull-up enabled
440	str	r1, [r0, #0x8]			@ S5PC1XX_GPIO_PULL_OFFSET
441
442	ldr	r1, [r0, #0x4]			@ S5PC1XX_GPIO_DAT_OFFSET
443	orr	r1, r1, #(1 << 7)		@ 7 = 7 * 1-bit
444	str	r1, [r0, #0x4]			@ S5PC1XX_GPIO_DAT_OFFSET
445200:
446	mov	pc, lr
447