1/*
2 * Memory Setup stuff - taken from blob memsetup.S
3 *
4 * Copyright (C) 2009 Samsung Electronics
5 * Kyungmin Park <kyungmin.park@samsung.com>
6 *
7 * SPDX-License-Identifier:	GPL-2.0+
8 */
9
10#include <config.h>
11#include <asm/arch/cpu.h>
12#include <asm/arch/clock.h>
13#include <asm/arch/power.h>
14
15/*
16 * Register usages:
17 *
18 * r5 has zero always
19 * r7 has S5PC100 GPIO base, 0xE0300000
20 * r8 has real GPIO base, 0xE0300000, 0xE0200000 at S5PC100, S5PC110 repectively
21 * r9 has Mobile DDR size, 1 means 1GiB, 2 means 2GiB and so on
22 */
23
24	.globl lowlevel_init
25lowlevel_init:
26	mov	r11, lr
27
28	/* r5 has always zero */
29	mov	r5, #0
30
31	ldr	r7, =S5PC100_GPIO_BASE
32	ldr	r8, =S5PC100_GPIO_BASE
33	/* Read CPU ID */
34	ldr	r2, =S5PC110_PRO_ID
35	ldr	r0, [r2]
36	mov	r1, #0x00010000
37	and	r0, r0, r1
38	cmp	r0, r5
39	beq	100f
40	ldr	r8, =S5PC110_GPIO_BASE
41100:
42	/* Turn on KEY_LED_ON [GPJ4(1)] XMSMWEN */
43	cmp	r7, r8
44	beq	skip_check_didle			@ Support C110 only
45
46	ldr	r0, =S5PC110_RST_STAT
47	ldr	r1, [r0]
48	and	r1, r1, #0x000D0000
49	cmp	r1, #(0x1 << 19)			@ DEEPIDLE_WAKEUP
50	beq	didle_wakeup
51	cmp	r7, r8
52
53skip_check_didle:
54	addeq	r0, r8, #0x280				@ S5PC100_GPIO_J4
55	addne	r0, r8, #0x2C0				@ S5PC110_GPIO_J4
56	ldr	r1, [r0, #0x0]				@ GPIO_CON_OFFSET
57	bic	r1, r1, #(0xf << 4)			@ 1 * 4-bit
58	orr	r1, r1, #(0x1 << 4)
59	str	r1, [r0, #0x0]				@ GPIO_CON_OFFSET
60
61	ldr	r1, [r0, #0x4]				@ GPIO_DAT_OFFSET
62	bic	r1, r1, #(1 << 1)
63	str	r1, [r0, #0x4]				@ GPIO_DAT_OFFSET
64
65	/* Don't setup at s5pc100 */
66	beq	100f
67
68	/*
69	 * Initialize Async Register Setting for EVT1
70	 * Because we are setting EVT1 as the default value of EVT0,
71	 * setting EVT0 as well does not make things worse.
72	 * Thus, for the simplicity, we set for EVT0, too
73	 *
74	 * The "Async Registers" are:
75	 *	0xE0F0_0000
76	 *	0xE1F0_0000
77	 *	0xF180_0000
78	 *	0xF190_0000
79	 *	0xF1A0_0000
80	 *	0xF1B0_0000
81	 *	0xF1C0_0000
82	 *	0xF1D0_0000
83	 *	0xF1E0_0000
84	 *	0xF1F0_0000
85	 *	0xFAF0_0000
86	 */
87	ldr     r0, =0xe0f00000
88	ldr     r1, [r0]
89	bic     r1, r1, #0x1
90	str     r1, [r0]
91
92	ldr     r0, =0xe1f00000
93	ldr     r1, [r0]
94	bic     r1, r1, #0x1
95	str     r1, [r0]
96
97	ldr     r0, =0xf1800000
98	ldr     r1, [r0]
99	bic     r1, r1, #0x1
100	str     r1, [r0]
101
102	ldr     r0, =0xf1900000
103	ldr     r1, [r0]
104	bic     r1, r1, #0x1
105	str     r1, [r0]
106
107	ldr     r0, =0xf1a00000
108	ldr     r1, [r0]
109	bic     r1, r1, #0x1
110	str     r1, [r0]
111
112	ldr     r0, =0xf1b00000
113	ldr     r1, [r0]
114	bic     r1, r1, #0x1
115	str     r1, [r0]
116
117	ldr     r0, =0xf1c00000
118	ldr     r1, [r0]
119	bic     r1, r1, #0x1
120	str     r1, [r0]
121
122	ldr     r0, =0xf1d00000
123	ldr     r1, [r0]
124	bic     r1, r1, #0x1
125	str     r1, [r0]
126
127	ldr     r0, =0xf1e00000
128	ldr     r1, [r0]
129	bic     r1, r1, #0x1
130	str     r1, [r0]
131
132	ldr     r0, =0xf1f00000
133	ldr     r1, [r0]
134	bic     r1, r1, #0x1
135	str     r1, [r0]
136
137	ldr     r0, =0xfaf00000
138	ldr     r1, [r0]
139	bic     r1, r1, #0x1
140	str     r1, [r0]
141
142	/*
143	 * Diable ABB block to reduce sleep current at low temperature
144	 * Note that it's hidden register setup don't modify it
145	 */
146	ldr	r0, =0xE010C300
147	ldr	r1, =0x00800000
148	str	r1, [r0]
149
150100:
151	/* IO retension release */
152	ldreq	r0, =S5PC100_OTHERS			@ 0xE0108200
153	ldrne	r0, =S5PC110_OTHERS			@ 0xE010E000
154	ldr	r1, [r0]
155	ldreq	r2, =(1 << 31)				@ IO_RET_REL
156	ldrne	r2, =((1 << 31) | (1 << 30) | (1 << 29) | (1 << 28))
157	orr	r1, r1, r2
158	/* Do not release retention here for S5PC110 */
159	streq	r1, [r0]
160
161	/* Disable Watchdog */
162	ldreq	r0, =S5PC100_WATCHDOG_BASE		@ 0xEA200000
163	ldrne	r0, =S5PC110_WATCHDOG_BASE		@ 0xE2700000
164	str	r5, [r0]
165
166	/* setting SRAM */
167	ldreq	r0, =S5PC100_SROMC_BASE
168	ldrne	r0, =S5PC110_SROMC_BASE
169	ldr	r1, =0x9
170	str	r1, [r0]
171
172	/* S5PC100 has 3 groups of interrupt sources */
173	ldreq	r0, =S5PC100_VIC0_BASE			@ 0xE4000000
174	ldrne	r0, =S5PC110_VIC0_BASE			@ 0xF2000000
175	add	r1, r0, #0x00100000
176	add	r2, r0, #0x00200000
177
178	/* Disable all interrupts (VIC0, VIC1 and VIC2) */
179	mvn	r3, #0x0
180	str	r3, [r0, #0x14]				@ INTENCLEAR
181	str	r3, [r1, #0x14]				@ INTENCLEAR
182	str	r3, [r2, #0x14]				@ INTENCLEAR
183
184	/* Set all interrupts as IRQ */
185	str	r5, [r0, #0xc]				@ INTSELECT
186	str	r5, [r1, #0xc]				@ INTSELECT
187	str	r5, [r2, #0xc]				@ INTSELECT
188
189	/* Pending Interrupt Clear */
190	str	r5, [r0, #0xf00]			@ INTADDRESS
191	str	r5, [r1, #0xf00]			@ INTADDRESS
192	str	r5, [r2, #0xf00]			@ INTADDRESS
193
194	/* for UART */
195	bl	uart_asm_init
196
197	bl	internal_ram_init
198
199	cmp	r7, r8
200	/* Clear wakeup status register */
201	ldreq	r0, =S5PC100_WAKEUP_STAT
202	ldrne	r0, =S5PC110_WAKEUP_STAT
203	ldr	r1, [r0]
204	str	r1, [r0]
205
206	/* IO retension release */
207	ldreq	r0, =S5PC100_OTHERS			@ 0xE0108200
208	ldrne	r0, =S5PC110_OTHERS			@ 0xE010E000
209	ldr	r1, [r0]
210	ldreq	r2, =(1 << 31)				@ IO_RET_REL
211	ldrne	r2, =((1 << 31) | (1 << 30) | (1 << 29) | (1 << 28))
212	orr	r1, r1, r2
213	str	r1, [r0]
214
215	b	1f
216
217didle_wakeup:
218	/* Wait when APLL is locked */
219	ldr	r0, =0xE0100100			@ S5PC110_APLL_CON
220lockloop:
221	ldr	r1, [r0]
222	and	r1, r1, #(1 << 29)
223	cmp	r1, #(1 << 29)
224	bne	lockloop
225
226	ldr	r0, =S5PC110_INFORM0
227	ldr	r1, [r0]
228	mov	pc, r1
229	nop
230	nop
231	nop
232	nop
233	nop
234
2351:
236	mov	lr, r11
237	mov	pc, lr
238
239/*
240 * system_clock_init: Initialize core clock and bus clock.
241 * void system_clock_init(void)
242 */
243system_clock_init:
244	ldr	r0, =S5PC110_CLOCK_BASE		@ 0xE0100000
245
246	/* Check S5PC100 */
247	cmp	r7, r8
248	bne	110f
249100:
250	/* Set Lock Time */
251	ldr	r1, =0xe10			@ Locktime : 0xe10 = 3600
252	str	r1, [r0, #0x000]		@ S5PC100_APLL_LOCK
253	str	r1, [r0, #0x004]		@ S5PC100_MPLL_LOCK
254	str	r1, [r0, #0x008]		@ S5PC100_EPLL_LOCK
255	str	r1, [r0, #0x00C]		@ S5PC100_HPLL_LOCK
256
257	/* S5P_APLL_CON */
258	ldr	r1, =0x81bc0400		@ SDIV 0, PDIV 4, MDIV 444 (1333MHz)
259	str	r1, [r0, #0x100]
260	/* S5P_MPLL_CON */
261	ldr	r1, =0x80590201		@ SDIV 1, PDIV 2, MDIV 89 (267MHz)
262	str	r1, [r0, #0x104]
263	/* S5P_EPLL_CON */
264	ldr	r1, =0x80870303		@ SDIV 3, PDIV 3, MDIV 135 (67.5MHz)
265	str	r1, [r0, #0x108]
266	/* S5P_HPLL_CON */
267	ldr	r1, =0x80600603		@ SDIV 3, PDIV 6, MDIV 96
268	str	r1, [r0, #0x10C]
269
270	ldr     r1, [r0, #0x300]
271	ldr     r2, =0x00003fff
272	bic     r1, r1, r2
273	ldr     r2, =0x00011301
274
275	orr	r1, r1, r2
276	str	r1, [r0, #0x300]
277	ldr     r1, [r0, #0x304]
278	ldr     r2, =0x00011110
279	orr     r1, r1, r2
280	str     r1, [r0, #0x304]
281	ldr     r1, =0x00000001
282	str     r1, [r0, #0x308]
283
284	/* Set Source Clock */
285	ldr	r1, =0x00001111			@ A, M, E, HPLL Muxing
286	str	r1, [r0, #0x200]		@ S5PC1XX_CLK_SRC0
287
288	b	200f
289110:
290	ldr	r0, =0xE010C000			@ S5PC110_PWR_CFG
291
292	/* Set OSC_FREQ value */
293	ldr	r1, =0xf
294	str	r1, [r0, #0x100]		@ S5PC110_OSC_FREQ
295
296	/* Set MTC_STABLE value */
297	ldr	r1, =0xffffffff
298	str	r1, [r0, #0x110]		@ S5PC110_MTC_STABLE
299
300	/* Set CLAMP_STABLE value */
301	ldr	r1, =0x3ff03ff
302	str	r1, [r0, #0x114]		@ S5PC110_CLAMP_STABLE
303
304	ldr	r0, =S5PC110_CLOCK_BASE		@ 0xE0100000
305
306	/* Set Clock divider */
307	ldr	r1, =0x14131330			@ 1:1:4:4, 1:4:5
308	str	r1, [r0, #0x300]
309	ldr	r1, =0x11110111			@ UART[3210]: MMC[3210]
310	str	r1, [r0, #0x310]
311
312	/* Set Lock Time */
313	ldr	r1, =0x2cf			@ Locktime : 30us
314	str	r1, [r0, #0x000]		@ S5PC110_APLL_LOCK
315	ldr	r1, =0xe10			@ Locktime : 0xe10 = 3600
316	str	r1, [r0, #0x008]		@ S5PC110_MPLL_LOCK
317	str	r1, [r0, #0x010]		@ S5PC110_EPLL_LOCK
318	str	r1, [r0, #0x020]		@ S5PC110_VPLL_LOCK
319
320	/* S5PC110_APLL_CON */
321	ldr	r1, =0x80C80601			@ 800MHz
322	str	r1, [r0, #0x100]
323	/* S5PC110_MPLL_CON */
324	ldr	r1, =0x829B0C01			@ 667MHz
325	str	r1, [r0, #0x108]
326	/* S5PC110_EPLL_CON */
327	ldr	r1, =0x80600602			@  96MHz VSEL 0 P 6 M 96 S 2
328	str	r1, [r0, #0x110]
329	/* S5PC110_VPLL_CON */
330	ldr	r1, =0x806C0603			@  54MHz
331	str	r1, [r0, #0x120]
332
333	/* Set Source Clock */
334	ldr	r1, =0x10001111			@ A, M, E, VPLL Muxing
335	str	r1, [r0, #0x200]		@ S5PC1XX_CLK_SRC0
336
337	/* OneDRAM(DMC0) clock setting */
338	ldr	r1, =0x01000000			@ ONEDRAM_SEL[25:24] 1 SCLKMPLL
339	str	r1, [r0, #0x218]		@ S5PC110_CLK_SRC6
340	ldr	r1, =0x30000000			@ ONEDRAM_RATIO[31:28] 3 + 1
341	str	r1, [r0, #0x318]		@ S5PC110_CLK_DIV6
342
343	/* XCLKOUT = XUSBXTI 24MHz */
344	add	r2, r0, #0xE000			@ S5PC110_OTHERS
345	ldr     r1, [r2]
346	orr	r1, r1, #(0x3 << 8)		@ CLKOUT[9:8] 3 XUSBXTI
347	str	r1, [r2]
348
349	/* CLK_IP0 */
350	ldr	r1, =0x8fefeeb			@ DMC[1:0] PDMA0[3] IMEM[5]
351	str	r1, [r0, #0x460]		@ S5PC110_CLK_IP0
352
353	/* CLK_IP1 */
354	ldr	r1, =0xe9fdf0f9			@ FIMD[0] USBOTG[16]
355						@ NANDXL[24]
356	str	r1, [r0, #0x464]		@ S5PC110_CLK_IP1
357
358	/* CLK_IP2 */
359	ldr	r1, =0xf75f7fc			@ CORESIGHT[8] MODEM[9]
360						@ HOSTIF[10] HSMMC0[16]
361						@ HSMMC2[18] VIC[27:24]
362	str	r1, [r0, #0x468]		@ S5PC110_CLK_IP2
363
364	/* CLK_IP3 */
365	ldr	r1, =0x8eff038c			@ I2C[8:6]
366						@ SYSTIMER[16] UART0[17]
367						@ UART1[18] UART2[19]
368						@ UART3[20] WDT[22]
369						@ PWM[23] GPIO[26] SYSCON[27]
370	str	r1, [r0, #0x46c]		@ S5PC110_CLK_IP3
371
372	/* CLK_IP4 */
373	ldr	r1, =0xfffffff1			@ CHIP_ID[0] TZPC[8:5]
374	str	r1, [r0, #0x470]		@ S5PC110_CLK_IP3
375
376200:
377	/* wait at least 200us to stablize all clock */
378	mov	r2, #0x10000
3791:	subs	r2, r2, #1
380	bne	1b
381
382	mov	pc, lr
383
384internal_ram_init:
385	ldreq	r0, =0xE3800000
386	ldrne	r0, =0xF1500000
387	ldr	r1, =0x0
388	str	r1, [r0]
389
390	mov	pc, lr
391
392/*
393 * uart_asm_init: Initialize UART's pins
394 */
395uart_asm_init:
396	/* set GPIO to enable UART0-UART4 */
397	mov	r0, r8
398	ldr	r1, =0x22222222
399	str	r1, [r0, #0x0]			@ S5PC100_GPIO_A0_OFFSET
400	ldr	r1, =0x00002222
401	str	r1, [r0, #0x20]			@ S5PC100_GPIO_A1_OFFSET
402
403	/* Check S5PC100 */
404	cmp	r7, r8
405	bne	110f
406
407	/* UART_SEL GPK0[5] at S5PC100 */
408	add	r0, r8, #0x2A0			@ S5PC100_GPIO_K0_OFFSET
409	ldr	r1, [r0, #0x0]			@ S5PC1XX_GPIO_CON_OFFSET
410	bic	r1, r1, #(0xf << 20)		@ 20 = 5 * 4-bit
411	orr	r1, r1, #(0x1 << 20)		@ Output
412	str	r1, [r0, #0x0]			@ S5PC1XX_GPIO_CON_OFFSET
413
414	ldr	r1, [r0, #0x8]			@ S5PC1XX_GPIO_PULL_OFFSET
415	bic	r1, r1, #(0x3 << 10)		@ 10 = 5 * 2-bit
416	orr	r1, r1, #(0x2 << 10)		@ Pull-up enabled
417	str	r1, [r0, #0x8]			@ S5PC1XX_GPIO_PULL_OFFSET
418
419	ldr	r1, [r0, #0x4]			@ S5PC1XX_GPIO_DAT_OFFSET
420	orr	r1, r1, #(1 << 5)		@ 5 = 5 * 1-bit
421	str	r1, [r0, #0x4]			@ S5PC1XX_GPIO_DAT_OFFSET
422
423	b	200f
424110:
425	/*
426	 * Note that the following address
427	 * 0xE020'0360 is reserved address at S5PC100
428	 */
429	/* UART_SEL MP0_5[7] at S5PC110 */
430	add	r0, r8, #0x360			@ S5PC110_GPIO_MP0_5_OFFSET
431	ldr	r1, [r0, #0x0]			@ S5PC1XX_GPIO_CON_OFFSET
432	bic	r1, r1, #(0xf << 28)		@ 28 = 7 * 4-bit
433	orr	r1, r1, #(0x1 << 28)		@ Output
434	str	r1, [r0, #0x0]			@ S5PC1XX_GPIO_CON_OFFSET
435
436	ldr	r1, [r0, #0x8]			@ S5PC1XX_GPIO_PULL_OFFSET
437	bic	r1, r1, #(0x3 << 14)		@ 14 = 7 * 2-bit
438	orr	r1, r1, #(0x2 << 14)		@ Pull-up enabled
439	str	r1, [r0, #0x8]			@ S5PC1XX_GPIO_PULL_OFFSET
440
441	ldr	r1, [r0, #0x4]			@ S5PC1XX_GPIO_DAT_OFFSET
442	orr	r1, r1, #(1 << 7)		@ 7 = 7 * 1-bit
443	str	r1, [r0, #0x4]			@ S5PC1XX_GPIO_DAT_OFFSET
444200:
445	mov	pc, lr
446