1/*
2 * Memory Setup stuff - taken from blob memsetup.S
3 *
4 * Copyright (C) 2009 Samsung Electronics
5 * Kyungmin Park <kyungmin.park@samsung.com>
6 *
7 * See file CREDITS for list of people who contributed to this
8 * project.
9 *
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of
13 * the License, or (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
23 * MA 02111-1307 USA
24 */
25
26#include <config.h>
27#include <version.h>
28#include <asm/arch/cpu.h>
29#include <asm/arch/clock.h>
30#include <asm/arch/power.h>
31
32/*
33 * Register usages:
34 *
35 * r5 has zero always
36 * r7 has S5PC100 GPIO base, 0xE0300000
37 * r8 has real GPIO base, 0xE0300000, 0xE0200000 at S5PC100, S5PC110 repectively
38 * r9 has Mobile DDR size, 1 means 1GiB, 2 means 2GiB and so on
39 */
40
41_TEXT_BASE:
42	.word	CONFIG_SYS_TEXT_BASE
43
44	.globl lowlevel_init
45lowlevel_init:
46	mov	r11, lr
47
48	/* r5 has always zero */
49	mov	r5, #0
50
51	ldr	r7, =S5PC100_GPIO_BASE
52	ldr	r8, =S5PC100_GPIO_BASE
53	/* Read CPU ID */
54	ldr	r2, =S5PC110_PRO_ID
55	ldr	r0, [r2]
56	mov	r1, #0x00010000
57	and	r0, r0, r1
58	cmp	r0, r5
59	beq	100f
60	ldr	r8, =S5PC110_GPIO_BASE
61100:
62	/* Turn on KEY_LED_ON [GPJ4(1)] XMSMWEN */
63	cmp	r7, r8
64	beq	skip_check_didle			@ Support C110 only
65
66	ldr	r0, =S5PC110_RST_STAT
67	ldr	r1, [r0]
68	and	r1, r1, #0x000D0000
69	cmp	r1, #(0x1 << 19)			@ DEEPIDLE_WAKEUP
70	beq	didle_wakeup
71	cmp	r7, r8
72
73skip_check_didle:
74	addeq	r0, r8, #0x280				@ S5PC100_GPIO_J4
75	addne	r0, r8, #0x2C0				@ S5PC110_GPIO_J4
76	ldr	r1, [r0, #0x0]				@ GPIO_CON_OFFSET
77	bic	r1, r1, #(0xf << 4)			@ 1 * 4-bit
78	orr	r1, r1, #(0x1 << 4)
79	str	r1, [r0, #0x0]				@ GPIO_CON_OFFSET
80
81	ldr	r1, [r0, #0x4]				@ GPIO_DAT_OFFSET
82	bic	r1, r1, #(1 << 1)
83	str	r1, [r0, #0x4]				@ GPIO_DAT_OFFSET
84
85	/* Don't setup at s5pc100 */
86	beq	100f
87
88	/*
89	 * Initialize Async Register Setting for EVT1
90	 * Because we are setting EVT1 as the default value of EVT0,
91	 * setting EVT0 as well does not make things worse.
92	 * Thus, for the simplicity, we set for EVT0, too
93	 *
94	 * The "Async Registers" are:
95	 *	0xE0F0_0000
96	 *	0xE1F0_0000
97	 *	0xF180_0000
98	 *	0xF190_0000
99	 *	0xF1A0_0000
100	 *	0xF1B0_0000
101	 *	0xF1C0_0000
102	 *	0xF1D0_0000
103	 *	0xF1E0_0000
104	 *	0xF1F0_0000
105	 *	0xFAF0_0000
106	 */
107	ldr     r0, =0xe0f00000
108	ldr     r1, [r0]
109	bic     r1, r1, #0x1
110	str     r1, [r0]
111
112	ldr     r0, =0xe1f00000
113	ldr     r1, [r0]
114	bic     r1, r1, #0x1
115	str     r1, [r0]
116
117	ldr     r0, =0xf1800000
118	ldr     r1, [r0]
119	bic     r1, r1, #0x1
120	str     r1, [r0]
121
122	ldr     r0, =0xf1900000
123	ldr     r1, [r0]
124	bic     r1, r1, #0x1
125	str     r1, [r0]
126
127	ldr     r0, =0xf1a00000
128	ldr     r1, [r0]
129	bic     r1, r1, #0x1
130	str     r1, [r0]
131
132	ldr     r0, =0xf1b00000
133	ldr     r1, [r0]
134	bic     r1, r1, #0x1
135	str     r1, [r0]
136
137	ldr     r0, =0xf1c00000
138	ldr     r1, [r0]
139	bic     r1, r1, #0x1
140	str     r1, [r0]
141
142	ldr     r0, =0xf1d00000
143	ldr     r1, [r0]
144	bic     r1, r1, #0x1
145	str     r1, [r0]
146
147	ldr     r0, =0xf1e00000
148	ldr     r1, [r0]
149	bic     r1, r1, #0x1
150	str     r1, [r0]
151
152	ldr     r0, =0xf1f00000
153	ldr     r1, [r0]
154	bic     r1, r1, #0x1
155	str     r1, [r0]
156
157	ldr     r0, =0xfaf00000
158	ldr     r1, [r0]
159	bic     r1, r1, #0x1
160	str     r1, [r0]
161
162	/*
163	 * Diable ABB block to reduce sleep current at low temperature
164	 * Note that it's hidden register setup don't modify it
165	 */
166	ldr	r0, =0xE010C300
167	ldr	r1, =0x00800000
168	str	r1, [r0]
169
170100:
171	/* IO retension release */
172	ldreq	r0, =S5PC100_OTHERS			@ 0xE0108200
173	ldrne	r0, =S5PC110_OTHERS			@ 0xE010E000
174	ldr	r1, [r0]
175	ldreq	r2, =(1 << 31)				@ IO_RET_REL
176	ldrne	r2, =((1 << 31) | (1 << 30) | (1 << 29) | (1 << 28))
177	orr	r1, r1, r2
178	/* Do not release retention here for S5PC110 */
179	streq	r1, [r0]
180
181	/* Disable Watchdog */
182	ldreq	r0, =S5PC100_WATCHDOG_BASE		@ 0xEA200000
183	ldrne	r0, =S5PC110_WATCHDOG_BASE		@ 0xE2700000
184	str	r5, [r0]
185
186	/* setting SRAM */
187	ldreq	r0, =S5PC100_SROMC_BASE
188	ldrne	r0, =S5PC110_SROMC_BASE
189	ldr	r1, =0x9
190	str	r1, [r0]
191
192	/* S5PC100 has 3 groups of interrupt sources */
193	ldreq	r0, =S5PC100_VIC0_BASE			@ 0xE4000000
194	ldrne	r0, =S5PC110_VIC0_BASE			@ 0xF2000000
195	add	r1, r0, #0x00100000
196	add	r2, r0, #0x00200000
197
198	/* Disable all interrupts (VIC0, VIC1 and VIC2) */
199	mvn	r3, #0x0
200	str	r3, [r0, #0x14]				@ INTENCLEAR
201	str	r3, [r1, #0x14]				@ INTENCLEAR
202	str	r3, [r2, #0x14]				@ INTENCLEAR
203
204	/* Set all interrupts as IRQ */
205	str	r5, [r0, #0xc]				@ INTSELECT
206	str	r5, [r1, #0xc]				@ INTSELECT
207	str	r5, [r2, #0xc]				@ INTSELECT
208
209	/* Pending Interrupt Clear */
210	str	r5, [r0, #0xf00]			@ INTADDRESS
211	str	r5, [r1, #0xf00]			@ INTADDRESS
212	str	r5, [r2, #0xf00]			@ INTADDRESS
213
214	/* for UART */
215	bl	uart_asm_init
216
217	bl	internal_ram_init
218
219	cmp	r7, r8
220	/* Clear wakeup status register */
221	ldreq	r0, =S5PC100_WAKEUP_STAT
222	ldrne	r0, =S5PC110_WAKEUP_STAT
223	ldr	r1, [r0]
224	str	r1, [r0]
225
226	/* IO retension release */
227	ldreq	r0, =S5PC100_OTHERS			@ 0xE0108200
228	ldrne	r0, =S5PC110_OTHERS			@ 0xE010E000
229	ldr	r1, [r0]
230	ldreq	r2, =(1 << 31)				@ IO_RET_REL
231	ldrne	r2, =((1 << 31) | (1 << 30) | (1 << 29) | (1 << 28))
232	orr	r1, r1, r2
233	str	r1, [r0]
234
235	b	1f
236
237didle_wakeup:
238	/* Wait when APLL is locked */
239	ldr	r0, =0xE0100100			@ S5PC110_APLL_CON
240lockloop:
241	ldr	r1, [r0]
242	and	r1, r1, #(1 << 29)
243	cmp	r1, #(1 << 29)
244	bne	lockloop
245
246	ldr	r0, =S5PC110_INFORM0
247	ldr	r1, [r0]
248	mov	pc, r1
249	nop
250	nop
251	nop
252	nop
253	nop
254
2551:
256	mov	lr, r11
257	mov	pc, lr
258
259/*
260 * system_clock_init: Initialize core clock and bus clock.
261 * void system_clock_init(void)
262 */
263system_clock_init:
264	ldr	r0, =S5PC110_CLOCK_BASE		@ 0xE0100000
265
266	/* Check S5PC100 */
267	cmp	r7, r8
268	bne	110f
269100:
270	/* Set Lock Time */
271	ldr	r1, =0xe10			@ Locktime : 0xe10 = 3600
272	str	r1, [r0, #0x000]		@ S5PC100_APLL_LOCK
273	str	r1, [r0, #0x004]		@ S5PC100_MPLL_LOCK
274	str	r1, [r0, #0x008]		@ S5PC100_EPLL_LOCK
275	str	r1, [r0, #0x00C]		@ S5PC100_HPLL_LOCK
276
277	/* S5P_APLL_CON */
278	ldr	r1, =0x81bc0400		@ SDIV 0, PDIV 4, MDIV 444 (1333MHz)
279	str	r1, [r0, #0x100]
280	/* S5P_MPLL_CON */
281	ldr	r1, =0x80590201		@ SDIV 1, PDIV 2, MDIV 89 (267MHz)
282	str	r1, [r0, #0x104]
283	/* S5P_EPLL_CON */
284	ldr	r1, =0x80870303		@ SDIV 3, PDIV 3, MDIV 135 (67.5MHz)
285	str	r1, [r0, #0x108]
286	/* S5P_HPLL_CON */
287	ldr	r1, =0x80600603		@ SDIV 3, PDIV 6, MDIV 96
288	str	r1, [r0, #0x10C]
289
290	ldr     r1, [r0, #0x300]
291	ldr     r2, =0x00003fff
292	bic     r1, r1, r2
293	ldr     r2, =0x00011301
294
295	orr	r1, r1, r2
296	str	r1, [r0, #0x300]
297	ldr     r1, [r0, #0x304]
298	ldr     r2, =0x00011110
299	orr     r1, r1, r2
300	str     r1, [r0, #0x304]
301	ldr     r1, =0x00000001
302	str     r1, [r0, #0x308]
303
304	/* Set Source Clock */
305	ldr	r1, =0x00001111			@ A, M, E, HPLL Muxing
306	str	r1, [r0, #0x200]		@ S5PC1XX_CLK_SRC0
307
308	b	200f
309110:
310	ldr	r0, =0xE010C000			@ S5PC110_PWR_CFG
311
312	/* Set OSC_FREQ value */
313	ldr	r1, =0xf
314	str	r1, [r0, #0x100]		@ S5PC110_OSC_FREQ
315
316	/* Set MTC_STABLE value */
317	ldr	r1, =0xffffffff
318	str	r1, [r0, #0x110]		@ S5PC110_MTC_STABLE
319
320	/* Set CLAMP_STABLE value */
321	ldr	r1, =0x3ff03ff
322	str	r1, [r0, #0x114]		@ S5PC110_CLAMP_STABLE
323
324	ldr	r0, =S5PC110_CLOCK_BASE		@ 0xE0100000
325
326	/* Set Clock divider */
327	ldr	r1, =0x14131330			@ 1:1:4:4, 1:4:5
328	str	r1, [r0, #0x300]
329	ldr	r1, =0x11110111			@ UART[3210]: MMC[3210]
330	str	r1, [r0, #0x310]
331
332	/* Set Lock Time */
333	ldr	r1, =0x2cf			@ Locktime : 30us
334	str	r1, [r0, #0x000]		@ S5PC110_APLL_LOCK
335	ldr	r1, =0xe10			@ Locktime : 0xe10 = 3600
336	str	r1, [r0, #0x008]		@ S5PC110_MPLL_LOCK
337	str	r1, [r0, #0x010]		@ S5PC110_EPLL_LOCK
338	str	r1, [r0, #0x020]		@ S5PC110_VPLL_LOCK
339
340	/* S5PC110_APLL_CON */
341	ldr	r1, =0x80C80601			@ 800MHz
342	str	r1, [r0, #0x100]
343	/* S5PC110_MPLL_CON */
344	ldr	r1, =0x829B0C01			@ 667MHz
345	str	r1, [r0, #0x108]
346	/* S5PC110_EPLL_CON */
347	ldr	r1, =0x80600602			@  96MHz VSEL 0 P 6 M 96 S 2
348	str	r1, [r0, #0x110]
349	/* S5PC110_VPLL_CON */
350	ldr	r1, =0x806C0603			@  54MHz
351	str	r1, [r0, #0x120]
352
353	/* Set Source Clock */
354	ldr	r1, =0x10001111			@ A, M, E, VPLL Muxing
355	str	r1, [r0, #0x200]		@ S5PC1XX_CLK_SRC0
356
357	/* OneDRAM(DMC0) clock setting */
358	ldr	r1, =0x01000000			@ ONEDRAM_SEL[25:24] 1 SCLKMPLL
359	str	r1, [r0, #0x218]		@ S5PC110_CLK_SRC6
360	ldr	r1, =0x30000000			@ ONEDRAM_RATIO[31:28] 3 + 1
361	str	r1, [r0, #0x318]		@ S5PC110_CLK_DIV6
362
363	/* XCLKOUT = XUSBXTI 24MHz */
364	add	r2, r0, #0xE000			@ S5PC110_OTHERS
365	ldr     r1, [r2]
366	orr	r1, r1, #(0x3 << 8)		@ CLKOUT[9:8] 3 XUSBXTI
367	str	r1, [r2]
368
369	/* CLK_IP0 */
370	ldr	r1, =0x8fefeeb			@ DMC[1:0] PDMA0[3] IMEM[5]
371	str	r1, [r0, #0x460]		@ S5PC110_CLK_IP0
372
373	/* CLK_IP1 */
374	ldr	r1, =0xe9fdf0f9			@ FIMD[0] USBOTG[16]
375						@ NANDXL[24]
376	str	r1, [r0, #0x464]		@ S5PC110_CLK_IP1
377
378	/* CLK_IP2 */
379	ldr	r1, =0xf75f7fc			@ CORESIGHT[8] MODEM[9]
380						@ HOSTIF[10] HSMMC0[16]
381						@ HSMMC2[18] VIC[27:24]
382	str	r1, [r0, #0x468]		@ S5PC110_CLK_IP2
383
384	/* CLK_IP3 */
385	ldr	r1, =0x8eff038c			@ I2C[8:6]
386						@ SYSTIMER[16] UART0[17]
387						@ UART1[18] UART2[19]
388						@ UART3[20] WDT[22]
389						@ PWM[23] GPIO[26] SYSCON[27]
390	str	r1, [r0, #0x46c]		@ S5PC110_CLK_IP3
391
392	/* CLK_IP4 */
393	ldr	r1, =0xfffffff1			@ CHIP_ID[0] TZPC[8:5]
394	str	r1, [r0, #0x470]		@ S5PC110_CLK_IP3
395
396200:
397	/* wait at least 200us to stablize all clock */
398	mov	r2, #0x10000
3991:	subs	r2, r2, #1
400	bne	1b
401
402	mov	pc, lr
403
404internal_ram_init:
405	ldreq	r0, =0xE3800000
406	ldrne	r0, =0xF1500000
407	ldr	r1, =0x0
408	str	r1, [r0]
409
410	mov	pc, lr
411
412/*
413 * uart_asm_init: Initialize UART's pins
414 */
415uart_asm_init:
416	/* set GPIO to enable UART0-UART4 */
417	mov	r0, r8
418	ldr	r1, =0x22222222
419	str	r1, [r0, #0x0]			@ S5PC100_GPIO_A0_OFFSET
420	ldr	r1, =0x00002222
421	str	r1, [r0, #0x20]			@ S5PC100_GPIO_A1_OFFSET
422
423	/* Check S5PC100 */
424	cmp	r7, r8
425	bne	110f
426
427	/* UART_SEL GPK0[5] at S5PC100 */
428	add	r0, r8, #0x2A0			@ S5PC100_GPIO_K0_OFFSET
429	ldr	r1, [r0, #0x0]			@ S5PC1XX_GPIO_CON_OFFSET
430	bic	r1, r1, #(0xf << 20)		@ 20 = 5 * 4-bit
431	orr	r1, r1, #(0x1 << 20)		@ Output
432	str	r1, [r0, #0x0]			@ S5PC1XX_GPIO_CON_OFFSET
433
434	ldr	r1, [r0, #0x8]			@ S5PC1XX_GPIO_PULL_OFFSET
435	bic	r1, r1, #(0x3 << 10)		@ 10 = 5 * 2-bit
436	orr	r1, r1, #(0x2 << 10)		@ Pull-up enabled
437	str	r1, [r0, #0x8]			@ S5PC1XX_GPIO_PULL_OFFSET
438
439	ldr	r1, [r0, #0x4]			@ S5PC1XX_GPIO_DAT_OFFSET
440	orr	r1, r1, #(1 << 5)		@ 5 = 5 * 1-bit
441	str	r1, [r0, #0x4]			@ S5PC1XX_GPIO_DAT_OFFSET
442
443	b	200f
444110:
445	/*
446	 * Note that the following address
447	 * 0xE020'0360 is reserved address at S5PC100
448	 */
449	/* UART_SEL MP0_5[7] at S5PC110 */
450	add	r0, r8, #0x360			@ S5PC110_GPIO_MP0_5_OFFSET
451	ldr	r1, [r0, #0x0]			@ S5PC1XX_GPIO_CON_OFFSET
452	bic	r1, r1, #(0xf << 28)		@ 28 = 7 * 4-bit
453	orr	r1, r1, #(0x1 << 28)		@ Output
454	str	r1, [r0, #0x0]			@ S5PC1XX_GPIO_CON_OFFSET
455
456	ldr	r1, [r0, #0x8]			@ S5PC1XX_GPIO_PULL_OFFSET
457	bic	r1, r1, #(0x3 << 14)		@ 14 = 7 * 2-bit
458	orr	r1, r1, #(0x2 << 14)		@ Pull-up enabled
459	str	r1, [r0, #0x8]			@ S5PC1XX_GPIO_PULL_OFFSET
460
461	ldr	r1, [r0, #0x4]			@ S5PC1XX_GPIO_DAT_OFFSET
462	orr	r1, r1, #(1 << 7)		@ 7 = 7 * 1-bit
463	str	r1, [r0, #0x4]			@ S5PC1XX_GPIO_DAT_OFFSET
464200:
465	mov	pc, lr
466