1 /* 2 * Copyright (C) 2012 Samsung Electronics 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #include <common.h> 8 #include <dm.h> 9 #include <dwc3-uboot.h> 10 #include <fdtdec.h> 11 #include <asm/io.h> 12 #include <errno.h> 13 #include <i2c.h> 14 #include <mmc.h> 15 #include <netdev.h> 16 #include <samsung-usb-phy-uboot.h> 17 #include <spi.h> 18 #include <usb.h> 19 #include <video_bridge.h> 20 #include <asm/gpio.h> 21 #include <asm/arch/cpu.h> 22 #include <asm/arch/dwmmc.h> 23 #include <asm/arch/mmc.h> 24 #include <asm/arch/pinmux.h> 25 #include <asm/arch/power.h> 26 #include <asm/arch/sromc.h> 27 #include <power/pmic.h> 28 #include <power/max77686_pmic.h> 29 #include <power/regulator.h> 30 #include <power/s5m8767.h> 31 #include <tmu.h> 32 33 DECLARE_GLOBAL_DATA_PTR; 34 35 static void board_enable_audio_codec(void) 36 { 37 int node, ret; 38 struct gpio_desc en_gpio; 39 40 node = fdtdec_next_compatible(gd->fdt_blob, 0, 41 COMPAT_SAMSUNG_EXYNOS5_SOUND); 42 if (node <= 0) 43 return; 44 45 ret = gpio_request_by_name_nodev(gd->fdt_blob, node, 46 "codec-enable-gpio", 0, &en_gpio, 47 GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE); 48 if (ret == -FDT_ERR_NOTFOUND) 49 return; 50 51 /* Turn on the GPIO which connects to the codec's "enable" line. */ 52 gpio_set_pull(gpio_get_number(&en_gpio), S5P_GPIO_PULL_NONE); 53 54 #ifdef CONFIG_SOUND_MAX98095 55 /* Enable MAX98095 Codec */ 56 gpio_request(EXYNOS5_GPIO_X17, "max98095_enable"); 57 gpio_direction_output(EXYNOS5_GPIO_X17, 1); 58 gpio_set_pull(EXYNOS5_GPIO_X17, S5P_GPIO_PULL_NONE); 59 #endif 60 } 61 62 int exynos_init(void) 63 { 64 board_enable_audio_codec(); 65 66 return 0; 67 } 68 69 static int exynos_set_regulator(const char *name, uint uv) 70 { 71 struct udevice *dev; 72 int ret; 73 74 ret = regulator_get_by_platname(name, &dev); 75 if (ret) { 76 debug("%s: Cannot find regulator %s\n", __func__, name); 77 return ret; 78 } 79 ret = regulator_set_value(dev, uv); 80 if (ret) { 81 debug("%s: Cannot set regulator %s\n", __func__, name); 82 return ret; 83 } 84 85 return 0; 86 } 87 88 int exynos_power_init(void) 89 { 90 struct udevice *dev; 91 int ret; 92 93 ret = pmic_get("max77686", &dev); 94 if (!ret) { 95 /* TODO(sjg@chromium.org): Move into the clock/pmic API */ 96 ret = pmic_clrsetbits(dev, MAX77686_REG_PMIC_32KHZ, 0, 97 MAX77686_32KHCP_EN); 98 if (ret) 99 return ret; 100 ret = pmic_clrsetbits(dev, MAX77686_REG_PMIC_BBAT, 0, 101 MAX77686_BBCHOSTEN | MAX77686_BBCVS_3_5V); 102 if (ret) 103 return ret; 104 } else { 105 ret = pmic_get("s5m8767-pmic", &dev); 106 /* TODO(sjg@chromium.org): Use driver model to access clock */ 107 #ifdef CONFIG_PMIC_S5M8767 108 if (!ret) 109 s5m8767_enable_32khz_cp(dev); 110 #endif 111 } 112 if (ret == -ENODEV) 113 return 0; 114 115 ret = regulators_enable_boot_on(false); 116 if (ret) 117 return ret; 118 119 ret = exynos_set_regulator("vdd_mif", 1100000); 120 if (ret) 121 return ret; 122 123 /* 124 * This would normally be 1.3V, but since we are running slowly 1V 125 * is enough. For spring it helps reduce CPU temperature and avoid 126 * hangs with the case open. 127 */ 128 ret = exynos_set_regulator("vdd_arm", 1000000); 129 if (ret) 130 return ret; 131 ret = exynos_set_regulator("vdd_int", 1012500); 132 if (ret) 133 return ret; 134 ret = exynos_set_regulator("vdd_g3d", 1200000); 135 if (ret) 136 return ret; 137 138 return 0; 139 } 140 141 int board_get_revision(void) 142 { 143 return 0; 144 } 145 146 #ifdef CONFIG_LCD 147 148 static int board_dp_bridge_init(struct udevice *dev) 149 { 150 const int max_tries = 10; 151 int num_tries; 152 int ret; 153 154 debug("%s\n", __func__); 155 ret = video_bridge_attach(dev); 156 if (ret) { 157 debug("video bridge init failed: %d\n", ret); 158 return ret; 159 } 160 161 /* 162 * We need to wait for 90ms after bringing up the bridge since there 163 * is a phantom "high" on the HPD chip during its bootup. The phantom 164 * high comes within 7ms of de-asserting PD and persists for at least 165 * 15ms. The real high comes roughly 50ms after PD is de-asserted. The 166 * phantom high makes it hard for us to know when the NXP chip is up. 167 */ 168 mdelay(90); 169 170 for (num_tries = 0; num_tries < max_tries; num_tries++) { 171 /* Check HPD. If it's high, or we don't have it, all is well */ 172 ret = video_bridge_check_attached(dev); 173 if (!ret || ret == -ENOENT) 174 return 0; 175 176 debug("%s: eDP bridge failed to come up; try %d of %d\n", 177 __func__, num_tries, max_tries); 178 } 179 180 /* Immediately go into bridge reset if the hp line is not high */ 181 return -EIO; 182 } 183 184 static int board_dp_bridge_setup(const void *blob) 185 { 186 const int max_tries = 2; 187 int num_tries; 188 struct udevice *dev; 189 int ret; 190 191 /* Configure I2C registers for Parade bridge */ 192 ret = uclass_get_device(UCLASS_VIDEO_BRIDGE, 0, &dev); 193 if (ret) { 194 debug("video bridge init failed: %d\n", ret); 195 return ret; 196 } 197 198 if (strncmp(dev->driver->name, "parade", 6)) { 199 /* Mux HPHPD to the special hotplug detect mode */ 200 exynos_pinmux_config(PERIPH_ID_DPHPD, 0); 201 } 202 203 for (num_tries = 0; num_tries < max_tries; num_tries++) { 204 ret = board_dp_bridge_init(dev); 205 if (!ret) 206 return 0; 207 if (num_tries == max_tries - 1) 208 break; 209 210 /* 211 * If we're here, the bridge chip failed to initialise. 212 * Power down the bridge in an attempt to reset. 213 */ 214 video_bridge_set_active(dev, false); 215 216 /* 217 * Arbitrarily wait 300ms here with DP_N low. Don't know for 218 * sure how long we should wait, but we're being paranoid. 219 */ 220 mdelay(300); 221 } 222 223 return ret; 224 } 225 226 void exynos_cfg_lcd_gpio(void) 227 { 228 /* For Backlight */ 229 gpio_request(EXYNOS5_GPIO_B20, "lcd_backlight"); 230 gpio_cfg_pin(EXYNOS5_GPIO_B20, S5P_GPIO_OUTPUT); 231 gpio_set_value(EXYNOS5_GPIO_B20, 1); 232 } 233 234 void exynos_set_dp_phy(unsigned int onoff) 235 { 236 set_dp_phy_ctrl(onoff); 237 } 238 239 static int board_dp_set_backlight(int percent) 240 { 241 struct udevice *dev; 242 int ret; 243 244 ret = uclass_get_device(UCLASS_VIDEO_BRIDGE, 0, &dev); 245 if (!ret) 246 ret = video_bridge_set_backlight(dev, percent); 247 248 return ret; 249 } 250 251 void exynos_backlight_on(unsigned int on) 252 { 253 struct udevice *dev; 254 int ret; 255 256 debug("%s(%u)\n", __func__, on); 257 if (!on) 258 return; 259 260 ret = regulator_get_by_platname("vcd_led", &dev); 261 if (!ret) 262 ret = regulator_set_enable(dev, true); 263 if (ret) 264 debug("Failed to enable backlight: ret=%d\n", ret); 265 266 /* T5 in the LCD timing spec (defined as > 10ms) */ 267 mdelay(10); 268 269 /* board_dp_backlight_pwm */ 270 gpio_direction_output(EXYNOS5_GPIO_B20, 1); 271 272 /* T6 in the LCD timing spec (defined as > 10ms) */ 273 mdelay(10); 274 275 /* try to set the backlight in the bridge registers */ 276 ret = board_dp_set_backlight(80); 277 278 /* if we have no bridge or it does not support backlight, use a GPIO */ 279 if (ret == -ENODEV || ret == -ENOSYS) { 280 gpio_request(EXYNOS5_GPIO_X30, "board_dp_backlight_en"); 281 gpio_direction_output(EXYNOS5_GPIO_X30, 1); 282 } 283 } 284 285 void exynos_lcd_power_on(void) 286 { 287 struct udevice *dev; 288 int ret; 289 290 debug("%s\n", __func__); 291 ret = regulator_get_by_platname("lcd_vdd", &dev); 292 if (!ret) 293 ret = regulator_set_enable(dev, true); 294 if (ret) 295 debug("Failed to enable LCD panel: ret=%d\n", ret); 296 297 ret = board_dp_bridge_setup(gd->fdt_blob); 298 if (ret && ret != -ENODEV) 299 printf("LCD bridge failed to enable: %d\n", ret); 300 } 301 302 #endif 303 304 #ifdef CONFIG_USB_DWC3 305 static struct dwc3_device dwc3_device_data = { 306 .maximum_speed = USB_SPEED_SUPER, 307 .base = 0x12400000, 308 .dr_mode = USB_DR_MODE_PERIPHERAL, 309 .index = 0, 310 }; 311 312 int usb_gadget_handle_interrupts(void) 313 { 314 dwc3_uboot_handle_interrupt(0); 315 return 0; 316 } 317 318 int board_usb_init(int index, enum usb_init_type init) 319 { 320 struct exynos_usb3_phy *phy = (struct exynos_usb3_phy *) 321 samsung_get_base_usb3_phy(); 322 323 if (!phy) { 324 error("usb3 phy not supported"); 325 return -ENODEV; 326 } 327 328 set_usbdrd_phy_ctrl(POWER_USB_DRD_PHY_CTRL_EN); 329 exynos5_usb3_phy_init(phy); 330 331 return dwc3_uboot_init(&dwc3_device_data); 332 } 333 #endif 334 #ifdef CONFIG_SET_DFU_ALT_INFO 335 char *get_dfu_alt_system(char *interface, char *devstr) 336 { 337 return getenv("dfu_alt_system"); 338 } 339 340 char *get_dfu_alt_boot(char *interface, char *devstr) 341 { 342 struct mmc *mmc; 343 char *alt_boot; 344 int dev_num; 345 346 dev_num = simple_strtoul(devstr, NULL, 10); 347 348 mmc = find_mmc_device(dev_num); 349 if (!mmc) 350 return NULL; 351 352 if (mmc_init(mmc)) 353 return NULL; 354 355 if (IS_SD(mmc)) 356 alt_boot = CONFIG_DFU_ALT_BOOT_SD; 357 else 358 alt_boot = CONFIG_DFU_ALT_BOOT_EMMC; 359 360 return alt_boot; 361 } 362 #endif 363