1 /* 2 * Copyright (C) 2012 Samsung Electronics 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #include <common.h> 8 #include <dm.h> 9 #include <dwc3-uboot.h> 10 #include <fdtdec.h> 11 #include <asm/io.h> 12 #include <errno.h> 13 #include <i2c.h> 14 #include <mmc.h> 15 #include <netdev.h> 16 #include <samsung-usb-phy-uboot.h> 17 #include <spi.h> 18 #include <usb.h> 19 #include <video_bridge.h> 20 #include <asm/gpio.h> 21 #include <asm/arch/cpu.h> 22 #include <asm/arch/dwmmc.h> 23 #include <asm/arch/mmc.h> 24 #include <asm/arch/pinmux.h> 25 #include <asm/arch/power.h> 26 #include <asm/arch/sromc.h> 27 #include <power/pmic.h> 28 #include <power/max77686_pmic.h> 29 #include <power/regulator.h> 30 #include <power/s5m8767.h> 31 #include <tmu.h> 32 33 DECLARE_GLOBAL_DATA_PTR; 34 35 static void board_enable_audio_codec(void) 36 { 37 int node, ret; 38 struct gpio_desc en_gpio; 39 40 node = fdtdec_next_compatible(gd->fdt_blob, 0, 41 COMPAT_SAMSUNG_EXYNOS5_SOUND); 42 if (node <= 0) 43 return; 44 45 ret = gpio_request_by_name_nodev(gd->fdt_blob, node, 46 "codec-enable-gpio", 0, &en_gpio, 47 GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE); 48 if (ret == -FDT_ERR_NOTFOUND) 49 return; 50 51 /* Turn on the GPIO which connects to the codec's "enable" line. */ 52 gpio_set_pull(gpio_get_number(&en_gpio), S5P_GPIO_PULL_NONE); 53 54 #ifdef CONFIG_SOUND_MAX98095 55 /* Enable MAX98095 Codec */ 56 gpio_request(EXYNOS5_GPIO_X17, "max98095_enable"); 57 gpio_direction_output(EXYNOS5_GPIO_X17, 1); 58 gpio_set_pull(EXYNOS5_GPIO_X17, S5P_GPIO_PULL_NONE); 59 #endif 60 } 61 62 int exynos_init(void) 63 { 64 board_enable_audio_codec(); 65 66 return 0; 67 } 68 69 static int exynos_set_regulator(const char *name, uint uv) 70 { 71 struct udevice *dev; 72 int ret; 73 74 ret = regulator_get_by_platname(name, &dev); 75 if (ret) { 76 debug("%s: Cannot find regulator %s\n", __func__, name); 77 return ret; 78 } 79 ret = regulator_set_value(dev, uv); 80 if (ret) { 81 debug("%s: Cannot set regulator %s\n", __func__, name); 82 return ret; 83 } 84 85 return 0; 86 } 87 88 int exynos_power_init(void) 89 { 90 struct udevice *dev; 91 int ret; 92 93 ret = pmic_get("max77686", &dev); 94 if (!ret) { 95 /* TODO(sjg@chromium.org): Move into the clock/pmic API */ 96 ret = pmic_clrsetbits(dev, MAX77686_REG_PMIC_32KHZ, 0, 97 MAX77686_32KHCP_EN); 98 if (ret) 99 return ret; 100 ret = pmic_clrsetbits(dev, MAX77686_REG_PMIC_BBAT, 0, 101 MAX77686_BBCHOSTEN | MAX77686_BBCVS_3_5V); 102 if (ret) 103 return ret; 104 } else { 105 ret = pmic_get("s5m8767-pmic", &dev); 106 /* TODO(sjg@chromium.org): Use driver model to access clock */ 107 #ifdef CONFIG_PMIC_S5M8767 108 if (!ret) 109 s5m8767_enable_32khz_cp(dev); 110 #endif 111 } 112 if (ret == -ENODEV) 113 return 0; 114 115 ret = regulators_enable_boot_on(false); 116 if (ret) 117 return ret; 118 119 ret = exynos_set_regulator("vdd_mif", 1100000); 120 if (ret) 121 return ret; 122 123 /* 124 * This would normally be 1.3V, but since we are running slowly 1.1V 125 * is enough. For spring it helps reduce CPU temperature and avoid 126 * hangs with the case open. 1.1V is minimum voltage borderline for 127 * chained bootloaders. 128 */ 129 ret = exynos_set_regulator("vdd_arm", 1100000); 130 if (ret) 131 return ret; 132 ret = exynos_set_regulator("vdd_int", 1012500); 133 if (ret) 134 return ret; 135 ret = exynos_set_regulator("vdd_g3d", 1200000); 136 if (ret) 137 return ret; 138 139 return 0; 140 } 141 142 int board_get_revision(void) 143 { 144 return 0; 145 } 146 147 #ifdef CONFIG_LCD 148 149 static int board_dp_bridge_init(struct udevice *dev) 150 { 151 const int max_tries = 10; 152 int num_tries; 153 int ret; 154 155 debug("%s\n", __func__); 156 ret = video_bridge_attach(dev); 157 if (ret) { 158 debug("video bridge init failed: %d\n", ret); 159 return ret; 160 } 161 162 /* 163 * We need to wait for 90ms after bringing up the bridge since there 164 * is a phantom "high" on the HPD chip during its bootup. The phantom 165 * high comes within 7ms of de-asserting PD and persists for at least 166 * 15ms. The real high comes roughly 50ms after PD is de-asserted. The 167 * phantom high makes it hard for us to know when the NXP chip is up. 168 */ 169 mdelay(90); 170 171 for (num_tries = 0; num_tries < max_tries; num_tries++) { 172 /* Check HPD. If it's high, or we don't have it, all is well */ 173 ret = video_bridge_check_attached(dev); 174 if (!ret || ret == -ENOENT) 175 return 0; 176 177 debug("%s: eDP bridge failed to come up; try %d of %d\n", 178 __func__, num_tries, max_tries); 179 } 180 181 /* Immediately go into bridge reset if the hp line is not high */ 182 return -EIO; 183 } 184 185 static int board_dp_bridge_setup(const void *blob) 186 { 187 const int max_tries = 2; 188 int num_tries; 189 struct udevice *dev; 190 int ret; 191 192 /* Configure I2C registers for Parade bridge */ 193 ret = uclass_get_device(UCLASS_VIDEO_BRIDGE, 0, &dev); 194 if (ret) { 195 debug("video bridge init failed: %d\n", ret); 196 return ret; 197 } 198 199 if (strncmp(dev->driver->name, "parade", 6)) { 200 /* Mux HPHPD to the special hotplug detect mode */ 201 exynos_pinmux_config(PERIPH_ID_DPHPD, 0); 202 } 203 204 for (num_tries = 0; num_tries < max_tries; num_tries++) { 205 ret = board_dp_bridge_init(dev); 206 if (!ret) 207 return 0; 208 if (num_tries == max_tries - 1) 209 break; 210 211 /* 212 * If we're here, the bridge chip failed to initialise. 213 * Power down the bridge in an attempt to reset. 214 */ 215 video_bridge_set_active(dev, false); 216 217 /* 218 * Arbitrarily wait 300ms here with DP_N low. Don't know for 219 * sure how long we should wait, but we're being paranoid. 220 */ 221 mdelay(300); 222 } 223 224 return ret; 225 } 226 227 void exynos_cfg_lcd_gpio(void) 228 { 229 /* For Backlight */ 230 gpio_request(EXYNOS5_GPIO_B20, "lcd_backlight"); 231 gpio_cfg_pin(EXYNOS5_GPIO_B20, S5P_GPIO_OUTPUT); 232 gpio_set_value(EXYNOS5_GPIO_B20, 1); 233 } 234 235 void exynos_set_dp_phy(unsigned int onoff) 236 { 237 set_dp_phy_ctrl(onoff); 238 } 239 240 static int board_dp_set_backlight(int percent) 241 { 242 struct udevice *dev; 243 int ret; 244 245 ret = uclass_get_device(UCLASS_VIDEO_BRIDGE, 0, &dev); 246 if (!ret) 247 ret = video_bridge_set_backlight(dev, percent); 248 249 return ret; 250 } 251 252 void exynos_backlight_on(unsigned int on) 253 { 254 struct udevice *dev; 255 int ret; 256 257 debug("%s(%u)\n", __func__, on); 258 if (!on) 259 return; 260 261 ret = regulator_get_by_platname("vcd_led", &dev); 262 if (!ret) 263 ret = regulator_set_enable(dev, true); 264 if (ret) 265 debug("Failed to enable backlight: ret=%d\n", ret); 266 267 /* T5 in the LCD timing spec (defined as > 10ms) */ 268 mdelay(10); 269 270 /* board_dp_backlight_pwm */ 271 gpio_direction_output(EXYNOS5_GPIO_B20, 1); 272 273 /* T6 in the LCD timing spec (defined as > 10ms) */ 274 mdelay(10); 275 276 /* try to set the backlight in the bridge registers */ 277 ret = board_dp_set_backlight(80); 278 279 /* if we have no bridge or it does not support backlight, use a GPIO */ 280 if (ret == -ENODEV || ret == -ENOSYS) { 281 gpio_request(EXYNOS5_GPIO_X30, "board_dp_backlight_en"); 282 gpio_direction_output(EXYNOS5_GPIO_X30, 1); 283 } 284 } 285 286 void exynos_lcd_power_on(void) 287 { 288 struct udevice *dev; 289 int ret; 290 291 debug("%s\n", __func__); 292 ret = regulator_get_by_platname("lcd_vdd", &dev); 293 if (!ret) 294 ret = regulator_set_enable(dev, true); 295 if (ret) 296 debug("Failed to enable LCD panel: ret=%d\n", ret); 297 298 ret = board_dp_bridge_setup(gd->fdt_blob); 299 if (ret && ret != -ENODEV) 300 printf("LCD bridge failed to enable: %d\n", ret); 301 } 302 303 #endif 304 305 #ifdef CONFIG_USB_DWC3 306 static struct dwc3_device dwc3_device_data = { 307 .maximum_speed = USB_SPEED_SUPER, 308 .base = 0x12400000, 309 .dr_mode = USB_DR_MODE_PERIPHERAL, 310 .index = 0, 311 }; 312 313 int usb_gadget_handle_interrupts(void) 314 { 315 dwc3_uboot_handle_interrupt(0); 316 return 0; 317 } 318 319 int board_usb_init(int index, enum usb_init_type init) 320 { 321 struct exynos_usb3_phy *phy = (struct exynos_usb3_phy *) 322 samsung_get_base_usb3_phy(); 323 324 if (!phy) { 325 error("usb3 phy not supported"); 326 return -ENODEV; 327 } 328 329 set_usbdrd_phy_ctrl(POWER_USB_DRD_PHY_CTRL_EN); 330 exynos5_usb3_phy_init(phy); 331 332 return dwc3_uboot_init(&dwc3_device_data); 333 } 334 #endif 335 #ifdef CONFIG_SET_DFU_ALT_INFO 336 char *get_dfu_alt_system(char *interface, char *devstr) 337 { 338 return getenv("dfu_alt_system"); 339 } 340 341 char *get_dfu_alt_boot(char *interface, char *devstr) 342 { 343 struct mmc *mmc; 344 char *alt_boot; 345 int dev_num; 346 347 dev_num = simple_strtoul(devstr, NULL, 10); 348 349 mmc = find_mmc_device(dev_num); 350 if (!mmc) 351 return NULL; 352 353 if (mmc_init(mmc)) 354 return NULL; 355 356 if (IS_SD(mmc)) 357 alt_boot = CONFIG_DFU_ALT_BOOT_SD; 358 else 359 alt_boot = CONFIG_DFU_ALT_BOOT_EMMC; 360 361 return alt_boot; 362 } 363 #endif 364