1 /* 2 * (C) Copyright 2013 SAMSUNG Electronics 3 * Rajeshwari Shinde <rajeshwari.s@samsung.com> 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8 #include <common.h> 9 #include <cros_ec.h> 10 #include <errno.h> 11 #include <fdtdec.h> 12 #include <spi.h> 13 #include <tmu.h> 14 #include <netdev.h> 15 #include <asm/io.h> 16 #include <asm/arch/board.h> 17 #include <asm/arch/cpu.h> 18 #include <asm/arch/dwmmc.h> 19 #include <asm/arch/gpio.h> 20 #include <asm/arch/mmc.h> 21 #include <asm/arch/pinmux.h> 22 #include <asm/arch/power.h> 23 #include <power/pmic.h> 24 #include <asm/arch/sromc.h> 25 #include <power/max77686_pmic.h> 26 27 DECLARE_GLOBAL_DATA_PTR; 28 29 #if defined CONFIG_EXYNOS_TMU 30 /* Boot Time Thermal Analysis for SoC temperature threshold breach */ 31 static void boot_temp_check(void) 32 { 33 int temp; 34 35 switch (tmu_monitor(&temp)) { 36 case TMU_STATUS_NORMAL: 37 break; 38 case TMU_STATUS_TRIPPED: 39 /* 40 * Status TRIPPED ans WARNING means corresponding threshold 41 * breach 42 */ 43 puts("EXYNOS_TMU: TRIPPING! Device power going down ...\n"); 44 set_ps_hold_ctrl(); 45 hang(); 46 break; 47 case TMU_STATUS_WARNING: 48 puts("EXYNOS_TMU: WARNING! Temperature very high\n"); 49 break; 50 case TMU_STATUS_INIT: 51 /* 52 * TMU_STATUS_INIT means something is wrong with temperature 53 * sensing and TMU status was changed back from NORMAL to INIT. 54 */ 55 puts("EXYNOS_TMU: WARNING! Temperature sensing not done\n"); 56 break; 57 default: 58 debug("EXYNOS_TMU: Unknown TMU state\n"); 59 } 60 } 61 #endif 62 63 int board_init(void) 64 { 65 gd->bd->bi_boot_params = (PHYS_SDRAM_1 + 0x100UL); 66 #if defined CONFIG_EXYNOS_TMU 67 if (tmu_init(gd->fdt_blob) != TMU_STATUS_NORMAL) { 68 debug("%s: Failed to init TMU\n", __func__); 69 return -1; 70 } 71 boot_temp_check(); 72 #endif 73 74 #ifdef CONFIG_EXYNOS_SPI 75 spi_init(); 76 #endif 77 return exynos_init(); 78 } 79 80 int dram_init(void) 81 { 82 int i; 83 u32 addr; 84 85 for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) { 86 addr = CONFIG_SYS_SDRAM_BASE + (i * SDRAM_BANK_SIZE); 87 gd->ram_size += get_ram_size((long *)addr, SDRAM_BANK_SIZE); 88 } 89 return 0; 90 } 91 92 void dram_init_banksize(void) 93 { 94 int i; 95 u32 addr, size; 96 97 for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) { 98 addr = CONFIG_SYS_SDRAM_BASE + (i * SDRAM_BANK_SIZE); 99 size = get_ram_size((long *)addr, SDRAM_BANK_SIZE); 100 101 gd->bd->bi_dram[i].start = addr; 102 gd->bd->bi_dram[i].size = size; 103 } 104 } 105 106 static int board_uart_init(void) 107 { 108 int err, uart_id, ret = 0; 109 110 for (uart_id = PERIPH_ID_UART0; uart_id <= PERIPH_ID_UART3; uart_id++) { 111 err = exynos_pinmux_config(uart_id, PINMUX_FLAG_NONE); 112 if (err) { 113 debug("UART%d not configured\n", 114 (uart_id - PERIPH_ID_UART0)); 115 ret |= err; 116 } 117 } 118 return ret; 119 } 120 121 #ifdef CONFIG_BOARD_EARLY_INIT_F 122 int board_early_init_f(void) 123 { 124 int err; 125 126 err = board_uart_init(); 127 if (err) { 128 debug("UART init failed\n"); 129 return err; 130 } 131 132 #ifdef CONFIG_SYS_I2C_INIT_BOARD 133 board_i2c_init(gd->fdt_blob); 134 #endif 135 136 return err; 137 } 138 #endif 139 140 #if defined(CONFIG_POWER) 141 #ifdef CONFIG_POWER_MAX77686 142 static int pmic_reg_update(struct pmic *p, int reg, uint regval) 143 { 144 u32 val; 145 int ret = 0; 146 147 ret = pmic_reg_read(p, reg, &val); 148 if (ret) { 149 debug("%s: PMIC %d register read failed\n", __func__, reg); 150 return -1; 151 } 152 val |= regval; 153 ret = pmic_reg_write(p, reg, val); 154 if (ret) { 155 debug("%s: PMIC %d register write failed\n", __func__, reg); 156 return -1; 157 } 158 return 0; 159 } 160 161 static int max77686_init(void) 162 { 163 struct pmic *p; 164 165 if (pmic_init(I2C_PMIC)) 166 return -1; 167 168 p = pmic_get("MAX77686_PMIC"); 169 if (!p) 170 return -ENODEV; 171 172 if (pmic_probe(p)) 173 return -1; 174 175 if (pmic_reg_update(p, MAX77686_REG_PMIC_32KHZ, MAX77686_32KHCP_EN)) 176 return -1; 177 178 if (pmic_reg_update(p, MAX77686_REG_PMIC_BBAT, 179 MAX77686_BBCHOSTEN | MAX77686_BBCVS_3_5V)) 180 return -1; 181 182 /* VDD_MIF */ 183 if (pmic_reg_write(p, MAX77686_REG_PMIC_BUCK1OUT, 184 MAX77686_BUCK1OUT_1V)) { 185 debug("%s: PMIC %d register write failed\n", __func__, 186 MAX77686_REG_PMIC_BUCK1OUT); 187 return -1; 188 } 189 190 if (pmic_reg_update(p, MAX77686_REG_PMIC_BUCK1CRTL, 191 MAX77686_BUCK1CTRL_EN)) 192 return -1; 193 194 /* VDD_ARM */ 195 if (pmic_reg_write(p, MAX77686_REG_PMIC_BUCK2DVS1, 196 MAX77686_BUCK2DVS1_1_3V)) { 197 debug("%s: PMIC %d register write failed\n", __func__, 198 MAX77686_REG_PMIC_BUCK2DVS1); 199 return -1; 200 } 201 202 if (pmic_reg_update(p, MAX77686_REG_PMIC_BUCK2CTRL1, 203 MAX77686_BUCK2CTRL_ON)) 204 return -1; 205 206 /* VDD_INT */ 207 if (pmic_reg_write(p, MAX77686_REG_PMIC_BUCK3DVS1, 208 MAX77686_BUCK3DVS1_1_0125V)) { 209 debug("%s: PMIC %d register write failed\n", __func__, 210 MAX77686_REG_PMIC_BUCK3DVS1); 211 return -1; 212 } 213 214 if (pmic_reg_update(p, MAX77686_REG_PMIC_BUCK3CTRL, 215 MAX77686_BUCK3CTRL_ON)) 216 return -1; 217 218 /* VDD_G3D */ 219 if (pmic_reg_write(p, MAX77686_REG_PMIC_BUCK4DVS1, 220 MAX77686_BUCK4DVS1_1_2V)) { 221 debug("%s: PMIC %d register write failed\n", __func__, 222 MAX77686_REG_PMIC_BUCK4DVS1); 223 return -1; 224 } 225 226 if (pmic_reg_update(p, MAX77686_REG_PMIC_BUCK4CTRL1, 227 MAX77686_BUCK3CTRL_ON)) 228 return -1; 229 230 /* VDD_LDO2 */ 231 if (pmic_reg_update(p, MAX77686_REG_PMIC_LDO2CTRL1, 232 MAX77686_LD02CTRL1_1_5V | EN_LDO)) 233 return -1; 234 235 /* VDD_LDO3 */ 236 if (pmic_reg_update(p, MAX77686_REG_PMIC_LDO3CTRL1, 237 MAX77686_LD03CTRL1_1_8V | EN_LDO)) 238 return -1; 239 240 /* VDD_LDO5 */ 241 if (pmic_reg_update(p, MAX77686_REG_PMIC_LDO5CTRL1, 242 MAX77686_LD05CTRL1_1_8V | EN_LDO)) 243 return -1; 244 245 /* VDD_LDO10 */ 246 if (pmic_reg_update(p, MAX77686_REG_PMIC_LDO10CTRL1, 247 MAX77686_LD10CTRL1_1_8V | EN_LDO)) 248 return -1; 249 250 return 0; 251 } 252 #endif 253 254 int power_init_board(void) 255 { 256 int ret = 0; 257 258 set_ps_hold_ctrl(); 259 260 #ifdef CONFIG_POWER_MAX77686 261 ret = max77686_init(); 262 #endif 263 264 return ret; 265 } 266 #endif 267 268 #ifdef CONFIG_OF_CONTROL 269 static int decode_sromc(const void *blob, struct fdt_sromc *config) 270 { 271 int err; 272 int node; 273 274 node = fdtdec_next_compatible(blob, 0, COMPAT_SAMSUNG_EXYNOS5_SROMC); 275 if (node < 0) { 276 debug("Could not find SROMC node\n"); 277 return node; 278 } 279 280 config->bank = fdtdec_get_int(blob, node, "bank", 0); 281 config->width = fdtdec_get_int(blob, node, "width", 2); 282 283 err = fdtdec_get_int_array(blob, node, "srom-timing", config->timing, 284 FDT_SROM_TIMING_COUNT); 285 if (err < 0) { 286 debug("Could not decode SROMC configuration Error: %s\n", 287 fdt_strerror(err)); 288 return -FDT_ERR_NOTFOUND; 289 } 290 return 0; 291 } 292 293 int board_eth_init(bd_t *bis) 294 { 295 #ifdef CONFIG_SMC911X 296 u32 smc_bw_conf, smc_bc_conf; 297 struct fdt_sromc config; 298 fdt_addr_t base_addr; 299 int node; 300 301 node = decode_sromc(gd->fdt_blob, &config); 302 if (node < 0) { 303 debug("%s: Could not find sromc configuration\n", __func__); 304 return 0; 305 } 306 node = fdtdec_next_compatible(gd->fdt_blob, node, COMPAT_SMSC_LAN9215); 307 if (node < 0) { 308 debug("%s: Could not find lan9215 configuration\n", __func__); 309 return 0; 310 } 311 312 /* We now have a node, so any problems from now on are errors */ 313 base_addr = fdtdec_get_addr(gd->fdt_blob, node, "reg"); 314 if (base_addr == FDT_ADDR_T_NONE) { 315 debug("%s: Could not find lan9215 address\n", __func__); 316 return -1; 317 } 318 319 /* Ethernet needs data bus width of 16 bits */ 320 if (config.width != 2) { 321 debug("%s: Unsupported bus width %d\n", __func__, 322 config.width); 323 return -1; 324 } 325 smc_bw_conf = SROMC_DATA16_WIDTH(config.bank) 326 | SROMC_BYTE_ENABLE(config.bank); 327 328 smc_bc_conf = SROMC_BC_TACS(config.timing[FDT_SROM_TACS]) | 329 SROMC_BC_TCOS(config.timing[FDT_SROM_TCOS]) | 330 SROMC_BC_TACC(config.timing[FDT_SROM_TACC]) | 331 SROMC_BC_TCOH(config.timing[FDT_SROM_TCOH]) | 332 SROMC_BC_TAH(config.timing[FDT_SROM_TAH]) | 333 SROMC_BC_TACP(config.timing[FDT_SROM_TACP]) | 334 SROMC_BC_PMC(config.timing[FDT_SROM_PMC]); 335 336 /* Select and configure the SROMC bank */ 337 exynos_pinmux_config(PERIPH_ID_SROMC, config.bank); 338 s5p_config_sromc(config.bank, smc_bw_conf, smc_bc_conf); 339 return smc911x_initialize(0, base_addr); 340 #endif 341 return 0; 342 } 343 344 #ifdef CONFIG_GENERIC_MMC 345 int board_mmc_init(bd_t *bis) 346 { 347 int ret; 348 349 /* dwmmc initializattion for available channels */ 350 ret = exynos_dwmmc_init(gd->fdt_blob); 351 if (ret) 352 debug("dwmmc init failed\n"); 353 354 return ret; 355 } 356 #endif 357 #endif 358 359 #ifdef CONFIG_BOARD_LATE_INIT 360 int board_late_init(void) 361 { 362 stdio_print_current_devices(); 363 364 if (cros_ec_get_error()) { 365 /* Force console on */ 366 gd->flags &= ~GD_FLG_SILENT; 367 368 printf("cros-ec communications failure %d\n", 369 cros_ec_get_error()); 370 puts("\nPlease reset with Power+Refresh\n\n"); 371 panic("Cannot init cros-ec device"); 372 return -1; 373 } 374 return 0; 375 } 376 #endif 377 378 int arch_early_init_r(void) 379 { 380 #ifdef CONFIG_CROS_EC 381 if (cros_ec_board_init()) { 382 printf("%s: Failed to init EC\n", __func__); 383 return 0; 384 } 385 #endif 386 387 return 0; 388 } 389