1 /* 2 * (C) Copyright 2013 SAMSUNG Electronics 3 * Rajeshwari Shinde <rajeshwari.s@samsung.com> 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8 #include <common.h> 9 #include <cros_ec.h> 10 #include <errno.h> 11 #include <fdtdec.h> 12 #include <spi.h> 13 #include <tmu.h> 14 #include <netdev.h> 15 #include <asm/io.h> 16 #include <asm/gpio.h> 17 #include <asm/arch/board.h> 18 #include <asm/arch/cpu.h> 19 #include <asm/arch/dwmmc.h> 20 #include <asm/arch/mmc.h> 21 #include <asm/arch/pinmux.h> 22 #include <asm/arch/power.h> 23 #include <asm/arch/system.h> 24 #include <asm/arch/sromc.h> 25 #include <lcd.h> 26 #include <i2c.h> 27 #include <usb.h> 28 #include <dwc3-uboot.h> 29 #include <samsung/misc.h> 30 #include <dm/pinctrl.h> 31 #include <dm.h> 32 33 DECLARE_GLOBAL_DATA_PTR; 34 35 __weak int exynos_early_init_f(void) 36 { 37 return 0; 38 } 39 40 __weak int exynos_power_init(void) 41 { 42 return 0; 43 } 44 45 #if defined CONFIG_EXYNOS_TMU 46 /* Boot Time Thermal Analysis for SoC temperature threshold breach */ 47 static void boot_temp_check(void) 48 { 49 int temp; 50 51 switch (tmu_monitor(&temp)) { 52 case TMU_STATUS_NORMAL: 53 break; 54 case TMU_STATUS_TRIPPED: 55 /* 56 * Status TRIPPED ans WARNING means corresponding threshold 57 * breach 58 */ 59 puts("EXYNOS_TMU: TRIPPING! Device power going down ...\n"); 60 set_ps_hold_ctrl(); 61 hang(); 62 break; 63 case TMU_STATUS_WARNING: 64 puts("EXYNOS_TMU: WARNING! Temperature very high\n"); 65 break; 66 case TMU_STATUS_INIT: 67 /* 68 * TMU_STATUS_INIT means something is wrong with temperature 69 * sensing and TMU status was changed back from NORMAL to INIT. 70 */ 71 puts("EXYNOS_TMU: WARNING! Temperature sensing not done\n"); 72 break; 73 default: 74 debug("EXYNOS_TMU: Unknown TMU state\n"); 75 } 76 } 77 #endif 78 79 int board_init(void) 80 { 81 gd->bd->bi_boot_params = (PHYS_SDRAM_1 + 0x100UL); 82 #if defined CONFIG_EXYNOS_TMU 83 if (tmu_init(gd->fdt_blob) != TMU_STATUS_NORMAL) { 84 debug("%s: Failed to init TMU\n", __func__); 85 return -1; 86 } 87 boot_temp_check(); 88 #endif 89 #ifdef CONFIG_TZSW_RESERVED_DRAM_SIZE 90 /* The last few MB of memory can be reserved for secure firmware */ 91 ulong size = CONFIG_TZSW_RESERVED_DRAM_SIZE; 92 93 gd->ram_size -= size; 94 gd->bd->bi_dram[CONFIG_NR_DRAM_BANKS - 1].size -= size; 95 #endif 96 return exynos_init(); 97 } 98 99 int dram_init(void) 100 { 101 unsigned int i; 102 unsigned long addr; 103 104 for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) { 105 addr = CONFIG_SYS_SDRAM_BASE + (i * SDRAM_BANK_SIZE); 106 gd->ram_size += get_ram_size((long *)addr, SDRAM_BANK_SIZE); 107 } 108 return 0; 109 } 110 111 void dram_init_banksize(void) 112 { 113 unsigned int i; 114 unsigned long addr, size; 115 116 for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) { 117 addr = CONFIG_SYS_SDRAM_BASE + (i * SDRAM_BANK_SIZE); 118 size = get_ram_size((long *)addr, SDRAM_BANK_SIZE); 119 120 gd->bd->bi_dram[i].start = addr; 121 gd->bd->bi_dram[i].size = size; 122 } 123 } 124 125 static int board_uart_init(void) 126 { 127 #ifndef CONFIG_PINCTRL_EXYNOS 128 int err, uart_id, ret = 0; 129 130 for (uart_id = PERIPH_ID_UART0; uart_id <= PERIPH_ID_UART3; uart_id++) { 131 err = exynos_pinmux_config(uart_id, PINMUX_FLAG_NONE); 132 if (err) { 133 debug("UART%d not configured\n", 134 (uart_id - PERIPH_ID_UART0)); 135 ret |= err; 136 } 137 } 138 return ret; 139 #else 140 return 0; 141 #endif 142 } 143 144 #ifdef CONFIG_BOARD_EARLY_INIT_F 145 int board_early_init_f(void) 146 { 147 int err; 148 #ifdef CONFIG_BOARD_TYPES 149 set_board_type(); 150 #endif 151 err = board_uart_init(); 152 if (err) { 153 debug("UART init failed\n"); 154 return err; 155 } 156 157 #ifdef CONFIG_SYS_I2C_INIT_BOARD 158 board_i2c_init(gd->fdt_blob); 159 #endif 160 161 #if defined(CONFIG_EXYNOS_FB) 162 /* 163 * board_init_f(arch/arm/lib/board.c) calls lcd_setmem() which needs 164 * panel_info.vl_col, panel_info.vl_row and panel_info.vl_bpix, 165 * to reserve frame-buffer memory at a very early stage. So, we need 166 * to fill panel_info.vl_col, panel_info.vl_row and panel_info.vl_bpix 167 * before lcd_setmem() is called. 168 */ 169 err = exynos_lcd_early_init(gd->fdt_blob); 170 if (err) { 171 debug("LCD early init failed\n"); 172 return err; 173 } 174 #endif 175 176 return exynos_early_init_f(); 177 } 178 #endif 179 180 #if defined(CONFIG_POWER) || defined(CONFIG_DM_PMIC) 181 int power_init_board(void) 182 { 183 set_ps_hold_ctrl(); 184 185 return exynos_power_init(); 186 } 187 #endif 188 189 #ifdef CONFIG_SMC911X 190 static int decode_sromc(const void *blob, struct fdt_sromc *config) 191 { 192 int err; 193 int node; 194 195 node = fdtdec_next_compatible(blob, 0, COMPAT_SAMSUNG_EXYNOS5_SROMC); 196 if (node < 0) { 197 debug("Could not find SROMC node\n"); 198 return node; 199 } 200 201 config->bank = fdtdec_get_int(blob, node, "bank", 0); 202 config->width = fdtdec_get_int(blob, node, "width", 2); 203 204 err = fdtdec_get_int_array(blob, node, "srom-timing", config->timing, 205 FDT_SROM_TIMING_COUNT); 206 if (err < 0) { 207 debug("Could not decode SROMC configuration Error: %s\n", 208 fdt_strerror(err)); 209 return -FDT_ERR_NOTFOUND; 210 } 211 return 0; 212 } 213 #endif 214 215 int board_eth_init(bd_t *bis) 216 { 217 #ifdef CONFIG_SMC911X 218 u32 smc_bw_conf, smc_bc_conf; 219 struct fdt_sromc config; 220 fdt_addr_t base_addr; 221 int node; 222 223 node = decode_sromc(gd->fdt_blob, &config); 224 if (node < 0) { 225 debug("%s: Could not find sromc configuration\n", __func__); 226 return 0; 227 } 228 node = fdtdec_next_compatible(gd->fdt_blob, node, COMPAT_SMSC_LAN9215); 229 if (node < 0) { 230 debug("%s: Could not find lan9215 configuration\n", __func__); 231 return 0; 232 } 233 234 /* We now have a node, so any problems from now on are errors */ 235 base_addr = fdtdec_get_addr(gd->fdt_blob, node, "reg"); 236 if (base_addr == FDT_ADDR_T_NONE) { 237 debug("%s: Could not find lan9215 address\n", __func__); 238 return -1; 239 } 240 241 /* Ethernet needs data bus width of 16 bits */ 242 if (config.width != 2) { 243 debug("%s: Unsupported bus width %d\n", __func__, 244 config.width); 245 return -1; 246 } 247 smc_bw_conf = SROMC_DATA16_WIDTH(config.bank) 248 | SROMC_BYTE_ENABLE(config.bank); 249 250 smc_bc_conf = SROMC_BC_TACS(config.timing[FDT_SROM_TACS]) | 251 SROMC_BC_TCOS(config.timing[FDT_SROM_TCOS]) | 252 SROMC_BC_TACC(config.timing[FDT_SROM_TACC]) | 253 SROMC_BC_TCOH(config.timing[FDT_SROM_TCOH]) | 254 SROMC_BC_TAH(config.timing[FDT_SROM_TAH]) | 255 SROMC_BC_TACP(config.timing[FDT_SROM_TACP]) | 256 SROMC_BC_PMC(config.timing[FDT_SROM_PMC]); 257 258 /* Select and configure the SROMC bank */ 259 exynos_pinmux_config(PERIPH_ID_SROMC, config.bank); 260 s5p_config_sromc(config.bank, smc_bw_conf, smc_bc_conf); 261 return smc911x_initialize(0, base_addr); 262 #endif 263 return 0; 264 } 265 266 #ifdef CONFIG_GENERIC_MMC 267 static int init_mmc(void) 268 { 269 #ifdef CONFIG_SDHCI 270 return exynos_mmc_init(gd->fdt_blob); 271 #else 272 return 0; 273 #endif 274 } 275 276 static int init_dwmmc(void) 277 { 278 #ifdef CONFIG_DWMMC 279 return exynos_dwmmc_init(gd->fdt_blob); 280 #else 281 return 0; 282 #endif 283 } 284 285 int board_mmc_init(bd_t *bis) 286 { 287 int ret; 288 289 if (get_boot_mode() == BOOT_MODE_SD) { 290 ret = init_mmc(); 291 ret |= init_dwmmc(); 292 } else { 293 ret = init_dwmmc(); 294 ret |= init_mmc(); 295 } 296 297 if (ret) 298 debug("mmc init failed\n"); 299 300 return ret; 301 } 302 #endif 303 304 #ifdef CONFIG_DISPLAY_BOARDINFO 305 int checkboard(void) 306 { 307 const char *board_info; 308 309 board_info = fdt_getprop(gd->fdt_blob, 0, "model", NULL); 310 printf("Board: %s\n", board_info ? board_info : "unknown"); 311 #ifdef CONFIG_BOARD_TYPES 312 board_info = get_board_type(); 313 if (board_info) 314 printf("Type: %s\n", board_info); 315 #endif 316 return 0; 317 } 318 #endif 319 320 #ifdef CONFIG_BOARD_LATE_INIT 321 int board_late_init(void) 322 { 323 stdio_print_current_devices(); 324 325 if (cros_ec_get_error()) { 326 /* Force console on */ 327 gd->flags &= ~GD_FLG_SILENT; 328 329 printf("cros-ec communications failure %d\n", 330 cros_ec_get_error()); 331 puts("\nPlease reset with Power+Refresh\n\n"); 332 panic("Cannot init cros-ec device"); 333 return -1; 334 } 335 return 0; 336 } 337 #endif 338 339 #ifdef CONFIG_MISC_INIT_R 340 int misc_init_r(void) 341 { 342 #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG 343 set_board_info(); 344 #endif 345 #ifdef CONFIG_LCD_MENU 346 keys_init(); 347 check_boot_mode(); 348 #endif 349 #ifdef CONFIG_CMD_BMP 350 if (panel_info.logo_on) 351 draw_logo(); 352 #endif 353 return 0; 354 } 355 #endif 356 357 void reset_misc(void) 358 { 359 struct gpio_desc gpio = {}; 360 int node; 361 362 node = fdt_node_offset_by_compatible(gd->fdt_blob, 0, 363 "samsung,emmc-reset"); 364 if (node < 0) 365 return; 366 367 gpio_request_by_name_nodev(gd->fdt_blob, node, "reset-gpio", 0, &gpio, 368 GPIOD_IS_OUT); 369 370 if (dm_gpio_is_valid(&gpio)) { 371 /* 372 * Reset eMMC 373 * 374 * FIXME: Need to optimize delay time. Minimum 1usec pulse is 375 * required by 'JEDEC Standard No.84-A441' (eMMC) 376 * document but real delay time is expected to greater 377 * than 1usec. 378 */ 379 dm_gpio_set_value(&gpio, 0); 380 mdelay(10); 381 dm_gpio_set_value(&gpio, 1); 382 } 383 } 384 385 int board_usb_cleanup(int index, enum usb_init_type init) 386 { 387 #ifdef CONFIG_USB_DWC3 388 dwc3_uboot_exit(index); 389 #endif 390 return 0; 391 } 392