1 /* 2 * (C) Copyright 2013 SAMSUNG Electronics 3 * Rajeshwari Shinde <rajeshwari.s@samsung.com> 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8 #include <common.h> 9 #include <cros_ec.h> 10 #include <errno.h> 11 #include <fdtdec.h> 12 #include <spi.h> 13 #include <tmu.h> 14 #include <netdev.h> 15 #include <asm/io.h> 16 #include <asm/gpio.h> 17 #include <asm/arch/board.h> 18 #include <asm/arch/cpu.h> 19 #include <asm/arch/dwmmc.h> 20 #include <asm/arch/mmc.h> 21 #include <asm/arch/pinmux.h> 22 #include <asm/arch/power.h> 23 #include <asm/arch/system.h> 24 #include <power/pmic.h> 25 #include <asm/arch/sromc.h> 26 #include <lcd.h> 27 #include <samsung/misc.h> 28 29 DECLARE_GLOBAL_DATA_PTR; 30 31 __weak int exynos_early_init_f(void) 32 { 33 return 0; 34 } 35 36 __weak int exynos_power_init(void) 37 { 38 return 0; 39 } 40 41 #if defined CONFIG_EXYNOS_TMU 42 /* Boot Time Thermal Analysis for SoC temperature threshold breach */ 43 static void boot_temp_check(void) 44 { 45 int temp; 46 47 switch (tmu_monitor(&temp)) { 48 case TMU_STATUS_NORMAL: 49 break; 50 case TMU_STATUS_TRIPPED: 51 /* 52 * Status TRIPPED ans WARNING means corresponding threshold 53 * breach 54 */ 55 puts("EXYNOS_TMU: TRIPPING! Device power going down ...\n"); 56 set_ps_hold_ctrl(); 57 hang(); 58 break; 59 case TMU_STATUS_WARNING: 60 puts("EXYNOS_TMU: WARNING! Temperature very high\n"); 61 break; 62 case TMU_STATUS_INIT: 63 /* 64 * TMU_STATUS_INIT means something is wrong with temperature 65 * sensing and TMU status was changed back from NORMAL to INIT. 66 */ 67 puts("EXYNOS_TMU: WARNING! Temperature sensing not done\n"); 68 break; 69 default: 70 debug("EXYNOS_TMU: Unknown TMU state\n"); 71 } 72 } 73 #endif 74 75 int board_init(void) 76 { 77 gd->bd->bi_boot_params = (PHYS_SDRAM_1 + 0x100UL); 78 #if defined CONFIG_EXYNOS_TMU 79 if (tmu_init(gd->fdt_blob) != TMU_STATUS_NORMAL) { 80 debug("%s: Failed to init TMU\n", __func__); 81 return -1; 82 } 83 boot_temp_check(); 84 #endif 85 #ifdef CONFIG_TZSW_RESERVED_DRAM_SIZE 86 /* The last few MB of memory can be reserved for secure firmware */ 87 ulong size = CONFIG_TZSW_RESERVED_DRAM_SIZE; 88 89 gd->ram_size -= size; 90 gd->bd->bi_dram[CONFIG_NR_DRAM_BANKS - 1].size -= size; 91 #endif 92 return exynos_init(); 93 } 94 95 int dram_init(void) 96 { 97 unsigned int i; 98 u32 addr; 99 100 for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) { 101 addr = CONFIG_SYS_SDRAM_BASE + (i * SDRAM_BANK_SIZE); 102 gd->ram_size += get_ram_size((long *)addr, SDRAM_BANK_SIZE); 103 } 104 return 0; 105 } 106 107 void dram_init_banksize(void) 108 { 109 unsigned int i; 110 u32 addr, size; 111 112 for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) { 113 addr = CONFIG_SYS_SDRAM_BASE + (i * SDRAM_BANK_SIZE); 114 size = get_ram_size((long *)addr, SDRAM_BANK_SIZE); 115 116 gd->bd->bi_dram[i].start = addr; 117 gd->bd->bi_dram[i].size = size; 118 } 119 } 120 121 static int board_uart_init(void) 122 { 123 int err, uart_id, ret = 0; 124 125 for (uart_id = PERIPH_ID_UART0; uart_id <= PERIPH_ID_UART3; uart_id++) { 126 err = exynos_pinmux_config(uart_id, PINMUX_FLAG_NONE); 127 if (err) { 128 debug("UART%d not configured\n", 129 (uart_id - PERIPH_ID_UART0)); 130 ret |= err; 131 } 132 } 133 return ret; 134 } 135 136 #ifdef CONFIG_BOARD_EARLY_INIT_F 137 int board_early_init_f(void) 138 { 139 int err; 140 #ifdef CONFIG_BOARD_TYPES 141 set_board_type(); 142 #endif 143 err = board_uart_init(); 144 if (err) { 145 debug("UART init failed\n"); 146 return err; 147 } 148 149 #ifdef CONFIG_SYS_I2C_INIT_BOARD 150 board_i2c_init(gd->fdt_blob); 151 #endif 152 153 #if defined(CONFIG_OF_CONTROL) && defined(CONFIG_EXYNOS_FB) 154 /* 155 * board_init_f(arch/arm/lib/board.c) calls lcd_setmem() which needs 156 * panel_info.vl_col, panel_info.vl_row and panel_info.vl_bpix, to reserve 157 * FB memory at a very early stage. So, we need to fill panel_info.vl_col, 158 * panel_info.vl_row and panel_info.vl_bpix before lcd_setmem() is called. 159 */ 160 err = exynos_lcd_early_init(gd->fdt_blob); 161 if (err) { 162 debug("LCD early init failed\n"); 163 return err; 164 } 165 #endif 166 167 return exynos_early_init_f(); 168 } 169 #endif 170 171 #if defined(CONFIG_POWER) 172 int power_init_board(void) 173 { 174 set_ps_hold_ctrl(); 175 176 return exynos_power_init(); 177 } 178 #endif 179 180 #ifdef CONFIG_OF_CONTROL 181 #ifdef CONFIG_SMC911X 182 static int decode_sromc(const void *blob, struct fdt_sromc *config) 183 { 184 int err; 185 int node; 186 187 node = fdtdec_next_compatible(blob, 0, COMPAT_SAMSUNG_EXYNOS5_SROMC); 188 if (node < 0) { 189 debug("Could not find SROMC node\n"); 190 return node; 191 } 192 193 config->bank = fdtdec_get_int(blob, node, "bank", 0); 194 config->width = fdtdec_get_int(blob, node, "width", 2); 195 196 err = fdtdec_get_int_array(blob, node, "srom-timing", config->timing, 197 FDT_SROM_TIMING_COUNT); 198 if (err < 0) { 199 debug("Could not decode SROMC configuration Error: %s\n", 200 fdt_strerror(err)); 201 return -FDT_ERR_NOTFOUND; 202 } 203 return 0; 204 } 205 #endif 206 207 int board_eth_init(bd_t *bis) 208 { 209 #ifdef CONFIG_SMC911X 210 u32 smc_bw_conf, smc_bc_conf; 211 struct fdt_sromc config; 212 fdt_addr_t base_addr; 213 int node; 214 215 node = decode_sromc(gd->fdt_blob, &config); 216 if (node < 0) { 217 debug("%s: Could not find sromc configuration\n", __func__); 218 return 0; 219 } 220 node = fdtdec_next_compatible(gd->fdt_blob, node, COMPAT_SMSC_LAN9215); 221 if (node < 0) { 222 debug("%s: Could not find lan9215 configuration\n", __func__); 223 return 0; 224 } 225 226 /* We now have a node, so any problems from now on are errors */ 227 base_addr = fdtdec_get_addr(gd->fdt_blob, node, "reg"); 228 if (base_addr == FDT_ADDR_T_NONE) { 229 debug("%s: Could not find lan9215 address\n", __func__); 230 return -1; 231 } 232 233 /* Ethernet needs data bus width of 16 bits */ 234 if (config.width != 2) { 235 debug("%s: Unsupported bus width %d\n", __func__, 236 config.width); 237 return -1; 238 } 239 smc_bw_conf = SROMC_DATA16_WIDTH(config.bank) 240 | SROMC_BYTE_ENABLE(config.bank); 241 242 smc_bc_conf = SROMC_BC_TACS(config.timing[FDT_SROM_TACS]) | 243 SROMC_BC_TCOS(config.timing[FDT_SROM_TCOS]) | 244 SROMC_BC_TACC(config.timing[FDT_SROM_TACC]) | 245 SROMC_BC_TCOH(config.timing[FDT_SROM_TCOH]) | 246 SROMC_BC_TAH(config.timing[FDT_SROM_TAH]) | 247 SROMC_BC_TACP(config.timing[FDT_SROM_TACP]) | 248 SROMC_BC_PMC(config.timing[FDT_SROM_PMC]); 249 250 /* Select and configure the SROMC bank */ 251 exynos_pinmux_config(PERIPH_ID_SROMC, config.bank); 252 s5p_config_sromc(config.bank, smc_bw_conf, smc_bc_conf); 253 return smc911x_initialize(0, base_addr); 254 #endif 255 return 0; 256 } 257 258 #ifdef CONFIG_GENERIC_MMC 259 static int init_mmc(void) 260 { 261 #ifdef CONFIG_SDHCI 262 return exynos_mmc_init(gd->fdt_blob); 263 #else 264 return 0; 265 #endif 266 } 267 268 static int init_dwmmc(void) 269 { 270 #ifdef CONFIG_DWMMC 271 return exynos_dwmmc_init(gd->fdt_blob); 272 #else 273 return 0; 274 #endif 275 } 276 277 int board_mmc_init(bd_t *bis) 278 { 279 int ret; 280 281 if (get_boot_mode() == BOOT_MODE_SD) { 282 ret = init_mmc(); 283 ret |= init_dwmmc(); 284 } else { 285 ret = init_dwmmc(); 286 ret |= init_mmc(); 287 } 288 289 if (ret) 290 debug("mmc init failed\n"); 291 292 return ret; 293 } 294 #endif 295 296 #ifdef CONFIG_DISPLAY_BOARDINFO 297 int checkboard(void) 298 { 299 const char *board_info; 300 301 board_info = fdt_getprop(gd->fdt_blob, 0, "model", NULL); 302 printf("Board: %s\n", board_info ? board_info : "unknown"); 303 #ifdef CONFIG_BOARD_TYPES 304 board_info = get_board_type(); 305 306 printf("Model: %s\n", board_info ? board_info : "unknown"); 307 #endif 308 return 0; 309 } 310 #endif 311 #endif /* CONFIG_OF_CONTROL */ 312 313 #ifdef CONFIG_BOARD_LATE_INIT 314 int board_late_init(void) 315 { 316 stdio_print_current_devices(); 317 318 if (cros_ec_get_error()) { 319 /* Force console on */ 320 gd->flags &= ~GD_FLG_SILENT; 321 322 printf("cros-ec communications failure %d\n", 323 cros_ec_get_error()); 324 puts("\nPlease reset with Power+Refresh\n\n"); 325 panic("Cannot init cros-ec device"); 326 return -1; 327 } 328 return 0; 329 } 330 #endif 331 332 int arch_early_init_r(void) 333 { 334 #ifdef CONFIG_CROS_EC 335 if (cros_ec_board_init()) { 336 printf("%s: Failed to init EC\n", __func__); 337 return 0; 338 } 339 #endif 340 341 return 0; 342 } 343 344 #ifdef CONFIG_MISC_INIT_R 345 int misc_init_r(void) 346 { 347 #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG 348 set_board_info(); 349 #endif 350 #ifdef CONFIG_LCD_MENU 351 keys_init(); 352 check_boot_mode(); 353 #endif 354 #ifdef CONFIG_CMD_BMP 355 if (panel_info.logo_on) 356 draw_logo(); 357 #endif 358 return 0; 359 } 360 #endif 361 362 void reset_misc(void) 363 { 364 struct gpio_desc gpio = {}; 365 int node; 366 367 node = fdt_node_offset_by_compatible(gd->fdt_blob, 0, 368 "samsung,emmc-reset"); 369 if (node < 0) 370 return; 371 372 gpio_request_by_name_nodev(gd->fdt_blob, node, "reset-gpio", 0, &gpio, 373 GPIOD_IS_OUT); 374 375 if (dm_gpio_is_valid(&gpio)) { 376 /* 377 * Reset eMMC 378 * 379 * FIXME: Need to optimize delay time. Minimum 1usec pulse is 380 * required by 'JEDEC Standard No.84-A441' (eMMC) 381 * document but real delay time is expected to greater 382 * than 1usec. 383 */ 384 dm_gpio_set_value(&gpio, 0); 385 mdelay(10); 386 dm_gpio_set_value(&gpio, 1); 387 } 388 } 389