1 /* 2 * (C) Copyright 2010 3 * Ilko Iliev <iliev@ronetix.at> 4 * Asen Dimov <dimov@ronetix.at> 5 * Ronetix GmbH <www.ronetix.at> 6 * 7 * (C) Copyright 2007-2008 8 * Stelian Pop <stelian@popies.net> 9 * Lead Tech Design <www.leadtechdesign.com> 10 * 11 * SPDX-License-Identifier: GPL-2.0+ 12 */ 13 14 #include <common.h> 15 #include <linux/sizes.h> 16 #include <asm/io.h> 17 #include <asm/gpio.h> 18 #include <asm/arch/at91sam9_smc.h> 19 #include <asm/arch/at91_common.h> 20 #include <asm/arch/at91_pmc.h> 21 #include <asm/arch/at91_rstc.h> 22 #include <asm/arch/at91_matrix.h> 23 #include <asm/arch/gpio.h> 24 #include <asm/arch/clk.h> 25 #if defined(CONFIG_RESET_PHY_R) && defined(CONFIG_MACB) 26 #include <net.h> 27 #endif 28 #include <netdev.h> 29 30 DECLARE_GLOBAL_DATA_PTR; 31 32 /* 33 * Miscelaneous platform dependent initialisations 34 */ 35 36 #ifdef CONFIG_CMD_NAND 37 static void pm9g45_nand_hw_init(void) 38 { 39 unsigned long csa; 40 struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC; 41 struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX; 42 struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; 43 44 /* Enable CS3 */ 45 csa = readl(&matrix->ccr[6]) | AT91_MATRIX_CSA_EBI_CS3A; 46 writel(csa, &matrix->ccr[6]); 47 48 /* Configure SMC CS3 for NAND/SmartMedia */ 49 writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(0) | 50 AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(0), 51 &smc->cs[3].setup); 52 53 writel(AT91_SMC_PULSE_NWE(4) | AT91_SMC_PULSE_NCS_WR(3) | 54 AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(2), 55 &smc->cs[3].pulse); 56 57 writel(AT91_SMC_CYCLE_NWE(7) | AT91_SMC_CYCLE_NRD(4), 58 &smc->cs[3].cycle); 59 60 writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE | 61 AT91_SMC_MODE_EXNW_DISABLE | 62 AT91_SMC_MODE_DBW_8 | 63 AT91_SMC_MODE_TDF_CYCLE(3), 64 &smc->cs[3].mode); 65 66 writel(1 << ATMEL_ID_PIOC, &pmc->pcer); 67 68 #ifdef CONFIG_SYS_NAND_READY_PIN 69 /* Configure RDY/BSY */ 70 gpio_direction_input(CONFIG_SYS_NAND_READY_PIN); 71 #endif 72 73 /* Enable NandFlash */ 74 gpio_direction_output(CONFIG_SYS_NAND_ENABLE_PIN, 1); 75 } 76 #endif 77 78 #ifdef CONFIG_MACB 79 static void pm9g45_macb_hw_init(void) 80 { 81 struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; 82 83 /* 84 * PD2 enables the 50MHz oscillator for Ethernet PHY 85 * 1 - enable 86 * 0 - disable 87 */ 88 at91_set_pio_output(AT91_PIO_PORTD, 2, 1); 89 at91_set_pio_value(AT91_PIO_PORTD, 2, 1); /* 1- enable, 0 - disable */ 90 91 /* Enable clock */ 92 writel(1 << ATMEL_ID_EMAC, &pmc->pcer); 93 94 /* 95 * Disable pull-up on: 96 * RXDV (PA15) => PHY normal mode (not Test mode) 97 * ERX0 (PA12) => PHY ADDR0 98 * ERX1 (PA13) => PHY ADDR1 => PHYADDR = 0x0 99 * 100 * PHY has internal pull-down 101 */ 102 at91_set_pio_pullup(AT91_PIO_PORTA, 15, 0); 103 at91_set_pio_pullup(AT91_PIO_PORTA, 12, 0); 104 at91_set_pio_pullup(AT91_PIO_PORTA, 13, 0); 105 106 /* Re-enable pull-up */ 107 at91_set_pio_pullup(AT91_PIO_PORTA, 15, 1); 108 at91_set_pio_pullup(AT91_PIO_PORTA, 12, 1); 109 at91_set_pio_pullup(AT91_PIO_PORTA, 13, 1); 110 111 at91_macb_hw_init(); 112 } 113 #endif 114 115 int board_early_init_f(void) 116 { 117 struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; 118 119 /* Enable clocks for all PIOs */ 120 writel((1 << ATMEL_ID_PIOA) | 121 (1 << ATMEL_ID_PIOB) | 122 (1 << ATMEL_ID_PIOC) | 123 (1 << ATMEL_ID_PIODE), &pmc->pcer); 124 125 at91_seriald_hw_init(); 126 127 return 0; 128 } 129 130 int board_init(void) 131 { 132 /* arch number of AT91SAM9M10G45EK-Board */ 133 gd->bd->bi_arch_number = MACH_TYPE_PM9G45; 134 /* adress of boot parameters */ 135 gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; 136 137 #ifdef CONFIG_CMD_NAND 138 pm9g45_nand_hw_init(); 139 #endif 140 141 #ifdef CONFIG_MACB 142 pm9g45_macb_hw_init(); 143 #endif 144 return 0; 145 } 146 147 int dram_init(void) 148 { 149 /* dram_init must store complete ramsize in gd->ram_size */ 150 gd->ram_size = get_ram_size((void *)PHYS_SDRAM, 151 PHYS_SDRAM_SIZE); 152 return 0; 153 } 154 155 void dram_init_banksize(void) 156 { 157 gd->bd->bi_dram[0].start = PHYS_SDRAM; 158 gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE; 159 } 160 161 #ifdef CONFIG_RESET_PHY_R 162 void reset_phy(void) 163 { 164 #ifdef CONFIG_MACB 165 /* 166 * Initialize ethernet HW addr prior to starting Linux, 167 * needed for nfsroot 168 */ 169 eth_init(gd->bd); 170 #endif 171 } 172 #endif 173 174 int board_eth_init(bd_t *bis) 175 { 176 int rc = 0; 177 #ifdef CONFIG_MACB 178 rc = macb_eth_initialize(0, (void *)ATMEL_BASE_EMAC, 0x01); 179 #endif 180 return rc; 181 } 182