1 /* 2 * (C) Copyright 2007-2008 3 * Stelian Pop <stelian@popies.net> 4 * Lead Tech Design <www.leadtechdesign.com> 5 * Copyright (C) 2008 Ronetix Ilko Iliev (www.ronetix.at) 6 * Copyright (C) 2009 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> 7 * 8 * SPDX-License-Identifier: GPL-2.0+ 9 */ 10 11 #include <common.h> 12 #include <linux/sizes.h> 13 #include <asm/io.h> 14 #include <asm/gpio.h> 15 #include <asm/arch/at91sam9_smc.h> 16 #include <asm/arch/at91_common.h> 17 #include <asm/arch/at91_rstc.h> 18 #include <asm/arch/at91_matrix.h> 19 #include <asm/arch/clk.h> 20 #include <asm/arch/gpio.h> 21 #include <lcd.h> 22 #include <atmel_lcdc.h> 23 #include <dataflash.h> 24 #if defined(CONFIG_RESET_PHY_R) && defined(CONFIG_MACB) 25 #include <net.h> 26 #endif 27 #include <netdev.h> 28 #include <asm/mach-types.h> 29 30 DECLARE_GLOBAL_DATA_PTR; 31 32 /* ------------------------------------------------------------------------- */ 33 /* 34 * Miscelaneous platform dependent initialisations 35 */ 36 37 #ifdef CONFIG_CMD_NAND 38 static void pm9263_nand_hw_init(void) 39 { 40 unsigned long csa; 41 struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC0; 42 struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX; 43 44 /* Enable CS3 */ 45 csa = readl(&matrix->csa[0]) | AT91_MATRIX_CSA_EBI_CS3A; 46 writel(csa, &matrix->csa[0]); 47 48 /* Configure SMC CS3 for NAND/SmartMedia */ 49 writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(1) | 50 AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(1), 51 &smc->cs[3].setup); 52 53 writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(3) | 54 AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(3), 55 &smc->cs[3].pulse); 56 57 writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(5), 58 &smc->cs[3].cycle); 59 60 writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE | 61 AT91_SMC_MODE_EXNW_DISABLE | 62 #ifdef CONFIG_SYS_NAND_DBW_16 63 AT91_SMC_MODE_DBW_16 | 64 #else /* CONFIG_SYS_NAND_DBW_8 */ 65 AT91_SMC_MODE_DBW_8 | 66 #endif 67 AT91_SMC_MODE_TDF_CYCLE(2), 68 &smc->cs[3].mode); 69 70 /* Configure RDY/BSY */ 71 gpio_direction_input(CONFIG_SYS_NAND_READY_PIN); 72 73 /* Enable NandFlash */ 74 gpio_direction_output(CONFIG_SYS_NAND_ENABLE_PIN, 1); 75 } 76 #endif 77 78 #ifdef CONFIG_MACB 79 static void pm9263_macb_hw_init(void) 80 { 81 /* 82 * PB27 enables the 50MHz oscillator for Ethernet PHY 83 * 1 - enable 84 * 0 - disable 85 */ 86 at91_set_pio_output(AT91_PIO_PORTB, 27, 1); 87 at91_set_pio_value(AT91_PIO_PORTB, 27, 1); /* 1- enable, 0 - disable */ 88 89 at91_periph_clk_enable(ATMEL_ID_EMAC); 90 91 /* 92 * Disable pull-up on: 93 * RXDV (PC25) => PHY normal mode (not Test mode) 94 * ERX0 (PE25) => PHY ADDR0 95 * ERX1 (PE26) => PHY ADDR1 => PHYADDR = 0x0 96 * 97 * PHY has internal pull-down 98 */ 99 100 at91_set_pio_pullup(AT91_PIO_PORTC, 25, 0); 101 at91_set_pio_pullup(AT91_PIO_PORTE, 25, 0); 102 at91_set_pio_pullup(AT91_PIO_PORTE, 26, 0); 103 104 /* Re-enable pull-up */ 105 at91_set_pio_pullup(AT91_PIO_PORTC, 25, 1); 106 at91_set_pio_pullup(AT91_PIO_PORTE, 25, 1); 107 at91_set_pio_pullup(AT91_PIO_PORTE, 26, 1); 108 109 at91_macb_hw_init(); 110 } 111 #endif 112 113 #ifdef CONFIG_LCD 114 vidinfo_t panel_info = { 115 .vl_col = 240, 116 .vl_row = 320, 117 .vl_clk = 4965000, 118 .vl_sync = ATMEL_LCDC_INVLINE_INVERTED | 119 ATMEL_LCDC_INVFRAME_INVERTED, 120 .vl_bpix = 3, 121 .vl_tft = 1, 122 .vl_hsync_len = 5, 123 .vl_left_margin = 1, 124 .vl_right_margin = 33, 125 .vl_vsync_len = 1, 126 .vl_upper_margin = 1, 127 .vl_lower_margin = 0, 128 .mmio = ATMEL_BASE_LCDC, 129 }; 130 131 void lcd_enable(void) 132 { 133 at91_set_pio_value(AT91_PIO_PORTA, 22, 1); /* power up */ 134 } 135 136 void lcd_disable(void) 137 { 138 at91_set_pio_value(AT91_PIO_PORTA, 22, 0); /* power down */ 139 } 140 141 #ifdef CONFIG_LCD_IN_PSRAM 142 143 #define PSRAM_CRE_PIN AT91_PIO_PORTB, 29 144 #define PSRAM_CTRL_REG (PHYS_PSRAM + PHYS_PSRAM_SIZE - 2) 145 146 /* Initialize the PSRAM memory */ 147 static int pm9263_lcd_hw_psram_init(void) 148 { 149 unsigned long csa; 150 struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC1; 151 struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX; 152 153 /* Enable CS3 3.3v, no pull-ups */ 154 csa = readl(&matrix->csa[1]) | AT91_MATRIX_CSA_DBPUC | 155 AT91_MATRIX_CSA_VDDIOMSEL_3_3V; 156 157 writel(csa, &matrix->csa[1]); 158 159 /* Configure SMC1 CS0 for PSRAM - 16-bit */ 160 writel(AT91_SMC_SETUP_NWE(0) | AT91_SMC_SETUP_NCS_WR(0) | 161 AT91_SMC_SETUP_NRD(0) | AT91_SMC_SETUP_NCS_RD(0), 162 &smc->cs[0].setup); 163 164 writel(AT91_SMC_PULSE_NWE(7) | AT91_SMC_PULSE_NCS_WR(7) | 165 AT91_SMC_PULSE_NRD(2) | AT91_SMC_PULSE_NCS_RD(7), 166 &smc->cs[0].pulse); 167 168 writel(AT91_SMC_CYCLE_NWE(8) | AT91_SMC_CYCLE_NRD(8), 169 &smc->cs[0].cycle); 170 171 writel(AT91_SMC_MODE_DBW_16 | AT91_SMC_MODE_PMEN | AT91_SMC_MODE_PS_32, 172 &smc->cs[0].mode); 173 174 /* setup PB29 as output */ 175 at91_set_pio_output(PSRAM_CRE_PIN, 1); 176 177 at91_set_pio_value(PSRAM_CRE_PIN, 0); /* set PSRAM_CRE_PIN to '0' */ 178 179 /* PSRAM: write BCR */ 180 readw(PSRAM_CTRL_REG); 181 readw(PSRAM_CTRL_REG); 182 writew(1, PSRAM_CTRL_REG); /* 0 - RCR,1 - BCR */ 183 writew(0x9d4f, PSRAM_CTRL_REG); /* write the BCR */ 184 185 /* write RCR of the PSRAM */ 186 readw(PSRAM_CTRL_REG); 187 readw(PSRAM_CTRL_REG); 188 writew(0, PSRAM_CTRL_REG); /* 0 - RCR,1 - BCR */ 189 /* set RCR; 0x10-async mode,0x90-page mode */ 190 writew(0x90, PSRAM_CTRL_REG); 191 192 /* 193 * test to see if the PSRAM is MT45W2M16A or MT45W2M16B 194 * MT45W2M16B - CRE must be 0 195 * MT45W2M16A - CRE must be 1 196 */ 197 writew(0x1234, PHYS_PSRAM); 198 writew(0x5678, PHYS_PSRAM + 2); 199 200 /* test if the chip is MT45W2M16B */ 201 if ((readw(PHYS_PSRAM) != 0x1234) || (readw(PHYS_PSRAM+2) != 0x5678)) { 202 /* try with CRE=1 (MT45W2M16A) */ 203 at91_set_pio_value(PSRAM_CRE_PIN, 1); /* set PSRAM_CRE_PIN to '1' */ 204 205 /* write RCR of the PSRAM */ 206 readw(PSRAM_CTRL_REG); 207 readw(PSRAM_CTRL_REG); 208 writew(0, PSRAM_CTRL_REG); /* 0 - RCR,1 - BCR */ 209 /* set RCR;0x10-async mode,0x90-page mode */ 210 writew(0x90, PSRAM_CTRL_REG); 211 212 213 writew(0x1234, PHYS_PSRAM); 214 writew(0x5678, PHYS_PSRAM+2); 215 if ((readw(PHYS_PSRAM) != 0x1234) 216 || (readw(PHYS_PSRAM + 2) != 0x5678)) 217 return 1; 218 219 } 220 221 /* Bus matrix */ 222 writel(AT91_MATRIX_PRA_M5(3), &matrix->pr[5].a); 223 writel(CONFIG_PSRAM_SCFG, &matrix->scfg[5]); 224 225 return 0; 226 } 227 #endif 228 229 static void pm9263_lcd_hw_init(void) 230 { 231 at91_set_a_periph(AT91_PIO_PORTC, 0, 0); /* LCDVSYNC */ 232 at91_set_a_periph(AT91_PIO_PORTC, 1, 0); /* LCDHSYNC */ 233 at91_set_a_periph(AT91_PIO_PORTC, 2, 0); /* LCDDOTCK */ 234 at91_set_a_periph(AT91_PIO_PORTC, 3, 0); /* LCDDEN */ 235 at91_set_b_periph(AT91_PIO_PORTB, 9, 0); /* LCDCC */ 236 at91_set_a_periph(AT91_PIO_PORTC, 6, 0); /* LCDD2 */ 237 at91_set_a_periph(AT91_PIO_PORTC, 7, 0); /* LCDD3 */ 238 at91_set_a_periph(AT91_PIO_PORTC, 8, 0); /* LCDD4 */ 239 at91_set_a_periph(AT91_PIO_PORTC, 9, 0); /* LCDD5 */ 240 at91_set_a_periph(AT91_PIO_PORTC, 10, 0); /* LCDD6 */ 241 at91_set_a_periph(AT91_PIO_PORTC, 11, 0); /* LCDD7 */ 242 at91_set_a_periph(AT91_PIO_PORTC, 14, 0); /* LCDD10 */ 243 at91_set_a_periph(AT91_PIO_PORTC, 15, 0); /* LCDD11 */ 244 at91_set_a_periph(AT91_PIO_PORTC, 16, 0); /* LCDD12 */ 245 at91_set_b_periph(AT91_PIO_PORTC, 12, 0); /* LCDD13 */ 246 at91_set_a_periph(AT91_PIO_PORTC, 18, 0); /* LCDD14 */ 247 at91_set_a_periph(AT91_PIO_PORTC, 19, 0); /* LCDD15 */ 248 at91_set_a_periph(AT91_PIO_PORTC, 22, 0); /* LCDD18 */ 249 at91_set_a_periph(AT91_PIO_PORTC, 23, 0); /* LCDD19 */ 250 at91_set_a_periph(AT91_PIO_PORTC, 24, 0); /* LCDD20 */ 251 at91_set_b_periph(AT91_PIO_PORTC, 17, 0); /* LCDD21 */ 252 at91_set_a_periph(AT91_PIO_PORTC, 26, 0); /* LCDD22 */ 253 at91_set_a_periph(AT91_PIO_PORTC, 27, 0); /* LCDD23 */ 254 255 at91_periph_clk_enable(ATMEL_ID_LCDC); 256 257 /* Power Control */ 258 at91_set_pio_output(AT91_PIO_PORTA, 22, 1); 259 at91_set_pio_value(AT91_PIO_PORTA, 22, 0); /* power down */ 260 261 #ifdef CONFIG_LCD_IN_PSRAM 262 /* initialize te PSRAM */ 263 int stat = pm9263_lcd_hw_psram_init(); 264 265 gd->fb_base = (stat == 0) ? PHYS_PSRAM : ATMEL_BASE_SRAM0; 266 #else 267 gd->fb_base = ATMEL_BASE_SRAM0; 268 #endif 269 270 } 271 272 #ifdef CONFIG_LCD_INFO 273 #include <nand.h> 274 #include <version.h> 275 276 extern flash_info_t flash_info[]; 277 278 void lcd_show_board_info(void) 279 { 280 ulong dram_size, nand_size, flash_size, dataflash_size; 281 int i; 282 char temp[32]; 283 284 lcd_printf ("%s\n", U_BOOT_VERSION); 285 lcd_printf ("(C) 2009 Ronetix GmbH\n"); 286 lcd_printf ("support@ronetix.at\n"); 287 lcd_printf ("%s CPU at %s MHz", 288 CONFIG_SYS_AT91_CPU_NAME, 289 strmhz(temp, get_cpu_clk_rate())); 290 291 dram_size = 0; 292 for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) 293 dram_size += gd->bd->bi_dram[i].size; 294 295 nand_size = 0; 296 for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++) 297 nand_size += nand_info[i]->size; 298 299 flash_size = 0; 300 for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) 301 flash_size += flash_info[i].size; 302 303 dataflash_size = 0; 304 for (i = 0; i < CONFIG_SYS_MAX_DATAFLASH_BANKS; i++) 305 dataflash_size += (unsigned int) dataflash_info[i].Device.pages_number * 306 dataflash_info[i].Device.pages_size; 307 308 lcd_printf ("%ld MB SDRAM, %ld MB NAND\n%ld MB NOR Flash\n" 309 "4 MB PSRAM, %ld MB DataFlash\n", 310 dram_size >> 20, 311 nand_size >> 20, 312 flash_size >> 20, 313 dataflash_size >> 20); 314 } 315 #endif /* CONFIG_LCD_INFO */ 316 317 #endif /* CONFIG_LCD */ 318 319 int board_early_init_f(void) 320 { 321 at91_periph_clk_enable(ATMEL_ID_PIOA); 322 at91_periph_clk_enable(ATMEL_ID_PIOB); 323 at91_periph_clk_enable(ATMEL_ID_PIOCDE); 324 325 at91_seriald_hw_init(); 326 327 return 0; 328 } 329 330 int board_init(void) 331 { 332 /* arch number of AT91SAM9263EK-Board */ 333 gd->bd->bi_arch_number = MACH_TYPE_PM9263; 334 335 /* adress of boot parameters */ 336 gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; 337 338 #ifdef CONFIG_CMD_NAND 339 pm9263_nand_hw_init(); 340 #endif 341 #ifdef CONFIG_HAS_DATAFLASH 342 at91_spi0_hw_init(1 << 0); 343 #endif 344 #ifdef CONFIG_MACB 345 pm9263_macb_hw_init(); 346 #endif 347 #ifdef CONFIG_USB_OHCI_NEW 348 at91_uhp_hw_init(); 349 #endif 350 #ifdef CONFIG_LCD 351 pm9263_lcd_hw_init(); 352 #endif 353 return 0; 354 } 355 356 int dram_init(void) 357 { 358 /* dram_init must store complete ramsize in gd->ram_size */ 359 gd->ram_size = get_ram_size((void *)PHYS_SDRAM, 360 PHYS_SDRAM_SIZE); 361 return 0; 362 } 363 364 int dram_init_banksize(void) 365 { 366 gd->bd->bi_dram[0].start = PHYS_SDRAM; 367 gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE; 368 369 return 0; 370 } 371 372 #ifdef CONFIG_RESET_PHY_R 373 void reset_phy(void) 374 { 375 } 376 #endif 377 378 int board_eth_init(bd_t *bis) 379 { 380 int rc = 0; 381 #ifdef CONFIG_MACB 382 rc = macb_eth_initialize(0, (void *)ATMEL_BASE_EMAC, 0x01); 383 #endif 384 return rc; 385 } 386 387 #ifdef CONFIG_DISPLAY_BOARDINFO 388 int checkboard (void) 389 { 390 char *ss; 391 392 printf ("Board : Ronetix PM9263\n"); 393 394 switch (gd->fb_base) { 395 case PHYS_PSRAM: 396 ss = "(PSRAM)"; 397 break; 398 399 case ATMEL_BASE_SRAM0: 400 ss = "(Internal SRAM)"; 401 break; 402 403 default: 404 ss = ""; 405 break; 406 } 407 printf("Video memory : 0x%08lX %s\n", gd->fb_base, ss ); 408 409 printf ("\n"); 410 return 0; 411 } 412 #endif 413