1 /* 2 * (C) Copyright 2007-2008 3 * Stelian Pop <stelian.pop@leadtechdesign.com> 4 * Lead Tech Design <www.leadtechdesign.com> 5 * Copyright (C) 2008 Ronetix Ilko Iliev (www.ronetix.at) 6 * Copyright (C) 2009 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> 7 * 8 * See file CREDITS for list of people who contributed to this 9 * project. 10 * 11 * This program is free software; you can redistribute it and/or 12 * modify it under the terms of the GNU General Public License as 13 * published by the Free Software Foundation; either version 2 of 14 * the License, or (at your option) any later version. 15 * 16 * This program is distributed in the hope that it will be useful, 17 * but WITHOUT ANY WARRANTY; without even the implied warranty of 18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 19 * GNU General Public License for more details. 20 * 21 * You should have received a copy of the GNU General Public License 22 * along with this program; if not, write to the Free Software 23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 24 * MA 02111-1307 USA 25 */ 26 27 #include <common.h> 28 #include <asm/sizes.h> 29 #include <asm/arch/at91sam9263.h> 30 #include <asm/arch/at91sam9263_matrix.h> 31 #include <asm/arch/at91sam9_smc.h> 32 #include <asm/arch/at91_common.h> 33 #include <asm/arch/at91_pmc.h> 34 #include <asm/arch/at91_rstc.h> 35 #include <asm/arch/clk.h> 36 #include <asm/arch/gpio.h> 37 #include <asm/arch/io.h> 38 #include <asm/arch/hardware.h> 39 #include <lcd.h> 40 #include <atmel_lcdc.h> 41 #include <dataflash.h> 42 #if defined(CONFIG_RESET_PHY_R) && defined(CONFIG_MACB) 43 #include <net.h> 44 #endif 45 #include <netdev.h> 46 47 DECLARE_GLOBAL_DATA_PTR; 48 49 /* ------------------------------------------------------------------------- */ 50 /* 51 * Miscelaneous platform dependent initialisations 52 */ 53 54 #ifdef CONFIG_CMD_NAND 55 static void pm9263_nand_hw_init(void) 56 { 57 unsigned long csa; 58 59 /* Enable CS3 */ 60 csa = at91_sys_read(AT91_MATRIX_EBI0CSA); 61 at91_sys_write(AT91_MATRIX_EBI0CSA, 62 csa | AT91_MATRIX_EBI0_CS3A_SMC_SMARTMEDIA); 63 64 /* Configure SMC CS3 for NAND/SmartMedia */ 65 at91_sys_write(AT91_SMC_SETUP(3), 66 AT91_SMC_NWESETUP_(1) | AT91_SMC_NCS_WRSETUP_(1) | 67 AT91_SMC_NRDSETUP_(1) | AT91_SMC_NCS_RDSETUP_(1)); 68 at91_sys_write(AT91_SMC_PULSE(3), 69 AT91_SMC_NWEPULSE_(3) | AT91_SMC_NCS_WRPULSE_(3) | 70 AT91_SMC_NRDPULSE_(3) | AT91_SMC_NCS_RDPULSE_(3)); 71 at91_sys_write(AT91_SMC_CYCLE(3), 72 AT91_SMC_NWECYCLE_(5) | AT91_SMC_NRDCYCLE_(5)); 73 at91_sys_write(AT91_SMC_MODE(3), 74 AT91_SMC_READMODE | AT91_SMC_WRITEMODE | 75 AT91_SMC_EXNWMODE_DISABLE | 76 #ifdef CONFIG_SYS_NAND_DBW_16 77 AT91_SMC_DBW_16 | 78 #else /* CONFIG_SYS_NAND_DBW_8 */ 79 AT91_SMC_DBW_8 | 80 #endif 81 AT91_SMC_TDF_(2)); 82 83 /* Configure RDY/BSY */ 84 at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1); 85 86 /* Enable NandFlash */ 87 at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1); 88 } 89 #endif 90 91 #ifdef CONFIG_MACB 92 static void pm9263_macb_hw_init(void) 93 { 94 /* 95 * PB27 enables the 50MHz oscillator for Ethernet PHY 96 * 1 - enable 97 * 0 - disable 98 */ 99 at91_set_gpio_output(AT91_PIN_PB27, 1); 100 at91_set_gpio_value(AT91_PIN_PB27, 1); /* 1- enable, 0 - disable */ 101 102 /* Enable clock */ 103 at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9263_ID_EMAC); 104 105 /* 106 * Disable pull-up on: 107 * RXDV (PC25) => PHY normal mode (not Test mode) 108 * ERX0 (PE25) => PHY ADDR0 109 * ERX1 (PE26) => PHY ADDR1 => PHYADDR = 0x0 110 * 111 * PHY has internal pull-down 112 */ 113 writel(pin_to_mask(AT91_PIN_PC25), 114 pin_to_controller(AT91_PIN_PC0) + PIO_PUDR); 115 writel(pin_to_mask(AT91_PIN_PE25) | 116 pin_to_mask(AT91_PIN_PE26), 117 pin_to_controller(AT91_PIN_PE0) + PIO_PUDR); 118 119 120 /* Re-enable pull-up */ 121 writel(pin_to_mask(AT91_PIN_PC25), 122 pin_to_controller(AT91_PIN_PC0) + PIO_PUER); 123 writel(pin_to_mask(AT91_PIN_PE25) | 124 pin_to_mask(AT91_PIN_PE26), 125 pin_to_controller(AT91_PIN_PE0) + PIO_PUER); 126 127 at91_macb_hw_init(); 128 } 129 #endif 130 131 #ifdef CONFIG_LCD 132 vidinfo_t panel_info = { 133 vl_col: 240, 134 vl_row: 320, 135 vl_clk: 4965000, 136 vl_sync: ATMEL_LCDC_INVLINE_INVERTED | 137 ATMEL_LCDC_INVFRAME_INVERTED, 138 vl_bpix: 3, 139 vl_tft: 1, 140 vl_hsync_len: 5, 141 vl_left_margin: 1, 142 vl_right_margin:33, 143 vl_vsync_len: 1, 144 vl_upper_margin:1, 145 vl_lower_margin:0, 146 mmio: AT91SAM9263_LCDC_BASE, 147 }; 148 149 void lcd_enable(void) 150 { 151 at91_set_gpio_value(AT91_PIN_PA22, 1); /* power up */ 152 } 153 154 void lcd_disable(void) 155 { 156 at91_set_gpio_value(AT91_PIN_PA22, 0); /* power down */ 157 } 158 159 #ifdef CONFIG_LCD_IN_PSRAM 160 161 #define PSRAM_CRE_PIN AT91_PIN_PB29 162 #define PSRAM_CTRL_REG (PHYS_PSRAM + PHYS_PSRAM_SIZE - 2) 163 164 /* Initialize the PSRAM memory */ 165 static int pm9263_lcd_hw_psram_init(void) 166 { 167 volatile uint16_t x; 168 unsigned long csa; 169 170 /* Enable CS3 3.3v, no pull-ups */ 171 csa = at91_sys_read(AT91_MATRIX_EBI1CSA); 172 at91_sys_write(AT91_MATRIX_EBI1CSA, 173 csa | AT91_MATRIX_EBI1_DBPUC | 174 AT91_MATRIX_EBI1_VDDIOMSEL_3_3V); 175 176 /* Configure SMC1 CS0 for PSRAM - 16-bit */ 177 at91_sys_write(AT91_SMC1_SETUP(0), 178 AT91_SMC_NWESETUP_(0) | AT91_SMC_NCS_WRSETUP_(0) | 179 AT91_SMC_NRDSETUP_(0) | AT91_SMC_NCS_RDSETUP_(0)); 180 at91_sys_write(AT91_SMC1_PULSE(0), 181 AT91_SMC_NWEPULSE_(7) | AT91_SMC_NCS_WRPULSE_(7) | 182 AT91_SMC_NRDPULSE_(2) | AT91_SMC_NCS_RDPULSE_(7)); 183 at91_sys_write(AT91_SMC1_CYCLE(0), 184 AT91_SMC_NWECYCLE_(8) | AT91_SMC_NRDCYCLE_(8)); 185 at91_sys_write(AT91_SMC1_MODE(0), 186 AT91_SMC_DBW_16 | 187 AT91_SMC_PMEN | 188 AT91_SMC_PS_32); 189 190 /* setup PB29 as output */ 191 at91_set_gpio_output(PSRAM_CRE_PIN, 1); 192 193 at91_set_gpio_value(PSRAM_CRE_PIN, 0); /* set PSRAM_CRE_PIN to '0' */ 194 195 /* PSRAM: write BCR */ 196 x = readw(PSRAM_CTRL_REG); 197 x = readw(PSRAM_CTRL_REG); 198 writew(1, PSRAM_CTRL_REG); /* 0 - RCR,1 - BCR */ 199 writew(0x9d4f, PSRAM_CTRL_REG); /* write the BCR */ 200 201 /* write RCR of the PSRAM */ 202 x = readw(PSRAM_CTRL_REG); 203 x = readw(PSRAM_CTRL_REG); 204 writew(0, PSRAM_CTRL_REG); /* 0 - RCR,1 - BCR */ 205 /* set RCR; 0x10-async mode,0x90-page mode */ 206 writew(0x90, PSRAM_CTRL_REG); 207 208 /* 209 * test to see if the PSRAM is MT45W2M16A or MT45W2M16B 210 * MT45W2M16B - CRE must be 0 211 * MT45W2M16A - CRE must be 1 212 */ 213 writew(0x1234, PHYS_PSRAM); 214 writew(0x5678, PHYS_PSRAM + 2); 215 216 /* test if the chip is MT45W2M16B */ 217 if ((readw(PHYS_PSRAM) != 0x1234) || (readw(PHYS_PSRAM+2) != 0x5678)) { 218 /* try with CRE=1 (MT45W2M16A) */ 219 at91_set_gpio_value(PSRAM_CRE_PIN, 1); /* set PSRAM_CRE_PIN to '1' */ 220 221 /* write RCR of the PSRAM */ 222 x = readw(PSRAM_CTRL_REG); 223 x = readw(PSRAM_CTRL_REG); 224 writew(0, PSRAM_CTRL_REG); /* 0 - RCR,1 - BCR */ 225 /* set RCR;0x10-async mode,0x90-page mode */ 226 writew(0x90, PSRAM_CTRL_REG); 227 228 229 writew(0x1234, PHYS_PSRAM); 230 writew(0x5678, PHYS_PSRAM+2); 231 if ((readw(PHYS_PSRAM) != 0x1234) 232 || (readw(PHYS_PSRAM + 2) != 0x5678)) 233 return 1; 234 235 } 236 237 /* Bus matrix */ 238 at91_sys_write( AT91_MATRIX_PRAS5, AT91_MATRIX_M5PR ); 239 at91_sys_write( AT91_MATRIX_SCFG5, AT91_MATRIX_ARBT_FIXED_PRIORITY | 240 (AT91_MATRIX_FIXED_DEFMSTR & (5 << 18)) | 241 AT91_MATRIX_DEFMSTR_TYPE_FIXED | 242 (AT91_MATRIX_SLOT_CYCLE & (0xFF << 0))); 243 244 return 0; 245 } 246 #endif 247 248 static void pm9263_lcd_hw_init(void) 249 { 250 at91_set_A_periph(AT91_PIN_PC0, 0); /* LCDVSYNC */ 251 at91_set_A_periph(AT91_PIN_PC1, 0); /* LCDHSYNC */ 252 at91_set_A_periph(AT91_PIN_PC2, 0); /* LCDDOTCK */ 253 at91_set_A_periph(AT91_PIN_PC3, 0); /* LCDDEN */ 254 at91_set_B_periph(AT91_PIN_PB9, 0); /* LCDCC */ 255 at91_set_A_periph(AT91_PIN_PC6, 0); /* LCDD2 */ 256 at91_set_A_periph(AT91_PIN_PC7, 0); /* LCDD3 */ 257 at91_set_A_periph(AT91_PIN_PC8, 0); /* LCDD4 */ 258 at91_set_A_periph(AT91_PIN_PC9, 0); /* LCDD5 */ 259 at91_set_A_periph(AT91_PIN_PC10, 0); /* LCDD6 */ 260 at91_set_A_periph(AT91_PIN_PC11, 0); /* LCDD7 */ 261 at91_set_A_periph(AT91_PIN_PC14, 0); /* LCDD10 */ 262 at91_set_A_periph(AT91_PIN_PC15, 0); /* LCDD11 */ 263 at91_set_A_periph(AT91_PIN_PC16, 0); /* LCDD12 */ 264 at91_set_B_periph(AT91_PIN_PC12, 0); /* LCDD13 */ 265 at91_set_A_periph(AT91_PIN_PC18, 0); /* LCDD14 */ 266 at91_set_A_periph(AT91_PIN_PC19, 0); /* LCDD15 */ 267 at91_set_A_periph(AT91_PIN_PC22, 0); /* LCDD18 */ 268 at91_set_A_periph(AT91_PIN_PC23, 0); /* LCDD19 */ 269 at91_set_A_periph(AT91_PIN_PC24, 0); /* LCDD20 */ 270 at91_set_B_periph(AT91_PIN_PC17, 0); /* LCDD21 */ 271 at91_set_A_periph(AT91_PIN_PC26, 0); /* LCDD22 */ 272 at91_set_A_periph(AT91_PIN_PC27, 0); /* LCDD23 */ 273 274 at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9263_ID_LCDC); 275 276 /* Power Control */ 277 at91_set_gpio_output(AT91_PIN_PA22, 1); 278 at91_set_gpio_value(AT91_PIN_PA22, 0); /* power down */ 279 280 #ifdef CONFIG_LCD_IN_PSRAM 281 /* initialize te PSRAM */ 282 int stat = pm9263_lcd_hw_psram_init(); 283 284 gd->fb_base = (stat == 0) ? PHYS_PSRAM : AT91SAM9263_SRAM0_BASE; 285 #else 286 gd->fb_base = AT91SAM9263_SRAM0_BASE; 287 #endif 288 289 } 290 291 #ifdef CONFIG_LCD_INFO 292 #include <nand.h> 293 #include <version.h> 294 295 extern flash_info_t flash_info[]; 296 297 void lcd_show_board_info(void) 298 { 299 ulong dram_size, nand_size, flash_size, dataflash_size; 300 int i; 301 char temp[32]; 302 303 lcd_printf ("%s\n", U_BOOT_VERSION); 304 lcd_printf ("(C) 2009 Ronetix GmbH\n"); 305 lcd_printf ("support@ronetix.at\n"); 306 lcd_printf ("%s CPU at %s MHz", 307 CONFIG_SYS_AT91_CPU_NAME, 308 strmhz(temp, get_cpu_clk_rate())); 309 310 dram_size = 0; 311 for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) 312 dram_size += gd->bd->bi_dram[i].size; 313 314 nand_size = 0; 315 for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++) 316 nand_size += nand_info[i].size; 317 318 flash_size = 0; 319 for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) 320 flash_size += flash_info[i].size; 321 322 dataflash_size = 0; 323 for (i = 0; i < CONFIG_SYS_MAX_DATAFLASH_BANKS; i++) 324 dataflash_size += (unsigned int) dataflash_info[i].Device.pages_number * 325 dataflash_info[i].Device.pages_size; 326 327 lcd_printf ("%ld MB SDRAM, %ld MB NAND\n%ld MB NOR Flash\n" 328 "4 MB PSRAM, %ld MB DataFlash\n", 329 dram_size >> 20, 330 nand_size >> 20, 331 flash_size >> 20, 332 dataflash_size >> 20); 333 } 334 #endif /* CONFIG_LCD_INFO */ 335 336 #endif /* CONFIG_LCD */ 337 338 int board_init(void) 339 { 340 /* Enable Ctrlc */ 341 console_init_f(); 342 343 at91_sys_write(AT91_PMC_PCER, 344 (1 << AT91SAM9263_ID_PIOA) | 345 (1 << AT91SAM9263_ID_PIOCDE) | 346 (1 << AT91SAM9263_ID_PIOB)); 347 348 /* arch number of AT91SAM9263EK-Board */ 349 gd->bd->bi_arch_number = MACH_TYPE_PM9263; 350 351 /* adress of boot parameters */ 352 gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; 353 354 at91_serial_hw_init(); 355 #ifdef CONFIG_CMD_NAND 356 pm9263_nand_hw_init(); 357 #endif 358 #ifdef CONFIG_HAS_DATAFLASH 359 at91_spi0_hw_init(1 << 0); 360 #endif 361 #ifdef CONFIG_MACB 362 pm9263_macb_hw_init(); 363 #endif 364 #ifdef CONFIG_USB_OHCI_NEW 365 at91_uhp_hw_init(); 366 #endif 367 #ifdef CONFIG_LCD 368 pm9263_lcd_hw_init(); 369 #endif 370 return 0; 371 } 372 373 int dram_init(void) 374 { 375 gd->bd->bi_dram[0].start = PHYS_SDRAM; 376 gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE; 377 return 0; 378 } 379 380 #ifdef CONFIG_RESET_PHY_R 381 void reset_phy(void) 382 { 383 #ifdef CONFIG_MACB 384 /* 385 * Initialize ethernet HW addr prior to starting Linux, 386 * needed for nfsroot 387 */ 388 eth_init(gd->bd); 389 #endif 390 } 391 #endif 392 393 int board_eth_init(bd_t *bis) 394 { 395 int rc = 0; 396 #ifdef CONFIG_MACB 397 rc = macb_eth_initialize(0, (void *)AT91SAM9263_BASE_EMAC, 0x01); 398 #endif 399 return rc; 400 } 401 402 #ifdef CONFIG_DISPLAY_BOARDINFO 403 int checkboard (void) 404 { 405 char *ss; 406 407 printf ("Board : Ronetix PM9263\n"); 408 409 switch (gd->fb_base) { 410 case PHYS_PSRAM: 411 ss = "(PSRAM)"; 412 break; 413 414 case AT91SAM9263_SRAM0_BASE: 415 ss = "(Internal SRAM)"; 416 break; 417 418 default: 419 ss = ""; 420 break; 421 } 422 printf("Video memory : 0x%08lX %s\n", gd->fb_base, ss ); 423 424 printf ("\n"); 425 return 0; 426 } 427 #endif 428