1 /* 2 * (C) Copyright 2007-2008 3 * Stelian Pop <stelian.pop@leadtechdesign.com> 4 * Lead Tech Design <www.leadtechdesign.com> 5 * Copyright (C) 2008 Ronetix Ilko Iliev (www.ronetix.at) 6 * Copyright (C) 2009 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> 7 * 8 * See file CREDITS for list of people who contributed to this 9 * project. 10 * 11 * This program is free software; you can redistribute it and/or 12 * modify it under the terms of the GNU General Public License as 13 * published by the Free Software Foundation; either version 2 of 14 * the License, or (at your option) any later version. 15 * 16 * This program is distributed in the hope that it will be useful, 17 * but WITHOUT ANY WARRANTY; without even the implied warranty of 18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 19 * GNU General Public License for more details. 20 * 21 * You should have received a copy of the GNU General Public License 22 * along with this program; if not, write to the Free Software 23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 24 * MA 02111-1307 USA 25 */ 26 27 #include <common.h> 28 #include <asm/sizes.h> 29 #include <asm/arch/at91sam9263.h> 30 #include <asm/arch/at91sam9_smc.h> 31 #include <asm/arch/at91_common.h> 32 #include <asm/arch/at91_pmc.h> 33 #include <asm/arch/at91_rstc.h> 34 #include <asm/arch/at91_matrix.h> 35 #include <asm/arch/at91_pio.h> 36 #include <asm/arch/clk.h> 37 #include <asm/arch/io.h> 38 #include <asm/arch/hardware.h> 39 #include <lcd.h> 40 #include <atmel_lcdc.h> 41 #include <dataflash.h> 42 #if defined(CONFIG_RESET_PHY_R) && defined(CONFIG_MACB) 43 #include <net.h> 44 #endif 45 #include <netdev.h> 46 47 DECLARE_GLOBAL_DATA_PTR; 48 49 /* ------------------------------------------------------------------------- */ 50 /* 51 * Miscelaneous platform dependent initialisations 52 */ 53 54 #ifdef CONFIG_CMD_NAND 55 static void pm9263_nand_hw_init(void) 56 { 57 unsigned long csa; 58 at91_smc_t *smc = (at91_smc_t *) AT91_SMC0_BASE; 59 at91_matrix_t *matrix = (at91_matrix_t *) AT91_MATRIX_BASE; 60 61 /* Enable CS3 */ 62 csa = readl(&matrix->csa[0]) | AT91_MATRIX_CSA_EBI_CS3A; 63 writel(csa, &matrix->csa[0]); 64 65 /* Configure SMC CS3 for NAND/SmartMedia */ 66 writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(1) | 67 AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(1), 68 &smc->cs[3].setup); 69 70 writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(3) | 71 AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(3), 72 &smc->cs[3].pulse); 73 74 writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(5), 75 &smc->cs[3].cycle); 76 77 writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE | 78 AT91_SMC_MODE_EXNW_DISABLE | 79 #ifdef CONFIG_SYS_NAND_DBW_16 80 AT91_SMC_MODE_DBW_16 | 81 #else /* CONFIG_SYS_NAND_DBW_8 */ 82 AT91_SMC_MODE_DBW_8 | 83 #endif 84 AT91_SMC_MODE_TDF_CYCLE(2), 85 &smc->cs[3].mode); 86 87 /* Configure RDY/BSY */ 88 at91_set_pio_input(CONFIG_SYS_NAND_READY_PIN, 1); 89 90 /* Enable NandFlash */ 91 at91_set_pio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1); 92 } 93 #endif 94 95 #ifdef CONFIG_MACB 96 static void pm9263_macb_hw_init(void) 97 { 98 at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE; 99 at91_pio_t *pio = (at91_pio_t *) AT91_PIO_BASE; 100 101 /* 102 * PB27 enables the 50MHz oscillator for Ethernet PHY 103 * 1 - enable 104 * 0 - disable 105 */ 106 at91_set_pio_output(AT91_PIO_PORTB, 27, 1); 107 at91_set_pio_value(AT91_PIO_PORTB, 27, 1); /* 1- enable, 0 - disable */ 108 109 /* Enable clock */ 110 writel(1 << AT91SAM9263_ID_EMAC, &pmc->pcer); 111 112 /* 113 * Disable pull-up on: 114 * RXDV (PC25) => PHY normal mode (not Test mode) 115 * ERX0 (PE25) => PHY ADDR0 116 * ERX1 (PE26) => PHY ADDR1 => PHYADDR = 0x0 117 * 118 * PHY has internal pull-down 119 */ 120 121 at91_set_pio_pullup(AT91_PIO_PORTC, 25, 0); 122 at91_set_pio_pullup(AT91_PIO_PORTE, 25, 0); 123 at91_set_pio_pullup(AT91_PIO_PORTE, 26, 0); 124 125 /* Re-enable pull-up */ 126 at91_set_pio_pullup(AT91_PIO_PORTC, 25, 1); 127 at91_set_pio_pullup(AT91_PIO_PORTE, 25, 1); 128 at91_set_pio_pullup(AT91_PIO_PORTE, 26, 1); 129 130 at91_macb_hw_init(); 131 } 132 #endif 133 134 #ifdef CONFIG_LCD 135 vidinfo_t panel_info = { 136 vl_col: 240, 137 vl_row: 320, 138 vl_clk: 4965000, 139 vl_sync: ATMEL_LCDC_INVLINE_INVERTED | 140 ATMEL_LCDC_INVFRAME_INVERTED, 141 vl_bpix: 3, 142 vl_tft: 1, 143 vl_hsync_len: 5, 144 vl_left_margin: 1, 145 vl_right_margin:33, 146 vl_vsync_len: 1, 147 vl_upper_margin:1, 148 vl_lower_margin:0, 149 mmio: AT91SAM9263_LCDC_BASE, 150 }; 151 152 void lcd_enable(void) 153 { 154 at91_set_pio_value(AT91_PIO_PORTA, 22, 1); /* power up */ 155 } 156 157 void lcd_disable(void) 158 { 159 at91_set_pio_value(AT91_PIO_PORTA, 22, 0); /* power down */ 160 } 161 162 #ifdef CONFIG_LCD_IN_PSRAM 163 164 #define PSRAM_CRE_PIN AT91_PIO_PORTB, 29 165 #define PSRAM_CTRL_REG (PHYS_PSRAM + PHYS_PSRAM_SIZE - 2) 166 167 /* Initialize the PSRAM memory */ 168 static int pm9263_lcd_hw_psram_init(void) 169 { 170 volatile uint16_t x; 171 unsigned long csa; 172 at91_smc_t *smc = (at91_smc_t *) AT91_SMC1_BASE; 173 at91_matrix_t *matrix = (at91_matrix_t *) AT91_MATRIX_BASE; 174 175 /* Enable CS3 3.3v, no pull-ups */ 176 csa = readl(&matrix->csa[1]) | AT91_MATRIX_CSA_DBPUC | 177 AT91_MATRIX_CSA_VDDIOMSEL_3_3V; 178 179 writel(csa, &matrix->csa[1]); 180 181 /* Configure SMC1 CS0 for PSRAM - 16-bit */ 182 writel(AT91_SMC_SETUP_NWE(0) | AT91_SMC_SETUP_NCS_WR(0) | 183 AT91_SMC_SETUP_NRD(0) | AT91_SMC_SETUP_NCS_RD(0), 184 &smc->cs[0].setup); 185 186 writel(AT91_SMC_PULSE_NWE(7) | AT91_SMC_PULSE_NCS_WR(7) | 187 AT91_SMC_PULSE_NRD(2) | AT91_SMC_PULSE_NCS_RD(7), 188 &smc->cs[0].pulse); 189 190 writel(AT91_SMC_CYCLE_NWE(8) | AT91_SMC_CYCLE_NRD(8), 191 &smc->cs[0].cycle); 192 193 writel(AT91_SMC_MODE_DBW_16 | AT91_SMC_MODE_PMEN | AT91_SMC_MODE_PS_32, 194 &smc->cs[0].mode); 195 196 /* setup PB29 as output */ 197 at91_set_pio_output(PSRAM_CRE_PIN, 1); 198 199 at91_set_pio_value(PSRAM_CRE_PIN, 0); /* set PSRAM_CRE_PIN to '0' */ 200 201 /* PSRAM: write BCR */ 202 x = readw(PSRAM_CTRL_REG); 203 x = readw(PSRAM_CTRL_REG); 204 writew(1, PSRAM_CTRL_REG); /* 0 - RCR,1 - BCR */ 205 writew(0x9d4f, PSRAM_CTRL_REG); /* write the BCR */ 206 207 /* write RCR of the PSRAM */ 208 x = readw(PSRAM_CTRL_REG); 209 x = readw(PSRAM_CTRL_REG); 210 writew(0, PSRAM_CTRL_REG); /* 0 - RCR,1 - BCR */ 211 /* set RCR; 0x10-async mode,0x90-page mode */ 212 writew(0x90, PSRAM_CTRL_REG); 213 214 /* 215 * test to see if the PSRAM is MT45W2M16A or MT45W2M16B 216 * MT45W2M16B - CRE must be 0 217 * MT45W2M16A - CRE must be 1 218 */ 219 writew(0x1234, PHYS_PSRAM); 220 writew(0x5678, PHYS_PSRAM + 2); 221 222 /* test if the chip is MT45W2M16B */ 223 if ((readw(PHYS_PSRAM) != 0x1234) || (readw(PHYS_PSRAM+2) != 0x5678)) { 224 /* try with CRE=1 (MT45W2M16A) */ 225 at91_set_pio_value(PSRAM_CRE_PIN, 1); /* set PSRAM_CRE_PIN to '1' */ 226 227 /* write RCR of the PSRAM */ 228 x = readw(PSRAM_CTRL_REG); 229 x = readw(PSRAM_CTRL_REG); 230 writew(0, PSRAM_CTRL_REG); /* 0 - RCR,1 - BCR */ 231 /* set RCR;0x10-async mode,0x90-page mode */ 232 writew(0x90, PSRAM_CTRL_REG); 233 234 235 writew(0x1234, PHYS_PSRAM); 236 writew(0x5678, PHYS_PSRAM+2); 237 if ((readw(PHYS_PSRAM) != 0x1234) 238 || (readw(PHYS_PSRAM + 2) != 0x5678)) 239 return 1; 240 241 } 242 243 /* Bus matrix */ 244 writel(AT91_MATRIX_PRA_M5(3), &matrix->pr[5].a); 245 writel(CONFIG_PSRAM_SCFG, &matrix->scfg[5]); 246 247 return 0; 248 } 249 #endif 250 251 static void pm9263_lcd_hw_init(void) 252 { 253 at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE; 254 255 at91_set_a_periph(AT91_PIO_PORTC, 0, 0); /* LCDVSYNC */ 256 at91_set_a_periph(AT91_PIO_PORTC, 1, 0); /* LCDHSYNC */ 257 at91_set_a_periph(AT91_PIO_PORTC, 2, 0); /* LCDDOTCK */ 258 at91_set_a_periph(AT91_PIO_PORTC, 3, 0); /* LCDDEN */ 259 at91_set_b_periph(AT91_PIO_PORTB, 9, 0); /* LCDCC */ 260 at91_set_a_periph(AT91_PIO_PORTC, 6, 0); /* LCDD2 */ 261 at91_set_a_periph(AT91_PIO_PORTC, 7, 0); /* LCDD3 */ 262 at91_set_a_periph(AT91_PIO_PORTC, 8, 0); /* LCDD4 */ 263 at91_set_a_periph(AT91_PIO_PORTC, 9, 0); /* LCDD5 */ 264 at91_set_a_periph(AT91_PIO_PORTC, 10, 0); /* LCDD6 */ 265 at91_set_a_periph(AT91_PIO_PORTC, 11, 0); /* LCDD7 */ 266 at91_set_a_periph(AT91_PIO_PORTC, 14, 0); /* LCDD10 */ 267 at91_set_a_periph(AT91_PIO_PORTC, 15, 0); /* LCDD11 */ 268 at91_set_a_periph(AT91_PIO_PORTC, 16, 0); /* LCDD12 */ 269 at91_set_b_periph(AT91_PIO_PORTC, 12, 0); /* LCDD13 */ 270 at91_set_a_periph(AT91_PIO_PORTC, 18, 0); /* LCDD14 */ 271 at91_set_a_periph(AT91_PIO_PORTC, 19, 0); /* LCDD15 */ 272 at91_set_a_periph(AT91_PIO_PORTC, 22, 0); /* LCDD18 */ 273 at91_set_a_periph(AT91_PIO_PORTC, 23, 0); /* LCDD19 */ 274 at91_set_a_periph(AT91_PIO_PORTC, 24, 0); /* LCDD20 */ 275 at91_set_b_periph(AT91_PIO_PORTC, 17, 0); /* LCDD21 */ 276 at91_set_a_periph(AT91_PIO_PORTC, 26, 0); /* LCDD22 */ 277 at91_set_a_periph(AT91_PIO_PORTC, 27, 0); /* LCDD23 */ 278 279 writel(1 << AT91SAM9263_ID_LCDC, &pmc->pcer); 280 281 /* Power Control */ 282 at91_set_pio_output(AT91_PIO_PORTA, 22, 1); 283 at91_set_pio_value(AT91_PIO_PORTA, 22, 0); /* power down */ 284 285 #ifdef CONFIG_LCD_IN_PSRAM 286 /* initialize te PSRAM */ 287 int stat = pm9263_lcd_hw_psram_init(); 288 289 gd->fb_base = (stat == 0) ? PHYS_PSRAM : AT91SAM9263_SRAM0_BASE; 290 #else 291 gd->fb_base = AT91SAM9263_SRAM0_BASE; 292 #endif 293 294 } 295 296 #ifdef CONFIG_LCD_INFO 297 #include <nand.h> 298 #include <version.h> 299 300 extern flash_info_t flash_info[]; 301 302 void lcd_show_board_info(void) 303 { 304 ulong dram_size, nand_size, flash_size, dataflash_size; 305 int i; 306 char temp[32]; 307 308 lcd_printf ("%s\n", U_BOOT_VERSION); 309 lcd_printf ("(C) 2009 Ronetix GmbH\n"); 310 lcd_printf ("support@ronetix.at\n"); 311 lcd_printf ("%s CPU at %s MHz", 312 CONFIG_SYS_AT91_CPU_NAME, 313 strmhz(temp, get_cpu_clk_rate())); 314 315 dram_size = 0; 316 for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) 317 dram_size += gd->bd->bi_dram[i].size; 318 319 nand_size = 0; 320 for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++) 321 nand_size += nand_info[i].size; 322 323 flash_size = 0; 324 for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) 325 flash_size += flash_info[i].size; 326 327 dataflash_size = 0; 328 for (i = 0; i < CONFIG_SYS_MAX_DATAFLASH_BANKS; i++) 329 dataflash_size += (unsigned int) dataflash_info[i].Device.pages_number * 330 dataflash_info[i].Device.pages_size; 331 332 lcd_printf ("%ld MB SDRAM, %ld MB NAND\n%ld MB NOR Flash\n" 333 "4 MB PSRAM, %ld MB DataFlash\n", 334 dram_size >> 20, 335 nand_size >> 20, 336 flash_size >> 20, 337 dataflash_size >> 20); 338 } 339 #endif /* CONFIG_LCD_INFO */ 340 341 #endif /* CONFIG_LCD */ 342 343 int board_init(void) 344 { 345 at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE; 346 347 /* Enable Ctrlc */ 348 console_init_f(); 349 350 writel((1 << AT91SAM9263_ID_PIOA) | 351 (1 << AT91SAM9263_ID_PIOCDE) | 352 (1 << AT91SAM9263_ID_PIOB), 353 &pmc->pcer); 354 355 /* arch number of AT91SAM9263EK-Board */ 356 gd->bd->bi_arch_number = MACH_TYPE_PM9263; 357 358 /* adress of boot parameters */ 359 gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; 360 361 at91_serial_hw_init(); 362 #ifdef CONFIG_CMD_NAND 363 pm9263_nand_hw_init(); 364 #endif 365 #ifdef CONFIG_HAS_DATAFLASH 366 at91_spi0_hw_init(1 << 0); 367 #endif 368 #ifdef CONFIG_MACB 369 pm9263_macb_hw_init(); 370 #endif 371 #ifdef CONFIG_USB_OHCI_NEW 372 at91_uhp_hw_init(); 373 #endif 374 #ifdef CONFIG_LCD 375 pm9263_lcd_hw_init(); 376 #endif 377 return 0; 378 } 379 380 int dram_init(void) 381 { 382 gd->bd->bi_dram[0].start = PHYS_SDRAM; 383 gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE; 384 return 0; 385 } 386 387 #ifdef CONFIG_RESET_PHY_R 388 void reset_phy(void) 389 { 390 #ifdef CONFIG_MACB 391 /* 392 * Initialize ethernet HW addr prior to starting Linux, 393 * needed for nfsroot 394 */ 395 eth_init(gd->bd); 396 #endif 397 } 398 #endif 399 400 int board_eth_init(bd_t *bis) 401 { 402 int rc = 0; 403 #ifdef CONFIG_MACB 404 rc = macb_eth_initialize(0, (void *)AT91_EMAC_BASE, 0x01); 405 #endif 406 return rc; 407 } 408 409 #ifdef CONFIG_DISPLAY_BOARDINFO 410 int checkboard (void) 411 { 412 char *ss; 413 414 printf ("Board : Ronetix PM9263\n"); 415 416 switch (gd->fb_base) { 417 case PHYS_PSRAM: 418 ss = "(PSRAM)"; 419 break; 420 421 case AT91SAM9263_SRAM0_BASE: 422 ss = "(Internal SRAM)"; 423 break; 424 425 default: 426 ss = ""; 427 break; 428 } 429 printf("Video memory : 0x%08lX %s\n", gd->fb_base, ss ); 430 431 printf ("\n"); 432 return 0; 433 } 434 #endif 435