1 /* 2 * (C) Copyright 2007-2008 3 * Stelian Pop <stelian.pop@leadtechdesign.com> 4 * Lead Tech Design <www.leadtechdesign.com> 5 * Copyright (C) 2008 Ronetix Ilko Iliev (www.ronetix.at) 6 * Copyright (C) 2009 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> 7 * 8 * See file CREDITS for list of people who contributed to this 9 * project. 10 * 11 * This program is free software; you can redistribute it and/or 12 * modify it under the terms of the GNU General Public License as 13 * published by the Free Software Foundation; either version 2 of 14 * the License, or (at your option) any later version. 15 * 16 * This program is distributed in the hope that it will be useful, 17 * but WITHOUT ANY WARRANTY; without even the implied warranty of 18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 19 * GNU General Public License for more details. 20 * 21 * You should have received a copy of the GNU General Public License 22 * along with this program; if not, write to the Free Software 23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 24 * MA 02111-1307 USA 25 */ 26 27 #include <common.h> 28 #include <asm/sizes.h> 29 #include <asm/io.h> 30 #include <asm/arch/at91sam9_smc.h> 31 #include <asm/arch/at91_common.h> 32 #include <asm/arch/at91_pmc.h> 33 #include <asm/arch/at91_rstc.h> 34 #include <asm/arch/at91_matrix.h> 35 #include <asm/arch/clk.h> 36 #include <asm/arch/gpio.h> 37 #include <lcd.h> 38 #include <atmel_lcdc.h> 39 #include <dataflash.h> 40 #if defined(CONFIG_RESET_PHY_R) && defined(CONFIG_MACB) 41 #include <net.h> 42 #endif 43 #include <netdev.h> 44 45 DECLARE_GLOBAL_DATA_PTR; 46 47 /* ------------------------------------------------------------------------- */ 48 /* 49 * Miscelaneous platform dependent initialisations 50 */ 51 52 #ifdef CONFIG_CMD_NAND 53 static void pm9263_nand_hw_init(void) 54 { 55 unsigned long csa; 56 struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC0; 57 struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX; 58 59 /* Enable CS3 */ 60 csa = readl(&matrix->csa[0]) | AT91_MATRIX_CSA_EBI_CS3A; 61 writel(csa, &matrix->csa[0]); 62 63 /* Configure SMC CS3 for NAND/SmartMedia */ 64 writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(1) | 65 AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(1), 66 &smc->cs[3].setup); 67 68 writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(3) | 69 AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(3), 70 &smc->cs[3].pulse); 71 72 writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(5), 73 &smc->cs[3].cycle); 74 75 writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE | 76 AT91_SMC_MODE_EXNW_DISABLE | 77 #ifdef CONFIG_SYS_NAND_DBW_16 78 AT91_SMC_MODE_DBW_16 | 79 #else /* CONFIG_SYS_NAND_DBW_8 */ 80 AT91_SMC_MODE_DBW_8 | 81 #endif 82 AT91_SMC_MODE_TDF_CYCLE(2), 83 &smc->cs[3].mode); 84 85 /* Configure RDY/BSY */ 86 at91_set_pio_input(CONFIG_SYS_NAND_READY_PIN, 1); 87 88 /* Enable NandFlash */ 89 at91_set_pio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1); 90 } 91 #endif 92 93 #ifdef CONFIG_MACB 94 static void pm9263_macb_hw_init(void) 95 { 96 struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; 97 98 /* 99 * PB27 enables the 50MHz oscillator for Ethernet PHY 100 * 1 - enable 101 * 0 - disable 102 */ 103 at91_set_pio_output(AT91_PIO_PORTB, 27, 1); 104 at91_set_pio_value(AT91_PIO_PORTB, 27, 1); /* 1- enable, 0 - disable */ 105 106 /* Enable clock */ 107 writel(1 << ATMEL_ID_EMAC, &pmc->pcer); 108 109 /* 110 * Disable pull-up on: 111 * RXDV (PC25) => PHY normal mode (not Test mode) 112 * ERX0 (PE25) => PHY ADDR0 113 * ERX1 (PE26) => PHY ADDR1 => PHYADDR = 0x0 114 * 115 * PHY has internal pull-down 116 */ 117 118 at91_set_pio_pullup(AT91_PIO_PORTC, 25, 0); 119 at91_set_pio_pullup(AT91_PIO_PORTE, 25, 0); 120 at91_set_pio_pullup(AT91_PIO_PORTE, 26, 0); 121 122 /* Re-enable pull-up */ 123 at91_set_pio_pullup(AT91_PIO_PORTC, 25, 1); 124 at91_set_pio_pullup(AT91_PIO_PORTE, 25, 1); 125 at91_set_pio_pullup(AT91_PIO_PORTE, 26, 1); 126 127 at91_macb_hw_init(); 128 } 129 #endif 130 131 #ifdef CONFIG_LCD 132 vidinfo_t panel_info = { 133 vl_col: 240, 134 vl_row: 320, 135 vl_clk: 4965000, 136 vl_sync: ATMEL_LCDC_INVLINE_INVERTED | 137 ATMEL_LCDC_INVFRAME_INVERTED, 138 vl_bpix: 3, 139 vl_tft: 1, 140 vl_hsync_len: 5, 141 vl_left_margin: 1, 142 vl_right_margin:33, 143 vl_vsync_len: 1, 144 vl_upper_margin:1, 145 vl_lower_margin:0, 146 mmio: ATMEL_BASE_LCDC, 147 }; 148 149 void lcd_enable(void) 150 { 151 at91_set_pio_value(AT91_PIO_PORTA, 22, 1); /* power up */ 152 } 153 154 void lcd_disable(void) 155 { 156 at91_set_pio_value(AT91_PIO_PORTA, 22, 0); /* power down */ 157 } 158 159 #ifdef CONFIG_LCD_IN_PSRAM 160 161 #define PSRAM_CRE_PIN AT91_PIO_PORTB, 29 162 #define PSRAM_CTRL_REG (PHYS_PSRAM + PHYS_PSRAM_SIZE - 2) 163 164 /* Initialize the PSRAM memory */ 165 static int pm9263_lcd_hw_psram_init(void) 166 { 167 volatile uint16_t x; 168 unsigned long csa; 169 struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC1; 170 struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX; 171 172 /* Enable CS3 3.3v, no pull-ups */ 173 csa = readl(&matrix->csa[1]) | AT91_MATRIX_CSA_DBPUC | 174 AT91_MATRIX_CSA_VDDIOMSEL_3_3V; 175 176 writel(csa, &matrix->csa[1]); 177 178 /* Configure SMC1 CS0 for PSRAM - 16-bit */ 179 writel(AT91_SMC_SETUP_NWE(0) | AT91_SMC_SETUP_NCS_WR(0) | 180 AT91_SMC_SETUP_NRD(0) | AT91_SMC_SETUP_NCS_RD(0), 181 &smc->cs[0].setup); 182 183 writel(AT91_SMC_PULSE_NWE(7) | AT91_SMC_PULSE_NCS_WR(7) | 184 AT91_SMC_PULSE_NRD(2) | AT91_SMC_PULSE_NCS_RD(7), 185 &smc->cs[0].pulse); 186 187 writel(AT91_SMC_CYCLE_NWE(8) | AT91_SMC_CYCLE_NRD(8), 188 &smc->cs[0].cycle); 189 190 writel(AT91_SMC_MODE_DBW_16 | AT91_SMC_MODE_PMEN | AT91_SMC_MODE_PS_32, 191 &smc->cs[0].mode); 192 193 /* setup PB29 as output */ 194 at91_set_pio_output(PSRAM_CRE_PIN, 1); 195 196 at91_set_pio_value(PSRAM_CRE_PIN, 0); /* set PSRAM_CRE_PIN to '0' */ 197 198 /* PSRAM: write BCR */ 199 x = readw(PSRAM_CTRL_REG); 200 x = readw(PSRAM_CTRL_REG); 201 writew(1, PSRAM_CTRL_REG); /* 0 - RCR,1 - BCR */ 202 writew(0x9d4f, PSRAM_CTRL_REG); /* write the BCR */ 203 204 /* write RCR of the PSRAM */ 205 x = readw(PSRAM_CTRL_REG); 206 x = readw(PSRAM_CTRL_REG); 207 writew(0, PSRAM_CTRL_REG); /* 0 - RCR,1 - BCR */ 208 /* set RCR; 0x10-async mode,0x90-page mode */ 209 writew(0x90, PSRAM_CTRL_REG); 210 211 /* 212 * test to see if the PSRAM is MT45W2M16A or MT45W2M16B 213 * MT45W2M16B - CRE must be 0 214 * MT45W2M16A - CRE must be 1 215 */ 216 writew(0x1234, PHYS_PSRAM); 217 writew(0x5678, PHYS_PSRAM + 2); 218 219 /* test if the chip is MT45W2M16B */ 220 if ((readw(PHYS_PSRAM) != 0x1234) || (readw(PHYS_PSRAM+2) != 0x5678)) { 221 /* try with CRE=1 (MT45W2M16A) */ 222 at91_set_pio_value(PSRAM_CRE_PIN, 1); /* set PSRAM_CRE_PIN to '1' */ 223 224 /* write RCR of the PSRAM */ 225 x = readw(PSRAM_CTRL_REG); 226 x = readw(PSRAM_CTRL_REG); 227 writew(0, PSRAM_CTRL_REG); /* 0 - RCR,1 - BCR */ 228 /* set RCR;0x10-async mode,0x90-page mode */ 229 writew(0x90, PSRAM_CTRL_REG); 230 231 232 writew(0x1234, PHYS_PSRAM); 233 writew(0x5678, PHYS_PSRAM+2); 234 if ((readw(PHYS_PSRAM) != 0x1234) 235 || (readw(PHYS_PSRAM + 2) != 0x5678)) 236 return 1; 237 238 } 239 240 /* Bus matrix */ 241 writel(AT91_MATRIX_PRA_M5(3), &matrix->pr[5].a); 242 writel(CONFIG_PSRAM_SCFG, &matrix->scfg[5]); 243 244 return 0; 245 } 246 #endif 247 248 static void pm9263_lcd_hw_init(void) 249 { 250 struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; 251 252 at91_set_a_periph(AT91_PIO_PORTC, 0, 0); /* LCDVSYNC */ 253 at91_set_a_periph(AT91_PIO_PORTC, 1, 0); /* LCDHSYNC */ 254 at91_set_a_periph(AT91_PIO_PORTC, 2, 0); /* LCDDOTCK */ 255 at91_set_a_periph(AT91_PIO_PORTC, 3, 0); /* LCDDEN */ 256 at91_set_b_periph(AT91_PIO_PORTB, 9, 0); /* LCDCC */ 257 at91_set_a_periph(AT91_PIO_PORTC, 6, 0); /* LCDD2 */ 258 at91_set_a_periph(AT91_PIO_PORTC, 7, 0); /* LCDD3 */ 259 at91_set_a_periph(AT91_PIO_PORTC, 8, 0); /* LCDD4 */ 260 at91_set_a_periph(AT91_PIO_PORTC, 9, 0); /* LCDD5 */ 261 at91_set_a_periph(AT91_PIO_PORTC, 10, 0); /* LCDD6 */ 262 at91_set_a_periph(AT91_PIO_PORTC, 11, 0); /* LCDD7 */ 263 at91_set_a_periph(AT91_PIO_PORTC, 14, 0); /* LCDD10 */ 264 at91_set_a_periph(AT91_PIO_PORTC, 15, 0); /* LCDD11 */ 265 at91_set_a_periph(AT91_PIO_PORTC, 16, 0); /* LCDD12 */ 266 at91_set_b_periph(AT91_PIO_PORTC, 12, 0); /* LCDD13 */ 267 at91_set_a_periph(AT91_PIO_PORTC, 18, 0); /* LCDD14 */ 268 at91_set_a_periph(AT91_PIO_PORTC, 19, 0); /* LCDD15 */ 269 at91_set_a_periph(AT91_PIO_PORTC, 22, 0); /* LCDD18 */ 270 at91_set_a_periph(AT91_PIO_PORTC, 23, 0); /* LCDD19 */ 271 at91_set_a_periph(AT91_PIO_PORTC, 24, 0); /* LCDD20 */ 272 at91_set_b_periph(AT91_PIO_PORTC, 17, 0); /* LCDD21 */ 273 at91_set_a_periph(AT91_PIO_PORTC, 26, 0); /* LCDD22 */ 274 at91_set_a_periph(AT91_PIO_PORTC, 27, 0); /* LCDD23 */ 275 276 writel(1 << ATMEL_ID_LCDC, &pmc->pcer); 277 278 /* Power Control */ 279 at91_set_pio_output(AT91_PIO_PORTA, 22, 1); 280 at91_set_pio_value(AT91_PIO_PORTA, 22, 0); /* power down */ 281 282 #ifdef CONFIG_LCD_IN_PSRAM 283 /* initialize te PSRAM */ 284 int stat = pm9263_lcd_hw_psram_init(); 285 286 gd->fb_base = (stat == 0) ? PHYS_PSRAM : ATMEL_BASE_SRAM0; 287 #else 288 gd->fb_base = ATMEL_BASE_SRAM0; 289 #endif 290 291 } 292 293 #ifdef CONFIG_LCD_INFO 294 #include <nand.h> 295 #include <version.h> 296 297 extern flash_info_t flash_info[]; 298 299 void lcd_show_board_info(void) 300 { 301 ulong dram_size, nand_size, flash_size, dataflash_size; 302 int i; 303 char temp[32]; 304 305 lcd_printf ("%s\n", U_BOOT_VERSION); 306 lcd_printf ("(C) 2009 Ronetix GmbH\n"); 307 lcd_printf ("support@ronetix.at\n"); 308 lcd_printf ("%s CPU at %s MHz", 309 CONFIG_SYS_AT91_CPU_NAME, 310 strmhz(temp, get_cpu_clk_rate())); 311 312 dram_size = 0; 313 for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) 314 dram_size += gd->bd->bi_dram[i].size; 315 316 nand_size = 0; 317 for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++) 318 nand_size += nand_info[i].size; 319 320 flash_size = 0; 321 for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) 322 flash_size += flash_info[i].size; 323 324 dataflash_size = 0; 325 for (i = 0; i < CONFIG_SYS_MAX_DATAFLASH_BANKS; i++) 326 dataflash_size += (unsigned int) dataflash_info[i].Device.pages_number * 327 dataflash_info[i].Device.pages_size; 328 329 lcd_printf ("%ld MB SDRAM, %ld MB NAND\n%ld MB NOR Flash\n" 330 "4 MB PSRAM, %ld MB DataFlash\n", 331 dram_size >> 20, 332 nand_size >> 20, 333 flash_size >> 20, 334 dataflash_size >> 20); 335 } 336 #endif /* CONFIG_LCD_INFO */ 337 338 #endif /* CONFIG_LCD */ 339 340 int board_init(void) 341 { 342 struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; 343 344 /* Enable Ctrlc */ 345 console_init_f(); 346 347 writel((1 << ATMEL_ID_PIOA) | 348 (1 << ATMEL_ID_PIOCDE) | 349 (1 << ATMEL_ID_PIOB), 350 &pmc->pcer); 351 352 /* arch number of AT91SAM9263EK-Board */ 353 gd->bd->bi_arch_number = MACH_TYPE_PM9263; 354 355 /* adress of boot parameters */ 356 gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; 357 358 at91_seriald_hw_init(); 359 #ifdef CONFIG_CMD_NAND 360 pm9263_nand_hw_init(); 361 #endif 362 #ifdef CONFIG_HAS_DATAFLASH 363 at91_spi0_hw_init(1 << 0); 364 #endif 365 #ifdef CONFIG_MACB 366 pm9263_macb_hw_init(); 367 #endif 368 #ifdef CONFIG_USB_OHCI_NEW 369 at91_uhp_hw_init(); 370 #endif 371 #ifdef CONFIG_LCD 372 pm9263_lcd_hw_init(); 373 #endif 374 return 0; 375 } 376 377 int dram_init(void) 378 { 379 /* dram_init must store complete ramsize in gd->ram_size */ 380 gd->ram_size = get_ram_size((void *)PHYS_SDRAM, 381 PHYS_SDRAM_SIZE); 382 return 0; 383 } 384 385 void dram_init_banksize(void) 386 { 387 gd->bd->bi_dram[0].start = PHYS_SDRAM; 388 gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE; 389 } 390 391 #ifdef CONFIG_RESET_PHY_R 392 void reset_phy(void) 393 { 394 } 395 #endif 396 397 int board_eth_init(bd_t *bis) 398 { 399 int rc = 0; 400 #ifdef CONFIG_MACB 401 rc = macb_eth_initialize(0, (void *)ATMEL_BASE_EMAC, 0x01); 402 #endif 403 return rc; 404 } 405 406 #ifdef CONFIG_DISPLAY_BOARDINFO 407 int checkboard (void) 408 { 409 char *ss; 410 411 printf ("Board : Ronetix PM9263\n"); 412 413 switch (gd->fb_base) { 414 case PHYS_PSRAM: 415 ss = "(PSRAM)"; 416 break; 417 418 case ATMEL_BASE_SRAM0: 419 ss = "(Internal SRAM)"; 420 break; 421 422 default: 423 ss = ""; 424 break; 425 } 426 printf("Video memory : 0x%08lX %s\n", gd->fb_base, ss ); 427 428 printf ("\n"); 429 return 0; 430 } 431 #endif 432