1f0a2c7b4SIlko Iliev /* 2f0a2c7b4SIlko Iliev * (C) Copyright 2007-2008 3c9e798d3SStelian Pop * Stelian Pop <stelian@popies.net> 4f0a2c7b4SIlko Iliev * Lead Tech Design <www.leadtechdesign.com> 5f0a2c7b4SIlko Iliev * Copyright (C) 2008 Ronetix Ilko Iliev (www.ronetix.at) 6f0a2c7b4SIlko Iliev * Copyright (C) 2009 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> 7f0a2c7b4SIlko Iliev * 81a459660SWolfgang Denk * SPDX-License-Identifier: GPL-2.0+ 9f0a2c7b4SIlko Iliev */ 10f0a2c7b4SIlko Iliev 11f0a2c7b4SIlko Iliev #include <common.h> 121ace4022SAlexey Brodkin #include <linux/sizes.h> 13684a567aSAsen Dimov #include <asm/io.h> 14ac45bb16SAndreas Bießmann #include <asm/gpio.h> 15f0a2c7b4SIlko Iliev #include <asm/arch/at91sam9_smc.h> 16f0a2c7b4SIlko Iliev #include <asm/arch/at91_common.h> 17f0a2c7b4SIlko Iliev #include <asm/arch/at91_rstc.h> 1820d98c2cSAsen Dimov #include <asm/arch/at91_matrix.h> 19f0a2c7b4SIlko Iliev #include <asm/arch/clk.h> 20684a567aSAsen Dimov #include <asm/arch/gpio.h> 21f0a2c7b4SIlko Iliev #include <lcd.h> 22f0a2c7b4SIlko Iliev #include <atmel_lcdc.h> 23f0a2c7b4SIlko Iliev #include <dataflash.h> 24f0a2c7b4SIlko Iliev #if defined(CONFIG_RESET_PHY_R) && defined(CONFIG_MACB) 25f0a2c7b4SIlko Iliev #include <net.h> 26f0a2c7b4SIlko Iliev #endif 27f0a2c7b4SIlko Iliev #include <netdev.h> 28f0a2c7b4SIlko Iliev 29f0a2c7b4SIlko Iliev DECLARE_GLOBAL_DATA_PTR; 30f0a2c7b4SIlko Iliev 31f0a2c7b4SIlko Iliev /* ------------------------------------------------------------------------- */ 32f0a2c7b4SIlko Iliev /* 33f0a2c7b4SIlko Iliev * Miscelaneous platform dependent initialisations 34f0a2c7b4SIlko Iliev */ 35f0a2c7b4SIlko Iliev 36f0a2c7b4SIlko Iliev #ifdef CONFIG_CMD_NAND 37f0a2c7b4SIlko Iliev static void pm9263_nand_hw_init(void) 38f0a2c7b4SIlko Iliev { 39f0a2c7b4SIlko Iliev unsigned long csa; 40684a567aSAsen Dimov struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC0; 41684a567aSAsen Dimov struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX; 42f0a2c7b4SIlko Iliev 43f0a2c7b4SIlko Iliev /* Enable CS3 */ 4420d98c2cSAsen Dimov csa = readl(&matrix->csa[0]) | AT91_MATRIX_CSA_EBI_CS3A; 4520d98c2cSAsen Dimov writel(csa, &matrix->csa[0]); 46f0a2c7b4SIlko Iliev 47f0a2c7b4SIlko Iliev /* Configure SMC CS3 for NAND/SmartMedia */ 4820d98c2cSAsen Dimov writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(1) | 4920d98c2cSAsen Dimov AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(1), 5020d98c2cSAsen Dimov &smc->cs[3].setup); 5120d98c2cSAsen Dimov 5220d98c2cSAsen Dimov writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(3) | 5320d98c2cSAsen Dimov AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(3), 5420d98c2cSAsen Dimov &smc->cs[3].pulse); 5520d98c2cSAsen Dimov 5620d98c2cSAsen Dimov writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(5), 5720d98c2cSAsen Dimov &smc->cs[3].cycle); 5820d98c2cSAsen Dimov 5920d98c2cSAsen Dimov writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE | 6020d98c2cSAsen Dimov AT91_SMC_MODE_EXNW_DISABLE | 61f0a2c7b4SIlko Iliev #ifdef CONFIG_SYS_NAND_DBW_16 6220d98c2cSAsen Dimov AT91_SMC_MODE_DBW_16 | 63f0a2c7b4SIlko Iliev #else /* CONFIG_SYS_NAND_DBW_8 */ 6420d98c2cSAsen Dimov AT91_SMC_MODE_DBW_8 | 65f0a2c7b4SIlko Iliev #endif 6620d98c2cSAsen Dimov AT91_SMC_MODE_TDF_CYCLE(2), 6720d98c2cSAsen Dimov &smc->cs[3].mode); 68f0a2c7b4SIlko Iliev 69f0a2c7b4SIlko Iliev /* Configure RDY/BSY */ 70ac45bb16SAndreas Bießmann gpio_direction_input(CONFIG_SYS_NAND_READY_PIN); 71f0a2c7b4SIlko Iliev 72f0a2c7b4SIlko Iliev /* Enable NandFlash */ 73ac45bb16SAndreas Bießmann gpio_direction_output(CONFIG_SYS_NAND_ENABLE_PIN, 1); 74f0a2c7b4SIlko Iliev } 75f0a2c7b4SIlko Iliev #endif 76f0a2c7b4SIlko Iliev 77f0a2c7b4SIlko Iliev #ifdef CONFIG_MACB 78f0a2c7b4SIlko Iliev static void pm9263_macb_hw_init(void) 79f0a2c7b4SIlko Iliev { 80f0a2c7b4SIlko Iliev /* 81f0a2c7b4SIlko Iliev * PB27 enables the 50MHz oscillator for Ethernet PHY 82f0a2c7b4SIlko Iliev * 1 - enable 83f0a2c7b4SIlko Iliev * 0 - disable 84f0a2c7b4SIlko Iliev */ 8520d98c2cSAsen Dimov at91_set_pio_output(AT91_PIO_PORTB, 27, 1); 8620d98c2cSAsen Dimov at91_set_pio_value(AT91_PIO_PORTB, 27, 1); /* 1- enable, 0 - disable */ 87f0a2c7b4SIlko Iliev 8870341e2eSWenyou Yang at91_periph_clk_enable(ATMEL_ID_EMAC); 89f0a2c7b4SIlko Iliev 90f0a2c7b4SIlko Iliev /* 91f0a2c7b4SIlko Iliev * Disable pull-up on: 92f0a2c7b4SIlko Iliev * RXDV (PC25) => PHY normal mode (not Test mode) 93f0a2c7b4SIlko Iliev * ERX0 (PE25) => PHY ADDR0 94f0a2c7b4SIlko Iliev * ERX1 (PE26) => PHY ADDR1 => PHYADDR = 0x0 95f0a2c7b4SIlko Iliev * 96f0a2c7b4SIlko Iliev * PHY has internal pull-down 97f0a2c7b4SIlko Iliev */ 98f0a2c7b4SIlko Iliev 9920d98c2cSAsen Dimov at91_set_pio_pullup(AT91_PIO_PORTC, 25, 0); 10020d98c2cSAsen Dimov at91_set_pio_pullup(AT91_PIO_PORTE, 25, 0); 10120d98c2cSAsen Dimov at91_set_pio_pullup(AT91_PIO_PORTE, 26, 0); 102f0a2c7b4SIlko Iliev 103f0a2c7b4SIlko Iliev /* Re-enable pull-up */ 10420d98c2cSAsen Dimov at91_set_pio_pullup(AT91_PIO_PORTC, 25, 1); 10520d98c2cSAsen Dimov at91_set_pio_pullup(AT91_PIO_PORTE, 25, 1); 10620d98c2cSAsen Dimov at91_set_pio_pullup(AT91_PIO_PORTE, 26, 1); 107f0a2c7b4SIlko Iliev 108f0a2c7b4SIlko Iliev at91_macb_hw_init(); 109f0a2c7b4SIlko Iliev } 110f0a2c7b4SIlko Iliev #endif 111f0a2c7b4SIlko Iliev 112f0a2c7b4SIlko Iliev #ifdef CONFIG_LCD 113f0a2c7b4SIlko Iliev vidinfo_t panel_info = { 1141b34e880SJeroen Hofstee .vl_col = 240, 1151b34e880SJeroen Hofstee .vl_row = 320, 1161b34e880SJeroen Hofstee .vl_clk = 4965000, 1171b34e880SJeroen Hofstee .vl_sync = ATMEL_LCDC_INVLINE_INVERTED | 118f0a2c7b4SIlko Iliev ATMEL_LCDC_INVFRAME_INVERTED, 1191b34e880SJeroen Hofstee .vl_bpix = 3, 1201b34e880SJeroen Hofstee .vl_tft = 1, 1211b34e880SJeroen Hofstee .vl_hsync_len = 5, 1221b34e880SJeroen Hofstee .vl_left_margin = 1, 1231b34e880SJeroen Hofstee .vl_right_margin = 33, 1241b34e880SJeroen Hofstee .vl_vsync_len = 1, 1251b34e880SJeroen Hofstee .vl_upper_margin = 1, 1261b34e880SJeroen Hofstee .vl_lower_margin = 0, 1271b34e880SJeroen Hofstee .mmio = ATMEL_BASE_LCDC, 128f0a2c7b4SIlko Iliev }; 129f0a2c7b4SIlko Iliev 130f0a2c7b4SIlko Iliev void lcd_enable(void) 131f0a2c7b4SIlko Iliev { 13220d98c2cSAsen Dimov at91_set_pio_value(AT91_PIO_PORTA, 22, 1); /* power up */ 133f0a2c7b4SIlko Iliev } 134f0a2c7b4SIlko Iliev 135f0a2c7b4SIlko Iliev void lcd_disable(void) 136f0a2c7b4SIlko Iliev { 13720d98c2cSAsen Dimov at91_set_pio_value(AT91_PIO_PORTA, 22, 0); /* power down */ 138f0a2c7b4SIlko Iliev } 139f0a2c7b4SIlko Iliev 140f0a2c7b4SIlko Iliev #ifdef CONFIG_LCD_IN_PSRAM 141f0a2c7b4SIlko Iliev 14220d98c2cSAsen Dimov #define PSRAM_CRE_PIN AT91_PIO_PORTB, 29 143f0a2c7b4SIlko Iliev #define PSRAM_CTRL_REG (PHYS_PSRAM + PHYS_PSRAM_SIZE - 2) 144f0a2c7b4SIlko Iliev 145f0a2c7b4SIlko Iliev /* Initialize the PSRAM memory */ 146f0a2c7b4SIlko Iliev static int pm9263_lcd_hw_psram_init(void) 147f0a2c7b4SIlko Iliev { 1487a11c7f9SJean-Christophe PLAGNIOL-VILLARD unsigned long csa; 149684a567aSAsen Dimov struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC1; 150684a567aSAsen Dimov struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX; 1517a11c7f9SJean-Christophe PLAGNIOL-VILLARD 1527a11c7f9SJean-Christophe PLAGNIOL-VILLARD /* Enable CS3 3.3v, no pull-ups */ 15320d98c2cSAsen Dimov csa = readl(&matrix->csa[1]) | AT91_MATRIX_CSA_DBPUC | 15420d98c2cSAsen Dimov AT91_MATRIX_CSA_VDDIOMSEL_3_3V; 15520d98c2cSAsen Dimov 15620d98c2cSAsen Dimov writel(csa, &matrix->csa[1]); 1577a11c7f9SJean-Christophe PLAGNIOL-VILLARD 1587a11c7f9SJean-Christophe PLAGNIOL-VILLARD /* Configure SMC1 CS0 for PSRAM - 16-bit */ 15920d98c2cSAsen Dimov writel(AT91_SMC_SETUP_NWE(0) | AT91_SMC_SETUP_NCS_WR(0) | 16020d98c2cSAsen Dimov AT91_SMC_SETUP_NRD(0) | AT91_SMC_SETUP_NCS_RD(0), 16120d98c2cSAsen Dimov &smc->cs[0].setup); 16220d98c2cSAsen Dimov 16320d98c2cSAsen Dimov writel(AT91_SMC_PULSE_NWE(7) | AT91_SMC_PULSE_NCS_WR(7) | 16420d98c2cSAsen Dimov AT91_SMC_PULSE_NRD(2) | AT91_SMC_PULSE_NCS_RD(7), 16520d98c2cSAsen Dimov &smc->cs[0].pulse); 16620d98c2cSAsen Dimov 16720d98c2cSAsen Dimov writel(AT91_SMC_CYCLE_NWE(8) | AT91_SMC_CYCLE_NRD(8), 16820d98c2cSAsen Dimov &smc->cs[0].cycle); 16920d98c2cSAsen Dimov 17020d98c2cSAsen Dimov writel(AT91_SMC_MODE_DBW_16 | AT91_SMC_MODE_PMEN | AT91_SMC_MODE_PS_32, 17120d98c2cSAsen Dimov &smc->cs[0].mode); 172f0a2c7b4SIlko Iliev 173f0a2c7b4SIlko Iliev /* setup PB29 as output */ 17420d98c2cSAsen Dimov at91_set_pio_output(PSRAM_CRE_PIN, 1); 175f0a2c7b4SIlko Iliev 17620d98c2cSAsen Dimov at91_set_pio_value(PSRAM_CRE_PIN, 0); /* set PSRAM_CRE_PIN to '0' */ 177f0a2c7b4SIlko Iliev 178f0a2c7b4SIlko Iliev /* PSRAM: write BCR */ 1790a59b711SAnatolij Gustschin readw(PSRAM_CTRL_REG); 1800a59b711SAnatolij Gustschin readw(PSRAM_CTRL_REG); 181f0a2c7b4SIlko Iliev writew(1, PSRAM_CTRL_REG); /* 0 - RCR,1 - BCR */ 182f0a2c7b4SIlko Iliev writew(0x9d4f, PSRAM_CTRL_REG); /* write the BCR */ 183f0a2c7b4SIlko Iliev 184f0a2c7b4SIlko Iliev /* write RCR of the PSRAM */ 1850a59b711SAnatolij Gustschin readw(PSRAM_CTRL_REG); 1860a59b711SAnatolij Gustschin readw(PSRAM_CTRL_REG); 187f0a2c7b4SIlko Iliev writew(0, PSRAM_CTRL_REG); /* 0 - RCR,1 - BCR */ 188f0a2c7b4SIlko Iliev /* set RCR; 0x10-async mode,0x90-page mode */ 189f0a2c7b4SIlko Iliev writew(0x90, PSRAM_CTRL_REG); 190f0a2c7b4SIlko Iliev 191f0a2c7b4SIlko Iliev /* 192f0a2c7b4SIlko Iliev * test to see if the PSRAM is MT45W2M16A or MT45W2M16B 193f0a2c7b4SIlko Iliev * MT45W2M16B - CRE must be 0 194f0a2c7b4SIlko Iliev * MT45W2M16A - CRE must be 1 195f0a2c7b4SIlko Iliev */ 196f0a2c7b4SIlko Iliev writew(0x1234, PHYS_PSRAM); 197f0a2c7b4SIlko Iliev writew(0x5678, PHYS_PSRAM + 2); 198f0a2c7b4SIlko Iliev 199f0a2c7b4SIlko Iliev /* test if the chip is MT45W2M16B */ 200f0a2c7b4SIlko Iliev if ((readw(PHYS_PSRAM) != 0x1234) || (readw(PHYS_PSRAM+2) != 0x5678)) { 201f0a2c7b4SIlko Iliev /* try with CRE=1 (MT45W2M16A) */ 20220d98c2cSAsen Dimov at91_set_pio_value(PSRAM_CRE_PIN, 1); /* set PSRAM_CRE_PIN to '1' */ 203f0a2c7b4SIlko Iliev 204f0a2c7b4SIlko Iliev /* write RCR of the PSRAM */ 2050a59b711SAnatolij Gustschin readw(PSRAM_CTRL_REG); 2060a59b711SAnatolij Gustschin readw(PSRAM_CTRL_REG); 207f0a2c7b4SIlko Iliev writew(0, PSRAM_CTRL_REG); /* 0 - RCR,1 - BCR */ 208f0a2c7b4SIlko Iliev /* set RCR;0x10-async mode,0x90-page mode */ 209f0a2c7b4SIlko Iliev writew(0x90, PSRAM_CTRL_REG); 210f0a2c7b4SIlko Iliev 211f0a2c7b4SIlko Iliev 212f0a2c7b4SIlko Iliev writew(0x1234, PHYS_PSRAM); 213f0a2c7b4SIlko Iliev writew(0x5678, PHYS_PSRAM+2); 214f0a2c7b4SIlko Iliev if ((readw(PHYS_PSRAM) != 0x1234) 215f0a2c7b4SIlko Iliev || (readw(PHYS_PSRAM + 2) != 0x5678)) 216f0a2c7b4SIlko Iliev return 1; 217f0a2c7b4SIlko Iliev 218f0a2c7b4SIlko Iliev } 219f0a2c7b4SIlko Iliev 220f0a2c7b4SIlko Iliev /* Bus matrix */ 22120d98c2cSAsen Dimov writel(AT91_MATRIX_PRA_M5(3), &matrix->pr[5].a); 22220d98c2cSAsen Dimov writel(CONFIG_PSRAM_SCFG, &matrix->scfg[5]); 223f0a2c7b4SIlko Iliev 224f0a2c7b4SIlko Iliev return 0; 225f0a2c7b4SIlko Iliev } 226f0a2c7b4SIlko Iliev #endif 227f0a2c7b4SIlko Iliev 228f0a2c7b4SIlko Iliev static void pm9263_lcd_hw_init(void) 229f0a2c7b4SIlko Iliev { 23020d98c2cSAsen Dimov at91_set_a_periph(AT91_PIO_PORTC, 0, 0); /* LCDVSYNC */ 23120d98c2cSAsen Dimov at91_set_a_periph(AT91_PIO_PORTC, 1, 0); /* LCDHSYNC */ 23220d98c2cSAsen Dimov at91_set_a_periph(AT91_PIO_PORTC, 2, 0); /* LCDDOTCK */ 23320d98c2cSAsen Dimov at91_set_a_periph(AT91_PIO_PORTC, 3, 0); /* LCDDEN */ 23420d98c2cSAsen Dimov at91_set_b_periph(AT91_PIO_PORTB, 9, 0); /* LCDCC */ 23520d98c2cSAsen Dimov at91_set_a_periph(AT91_PIO_PORTC, 6, 0); /* LCDD2 */ 23620d98c2cSAsen Dimov at91_set_a_periph(AT91_PIO_PORTC, 7, 0); /* LCDD3 */ 23720d98c2cSAsen Dimov at91_set_a_periph(AT91_PIO_PORTC, 8, 0); /* LCDD4 */ 23820d98c2cSAsen Dimov at91_set_a_periph(AT91_PIO_PORTC, 9, 0); /* LCDD5 */ 23920d98c2cSAsen Dimov at91_set_a_periph(AT91_PIO_PORTC, 10, 0); /* LCDD6 */ 24020d98c2cSAsen Dimov at91_set_a_periph(AT91_PIO_PORTC, 11, 0); /* LCDD7 */ 24120d98c2cSAsen Dimov at91_set_a_periph(AT91_PIO_PORTC, 14, 0); /* LCDD10 */ 24220d98c2cSAsen Dimov at91_set_a_periph(AT91_PIO_PORTC, 15, 0); /* LCDD11 */ 24320d98c2cSAsen Dimov at91_set_a_periph(AT91_PIO_PORTC, 16, 0); /* LCDD12 */ 24420d98c2cSAsen Dimov at91_set_b_periph(AT91_PIO_PORTC, 12, 0); /* LCDD13 */ 24520d98c2cSAsen Dimov at91_set_a_periph(AT91_PIO_PORTC, 18, 0); /* LCDD14 */ 24620d98c2cSAsen Dimov at91_set_a_periph(AT91_PIO_PORTC, 19, 0); /* LCDD15 */ 24720d98c2cSAsen Dimov at91_set_a_periph(AT91_PIO_PORTC, 22, 0); /* LCDD18 */ 24820d98c2cSAsen Dimov at91_set_a_periph(AT91_PIO_PORTC, 23, 0); /* LCDD19 */ 24920d98c2cSAsen Dimov at91_set_a_periph(AT91_PIO_PORTC, 24, 0); /* LCDD20 */ 25020d98c2cSAsen Dimov at91_set_b_periph(AT91_PIO_PORTC, 17, 0); /* LCDD21 */ 25120d98c2cSAsen Dimov at91_set_a_periph(AT91_PIO_PORTC, 26, 0); /* LCDD22 */ 25220d98c2cSAsen Dimov at91_set_a_periph(AT91_PIO_PORTC, 27, 0); /* LCDD23 */ 25320d98c2cSAsen Dimov 25470341e2eSWenyou Yang at91_periph_clk_enable(ATMEL_ID_LCDC); 255f0a2c7b4SIlko Iliev 256f0a2c7b4SIlko Iliev /* Power Control */ 25720d98c2cSAsen Dimov at91_set_pio_output(AT91_PIO_PORTA, 22, 1); 25820d98c2cSAsen Dimov at91_set_pio_value(AT91_PIO_PORTA, 22, 0); /* power down */ 259f0a2c7b4SIlko Iliev 260f0a2c7b4SIlko Iliev #ifdef CONFIG_LCD_IN_PSRAM 261f0a2c7b4SIlko Iliev /* initialize te PSRAM */ 262f0a2c7b4SIlko Iliev int stat = pm9263_lcd_hw_psram_init(); 263f0a2c7b4SIlko Iliev 264684a567aSAsen Dimov gd->fb_base = (stat == 0) ? PHYS_PSRAM : ATMEL_BASE_SRAM0; 265f0a2c7b4SIlko Iliev #else 266684a567aSAsen Dimov gd->fb_base = ATMEL_BASE_SRAM0; 267f0a2c7b4SIlko Iliev #endif 268f0a2c7b4SIlko Iliev 269f0a2c7b4SIlko Iliev } 270f0a2c7b4SIlko Iliev 271f0a2c7b4SIlko Iliev #ifdef CONFIG_LCD_INFO 272f0a2c7b4SIlko Iliev #include <nand.h> 273f0a2c7b4SIlko Iliev #include <version.h> 274f0a2c7b4SIlko Iliev 275f0a2c7b4SIlko Iliev extern flash_info_t flash_info[]; 276f0a2c7b4SIlko Iliev 277f0a2c7b4SIlko Iliev void lcd_show_board_info(void) 278f0a2c7b4SIlko Iliev { 279f0a2c7b4SIlko Iliev ulong dram_size, nand_size, flash_size, dataflash_size; 280f0a2c7b4SIlko Iliev int i; 281f0a2c7b4SIlko Iliev char temp[32]; 282f0a2c7b4SIlko Iliev 283f0a2c7b4SIlko Iliev lcd_printf ("%s\n", U_BOOT_VERSION); 284f0a2c7b4SIlko Iliev lcd_printf ("(C) 2009 Ronetix GmbH\n"); 285f0a2c7b4SIlko Iliev lcd_printf ("support@ronetix.at\n"); 286f0a2c7b4SIlko Iliev lcd_printf ("%s CPU at %s MHz", 2877c966a8bSAchim Ehrlich CONFIG_SYS_AT91_CPU_NAME, 288f0a2c7b4SIlko Iliev strmhz(temp, get_cpu_clk_rate())); 289f0a2c7b4SIlko Iliev 290f0a2c7b4SIlko Iliev dram_size = 0; 291f0a2c7b4SIlko Iliev for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) 292f0a2c7b4SIlko Iliev dram_size += gd->bd->bi_dram[i].size; 293f0a2c7b4SIlko Iliev 294f0a2c7b4SIlko Iliev nand_size = 0; 295f0a2c7b4SIlko Iliev for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++) 296b616d9b0SScott Wood nand_size += nand_info[i]->size; 297f0a2c7b4SIlko Iliev 298f0a2c7b4SIlko Iliev flash_size = 0; 299f0a2c7b4SIlko Iliev for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) 300f0a2c7b4SIlko Iliev flash_size += flash_info[i].size; 301f0a2c7b4SIlko Iliev 302f0a2c7b4SIlko Iliev dataflash_size = 0; 303f0a2c7b4SIlko Iliev for (i = 0; i < CONFIG_SYS_MAX_DATAFLASH_BANKS; i++) 304f0a2c7b4SIlko Iliev dataflash_size += (unsigned int) dataflash_info[i].Device.pages_number * 305f0a2c7b4SIlko Iliev dataflash_info[i].Device.pages_size; 306f0a2c7b4SIlko Iliev 307f0a2c7b4SIlko Iliev lcd_printf ("%ld MB SDRAM, %ld MB NAND\n%ld MB NOR Flash\n" 308f0a2c7b4SIlko Iliev "4 MB PSRAM, %ld MB DataFlash\n", 309f0a2c7b4SIlko Iliev dram_size >> 20, 310f0a2c7b4SIlko Iliev nand_size >> 20, 311f0a2c7b4SIlko Iliev flash_size >> 20, 312f0a2c7b4SIlko Iliev dataflash_size >> 20); 313f0a2c7b4SIlko Iliev } 314f0a2c7b4SIlko Iliev #endif /* CONFIG_LCD_INFO */ 315f0a2c7b4SIlko Iliev 316f0a2c7b4SIlko Iliev #endif /* CONFIG_LCD */ 317f0a2c7b4SIlko Iliev 31852b26016SAsen Dimov int board_early_init_f(void) 319f0a2c7b4SIlko Iliev { 32070341e2eSWenyou Yang at91_periph_clk_enable(ATMEL_ID_PIOA); 32170341e2eSWenyou Yang at91_periph_clk_enable(ATMEL_ID_PIOB); 32270341e2eSWenyou Yang at91_periph_clk_enable(ATMEL_ID_PIOCDE); 323f0a2c7b4SIlko Iliev 32452b26016SAsen Dimov at91_seriald_hw_init(); 32552b26016SAsen Dimov 32652b26016SAsen Dimov return 0; 32752b26016SAsen Dimov } 32852b26016SAsen Dimov 32952b26016SAsen Dimov int board_init(void) 33052b26016SAsen Dimov { 33152b26016SAsen Dimov /* arch number of AT91SAM9263EK-Board */ 33252b26016SAsen Dimov gd->bd->bi_arch_number = MACH_TYPE_PM9263; 33352b26016SAsen Dimov 334f0a2c7b4SIlko Iliev /* adress of boot parameters */ 335f0a2c7b4SIlko Iliev gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; 336f0a2c7b4SIlko Iliev 337f0a2c7b4SIlko Iliev #ifdef CONFIG_CMD_NAND 338f0a2c7b4SIlko Iliev pm9263_nand_hw_init(); 339f0a2c7b4SIlko Iliev #endif 340f0a2c7b4SIlko Iliev #ifdef CONFIG_HAS_DATAFLASH 341f0a2c7b4SIlko Iliev at91_spi0_hw_init(1 << 0); 342f0a2c7b4SIlko Iliev #endif 343f0a2c7b4SIlko Iliev #ifdef CONFIG_MACB 344f0a2c7b4SIlko Iliev pm9263_macb_hw_init(); 345f0a2c7b4SIlko Iliev #endif 346f0a2c7b4SIlko Iliev #ifdef CONFIG_USB_OHCI_NEW 347f0a2c7b4SIlko Iliev at91_uhp_hw_init(); 348f0a2c7b4SIlko Iliev #endif 349f0a2c7b4SIlko Iliev #ifdef CONFIG_LCD 350f0a2c7b4SIlko Iliev pm9263_lcd_hw_init(); 351f0a2c7b4SIlko Iliev #endif 352f0a2c7b4SIlko Iliev return 0; 353f0a2c7b4SIlko Iliev } 354f0a2c7b4SIlko Iliev 355f0a2c7b4SIlko Iliev int dram_init(void) 356f0a2c7b4SIlko Iliev { 3579a2a05a4SAsen Dimov /* dram_init must store complete ramsize in gd->ram_size */ 358a55d23ccSAlbert ARIBAUD gd->ram_size = get_ram_size((void *)PHYS_SDRAM, 3599a2a05a4SAsen Dimov PHYS_SDRAM_SIZE); 3609a2a05a4SAsen Dimov return 0; 3619a2a05a4SAsen Dimov } 3629a2a05a4SAsen Dimov 363*76b00acaSSimon Glass int dram_init_banksize(void) 3649a2a05a4SAsen Dimov { 365f0a2c7b4SIlko Iliev gd->bd->bi_dram[0].start = PHYS_SDRAM; 366f0a2c7b4SIlko Iliev gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE; 367*76b00acaSSimon Glass 368*76b00acaSSimon Glass return 0; 369f0a2c7b4SIlko Iliev } 370f0a2c7b4SIlko Iliev 371f0a2c7b4SIlko Iliev #ifdef CONFIG_RESET_PHY_R 372f0a2c7b4SIlko Iliev void reset_phy(void) 373f0a2c7b4SIlko Iliev { 374f0a2c7b4SIlko Iliev } 375f0a2c7b4SIlko Iliev #endif 376f0a2c7b4SIlko Iliev 377f0a2c7b4SIlko Iliev int board_eth_init(bd_t *bis) 378f0a2c7b4SIlko Iliev { 379f0a2c7b4SIlko Iliev int rc = 0; 380f0a2c7b4SIlko Iliev #ifdef CONFIG_MACB 381684a567aSAsen Dimov rc = macb_eth_initialize(0, (void *)ATMEL_BASE_EMAC, 0x01); 382f0a2c7b4SIlko Iliev #endif 383f0a2c7b4SIlko Iliev return rc; 384f0a2c7b4SIlko Iliev } 385f0a2c7b4SIlko Iliev 386f0a2c7b4SIlko Iliev #ifdef CONFIG_DISPLAY_BOARDINFO 387f0a2c7b4SIlko Iliev int checkboard (void) 388f0a2c7b4SIlko Iliev { 389f0a2c7b4SIlko Iliev char *ss; 390f0a2c7b4SIlko Iliev 391f0a2c7b4SIlko Iliev printf ("Board : Ronetix PM9263\n"); 392f0a2c7b4SIlko Iliev 393f0a2c7b4SIlko Iliev switch (gd->fb_base) { 394f0a2c7b4SIlko Iliev case PHYS_PSRAM: 395f0a2c7b4SIlko Iliev ss = "(PSRAM)"; 396f0a2c7b4SIlko Iliev break; 397f0a2c7b4SIlko Iliev 398684a567aSAsen Dimov case ATMEL_BASE_SRAM0: 399f0a2c7b4SIlko Iliev ss = "(Internal SRAM)"; 400f0a2c7b4SIlko Iliev break; 401f0a2c7b4SIlko Iliev 402f0a2c7b4SIlko Iliev default: 403f0a2c7b4SIlko Iliev ss = ""; 404f0a2c7b4SIlko Iliev break; 405f0a2c7b4SIlko Iliev } 406f0a2c7b4SIlko Iliev printf("Video memory : 0x%08lX %s\n", gd->fb_base, ss ); 407f0a2c7b4SIlko Iliev 408f0a2c7b4SIlko Iliev printf ("\n"); 409f0a2c7b4SIlko Iliev return 0; 410f0a2c7b4SIlko Iliev } 411f0a2c7b4SIlko Iliev #endif 412