1f0a2c7b4SIlko Iliev /* 2f0a2c7b4SIlko Iliev * (C) Copyright 2007-2008 3f0a2c7b4SIlko Iliev * Stelian Pop <stelian.pop@leadtechdesign.com> 4f0a2c7b4SIlko Iliev * Lead Tech Design <www.leadtechdesign.com> 5f0a2c7b4SIlko Iliev * Copyright (C) 2008 Ronetix Ilko Iliev (www.ronetix.at) 6f0a2c7b4SIlko Iliev * Copyright (C) 2009 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> 7f0a2c7b4SIlko Iliev * 8f0a2c7b4SIlko Iliev * See file CREDITS for list of people who contributed to this 9f0a2c7b4SIlko Iliev * project. 10f0a2c7b4SIlko Iliev * 11f0a2c7b4SIlko Iliev * This program is free software; you can redistribute it and/or 12f0a2c7b4SIlko Iliev * modify it under the terms of the GNU General Public License as 13f0a2c7b4SIlko Iliev * published by the Free Software Foundation; either version 2 of 14f0a2c7b4SIlko Iliev * the License, or (at your option) any later version. 15f0a2c7b4SIlko Iliev * 16f0a2c7b4SIlko Iliev * This program is distributed in the hope that it will be useful, 17f0a2c7b4SIlko Iliev * but WITHOUT ANY WARRANTY; without even the implied warranty of 18f0a2c7b4SIlko Iliev * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 19f0a2c7b4SIlko Iliev * GNU General Public License for more details. 20f0a2c7b4SIlko Iliev * 21f0a2c7b4SIlko Iliev * You should have received a copy of the GNU General Public License 22f0a2c7b4SIlko Iliev * along with this program; if not, write to the Free Software 23f0a2c7b4SIlko Iliev * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 24f0a2c7b4SIlko Iliev * MA 02111-1307 USA 25f0a2c7b4SIlko Iliev */ 26f0a2c7b4SIlko Iliev 27f0a2c7b4SIlko Iliev #include <common.h> 28f0a2c7b4SIlko Iliev #include <asm/sizes.h> 29f0a2c7b4SIlko Iliev #include <asm/arch/at91sam9263.h> 30f0a2c7b4SIlko Iliev #include <asm/arch/at91sam9_smc.h> 31f0a2c7b4SIlko Iliev #include <asm/arch/at91_common.h> 32f0a2c7b4SIlko Iliev #include <asm/arch/at91_pmc.h> 33f0a2c7b4SIlko Iliev #include <asm/arch/at91_rstc.h> 34*20d98c2cSAsen Dimov #include <asm/arch/at91_matrix.h> 35*20d98c2cSAsen Dimov #include <asm/arch/at91_pio.h> 36f0a2c7b4SIlko Iliev #include <asm/arch/clk.h> 37f0a2c7b4SIlko Iliev #include <asm/arch/io.h> 38f0a2c7b4SIlko Iliev #include <asm/arch/hardware.h> 39f0a2c7b4SIlko Iliev #include <lcd.h> 40f0a2c7b4SIlko Iliev #include <atmel_lcdc.h> 41f0a2c7b4SIlko Iliev #include <dataflash.h> 42f0a2c7b4SIlko Iliev #if defined(CONFIG_RESET_PHY_R) && defined(CONFIG_MACB) 43f0a2c7b4SIlko Iliev #include <net.h> 44f0a2c7b4SIlko Iliev #endif 45f0a2c7b4SIlko Iliev #include <netdev.h> 46f0a2c7b4SIlko Iliev 47f0a2c7b4SIlko Iliev DECLARE_GLOBAL_DATA_PTR; 48f0a2c7b4SIlko Iliev 49f0a2c7b4SIlko Iliev /* ------------------------------------------------------------------------- */ 50f0a2c7b4SIlko Iliev /* 51f0a2c7b4SIlko Iliev * Miscelaneous platform dependent initialisations 52f0a2c7b4SIlko Iliev */ 53f0a2c7b4SIlko Iliev 54f0a2c7b4SIlko Iliev #ifdef CONFIG_CMD_NAND 55f0a2c7b4SIlko Iliev static void pm9263_nand_hw_init(void) 56f0a2c7b4SIlko Iliev { 57f0a2c7b4SIlko Iliev unsigned long csa; 58*20d98c2cSAsen Dimov at91_smc_t *smc = (at91_smc_t *) AT91_SMC0_BASE; 59*20d98c2cSAsen Dimov at91_matrix_t *matrix = (at91_matrix_t *) AT91_MATRIX_BASE; 60f0a2c7b4SIlko Iliev 61f0a2c7b4SIlko Iliev /* Enable CS3 */ 62*20d98c2cSAsen Dimov csa = readl(&matrix->csa[0]) | AT91_MATRIX_CSA_EBI_CS3A; 63*20d98c2cSAsen Dimov writel(csa, &matrix->csa[0]); 64f0a2c7b4SIlko Iliev 65f0a2c7b4SIlko Iliev /* Configure SMC CS3 for NAND/SmartMedia */ 66*20d98c2cSAsen Dimov writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(1) | 67*20d98c2cSAsen Dimov AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(1), 68*20d98c2cSAsen Dimov &smc->cs[3].setup); 69*20d98c2cSAsen Dimov 70*20d98c2cSAsen Dimov writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(3) | 71*20d98c2cSAsen Dimov AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(3), 72*20d98c2cSAsen Dimov &smc->cs[3].pulse); 73*20d98c2cSAsen Dimov 74*20d98c2cSAsen Dimov writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(5), 75*20d98c2cSAsen Dimov &smc->cs[3].cycle); 76*20d98c2cSAsen Dimov 77*20d98c2cSAsen Dimov writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE | 78*20d98c2cSAsen Dimov AT91_SMC_MODE_EXNW_DISABLE | 79f0a2c7b4SIlko Iliev #ifdef CONFIG_SYS_NAND_DBW_16 80*20d98c2cSAsen Dimov AT91_SMC_MODE_DBW_16 | 81f0a2c7b4SIlko Iliev #else /* CONFIG_SYS_NAND_DBW_8 */ 82*20d98c2cSAsen Dimov AT91_SMC_MODE_DBW_8 | 83f0a2c7b4SIlko Iliev #endif 84*20d98c2cSAsen Dimov AT91_SMC_MODE_TDF_CYCLE(2), 85*20d98c2cSAsen Dimov &smc->cs[3].mode); 86f0a2c7b4SIlko Iliev 87f0a2c7b4SIlko Iliev /* Configure RDY/BSY */ 88*20d98c2cSAsen Dimov at91_set_pio_input(CONFIG_SYS_NAND_READY_PIN, 1); 89f0a2c7b4SIlko Iliev 90f0a2c7b4SIlko Iliev /* Enable NandFlash */ 91*20d98c2cSAsen Dimov at91_set_pio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1); 92f0a2c7b4SIlko Iliev } 93f0a2c7b4SIlko Iliev #endif 94f0a2c7b4SIlko Iliev 95f0a2c7b4SIlko Iliev #ifdef CONFIG_MACB 96f0a2c7b4SIlko Iliev static void pm9263_macb_hw_init(void) 97f0a2c7b4SIlko Iliev { 98*20d98c2cSAsen Dimov at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE; 99*20d98c2cSAsen Dimov at91_pio_t *pio = (at91_pio_t *) AT91_PIO_BASE; 100*20d98c2cSAsen Dimov 101f0a2c7b4SIlko Iliev /* 102f0a2c7b4SIlko Iliev * PB27 enables the 50MHz oscillator for Ethernet PHY 103f0a2c7b4SIlko Iliev * 1 - enable 104f0a2c7b4SIlko Iliev * 0 - disable 105f0a2c7b4SIlko Iliev */ 106*20d98c2cSAsen Dimov at91_set_pio_output(AT91_PIO_PORTB, 27, 1); 107*20d98c2cSAsen Dimov at91_set_pio_value(AT91_PIO_PORTB, 27, 1); /* 1- enable, 0 - disable */ 108f0a2c7b4SIlko Iliev 109f0a2c7b4SIlko Iliev /* Enable clock */ 110*20d98c2cSAsen Dimov writel(1 << AT91SAM9263_ID_EMAC, &pmc->pcer); 111f0a2c7b4SIlko Iliev 112f0a2c7b4SIlko Iliev /* 113f0a2c7b4SIlko Iliev * Disable pull-up on: 114f0a2c7b4SIlko Iliev * RXDV (PC25) => PHY normal mode (not Test mode) 115f0a2c7b4SIlko Iliev * ERX0 (PE25) => PHY ADDR0 116f0a2c7b4SIlko Iliev * ERX1 (PE26) => PHY ADDR1 => PHYADDR = 0x0 117f0a2c7b4SIlko Iliev * 118f0a2c7b4SIlko Iliev * PHY has internal pull-down 119f0a2c7b4SIlko Iliev */ 120f0a2c7b4SIlko Iliev 121*20d98c2cSAsen Dimov at91_set_pio_pullup(AT91_PIO_PORTC, 25, 0); 122*20d98c2cSAsen Dimov at91_set_pio_pullup(AT91_PIO_PORTE, 25, 0); 123*20d98c2cSAsen Dimov at91_set_pio_pullup(AT91_PIO_PORTE, 26, 0); 124f0a2c7b4SIlko Iliev 125f0a2c7b4SIlko Iliev /* Re-enable pull-up */ 126*20d98c2cSAsen Dimov at91_set_pio_pullup(AT91_PIO_PORTC, 25, 1); 127*20d98c2cSAsen Dimov at91_set_pio_pullup(AT91_PIO_PORTE, 25, 1); 128*20d98c2cSAsen Dimov at91_set_pio_pullup(AT91_PIO_PORTE, 26, 1); 129f0a2c7b4SIlko Iliev 130f0a2c7b4SIlko Iliev at91_macb_hw_init(); 131f0a2c7b4SIlko Iliev } 132f0a2c7b4SIlko Iliev #endif 133f0a2c7b4SIlko Iliev 134f0a2c7b4SIlko Iliev #ifdef CONFIG_LCD 135f0a2c7b4SIlko Iliev vidinfo_t panel_info = { 136f0a2c7b4SIlko Iliev vl_col: 240, 137f0a2c7b4SIlko Iliev vl_row: 320, 138f0a2c7b4SIlko Iliev vl_clk: 4965000, 139f0a2c7b4SIlko Iliev vl_sync: ATMEL_LCDC_INVLINE_INVERTED | 140f0a2c7b4SIlko Iliev ATMEL_LCDC_INVFRAME_INVERTED, 141f0a2c7b4SIlko Iliev vl_bpix: 3, 142f0a2c7b4SIlko Iliev vl_tft: 1, 143f0a2c7b4SIlko Iliev vl_hsync_len: 5, 144f0a2c7b4SIlko Iliev vl_left_margin: 1, 145f0a2c7b4SIlko Iliev vl_right_margin:33, 146f0a2c7b4SIlko Iliev vl_vsync_len: 1, 147f0a2c7b4SIlko Iliev vl_upper_margin:1, 148f0a2c7b4SIlko Iliev vl_lower_margin:0, 149f0a2c7b4SIlko Iliev mmio: AT91SAM9263_LCDC_BASE, 150f0a2c7b4SIlko Iliev }; 151f0a2c7b4SIlko Iliev 152f0a2c7b4SIlko Iliev void lcd_enable(void) 153f0a2c7b4SIlko Iliev { 154*20d98c2cSAsen Dimov at91_set_pio_value(AT91_PIO_PORTA, 22, 1); /* power up */ 155f0a2c7b4SIlko Iliev } 156f0a2c7b4SIlko Iliev 157f0a2c7b4SIlko Iliev void lcd_disable(void) 158f0a2c7b4SIlko Iliev { 159*20d98c2cSAsen Dimov at91_set_pio_value(AT91_PIO_PORTA, 22, 0); /* power down */ 160f0a2c7b4SIlko Iliev } 161f0a2c7b4SIlko Iliev 162f0a2c7b4SIlko Iliev #ifdef CONFIG_LCD_IN_PSRAM 163f0a2c7b4SIlko Iliev 164*20d98c2cSAsen Dimov #define PSRAM_CRE_PIN AT91_PIO_PORTB, 29 165f0a2c7b4SIlko Iliev #define PSRAM_CTRL_REG (PHYS_PSRAM + PHYS_PSRAM_SIZE - 2) 166f0a2c7b4SIlko Iliev 167f0a2c7b4SIlko Iliev /* Initialize the PSRAM memory */ 168f0a2c7b4SIlko Iliev static int pm9263_lcd_hw_psram_init(void) 169f0a2c7b4SIlko Iliev { 170f0a2c7b4SIlko Iliev volatile uint16_t x; 1717a11c7f9SJean-Christophe PLAGNIOL-VILLARD unsigned long csa; 172*20d98c2cSAsen Dimov at91_smc_t *smc = (at91_smc_t *) AT91_SMC1_BASE; 173*20d98c2cSAsen Dimov at91_matrix_t *matrix = (at91_matrix_t *) AT91_MATRIX_BASE; 1747a11c7f9SJean-Christophe PLAGNIOL-VILLARD 1757a11c7f9SJean-Christophe PLAGNIOL-VILLARD /* Enable CS3 3.3v, no pull-ups */ 176*20d98c2cSAsen Dimov csa = readl(&matrix->csa[1]) | AT91_MATRIX_CSA_DBPUC | 177*20d98c2cSAsen Dimov AT91_MATRIX_CSA_VDDIOMSEL_3_3V; 178*20d98c2cSAsen Dimov 179*20d98c2cSAsen Dimov writel(csa, &matrix->csa[1]); 1807a11c7f9SJean-Christophe PLAGNIOL-VILLARD 1817a11c7f9SJean-Christophe PLAGNIOL-VILLARD /* Configure SMC1 CS0 for PSRAM - 16-bit */ 182*20d98c2cSAsen Dimov writel(AT91_SMC_SETUP_NWE(0) | AT91_SMC_SETUP_NCS_WR(0) | 183*20d98c2cSAsen Dimov AT91_SMC_SETUP_NRD(0) | AT91_SMC_SETUP_NCS_RD(0), 184*20d98c2cSAsen Dimov &smc->cs[0].setup); 185*20d98c2cSAsen Dimov 186*20d98c2cSAsen Dimov writel(AT91_SMC_PULSE_NWE(7) | AT91_SMC_PULSE_NCS_WR(7) | 187*20d98c2cSAsen Dimov AT91_SMC_PULSE_NRD(2) | AT91_SMC_PULSE_NCS_RD(7), 188*20d98c2cSAsen Dimov &smc->cs[0].pulse); 189*20d98c2cSAsen Dimov 190*20d98c2cSAsen Dimov writel(AT91_SMC_CYCLE_NWE(8) | AT91_SMC_CYCLE_NRD(8), 191*20d98c2cSAsen Dimov &smc->cs[0].cycle); 192*20d98c2cSAsen Dimov 193*20d98c2cSAsen Dimov writel(AT91_SMC_MODE_DBW_16 | AT91_SMC_MODE_PMEN | AT91_SMC_MODE_PS_32, 194*20d98c2cSAsen Dimov &smc->cs[0].mode); 195f0a2c7b4SIlko Iliev 196f0a2c7b4SIlko Iliev /* setup PB29 as output */ 197*20d98c2cSAsen Dimov at91_set_pio_output(PSRAM_CRE_PIN, 1); 198f0a2c7b4SIlko Iliev 199*20d98c2cSAsen Dimov at91_set_pio_value(PSRAM_CRE_PIN, 0); /* set PSRAM_CRE_PIN to '0' */ 200f0a2c7b4SIlko Iliev 201f0a2c7b4SIlko Iliev /* PSRAM: write BCR */ 202f0a2c7b4SIlko Iliev x = readw(PSRAM_CTRL_REG); 203f0a2c7b4SIlko Iliev x = readw(PSRAM_CTRL_REG); 204f0a2c7b4SIlko Iliev writew(1, PSRAM_CTRL_REG); /* 0 - RCR,1 - BCR */ 205f0a2c7b4SIlko Iliev writew(0x9d4f, PSRAM_CTRL_REG); /* write the BCR */ 206f0a2c7b4SIlko Iliev 207f0a2c7b4SIlko Iliev /* write RCR of the PSRAM */ 208f0a2c7b4SIlko Iliev x = readw(PSRAM_CTRL_REG); 209f0a2c7b4SIlko Iliev x = readw(PSRAM_CTRL_REG); 210f0a2c7b4SIlko Iliev writew(0, PSRAM_CTRL_REG); /* 0 - RCR,1 - BCR */ 211f0a2c7b4SIlko Iliev /* set RCR; 0x10-async mode,0x90-page mode */ 212f0a2c7b4SIlko Iliev writew(0x90, PSRAM_CTRL_REG); 213f0a2c7b4SIlko Iliev 214f0a2c7b4SIlko Iliev /* 215f0a2c7b4SIlko Iliev * test to see if the PSRAM is MT45W2M16A or MT45W2M16B 216f0a2c7b4SIlko Iliev * MT45W2M16B - CRE must be 0 217f0a2c7b4SIlko Iliev * MT45W2M16A - CRE must be 1 218f0a2c7b4SIlko Iliev */ 219f0a2c7b4SIlko Iliev writew(0x1234, PHYS_PSRAM); 220f0a2c7b4SIlko Iliev writew(0x5678, PHYS_PSRAM + 2); 221f0a2c7b4SIlko Iliev 222f0a2c7b4SIlko Iliev /* test if the chip is MT45W2M16B */ 223f0a2c7b4SIlko Iliev if ((readw(PHYS_PSRAM) != 0x1234) || (readw(PHYS_PSRAM+2) != 0x5678)) { 224f0a2c7b4SIlko Iliev /* try with CRE=1 (MT45W2M16A) */ 225*20d98c2cSAsen Dimov at91_set_pio_value(PSRAM_CRE_PIN, 1); /* set PSRAM_CRE_PIN to '1' */ 226f0a2c7b4SIlko Iliev 227f0a2c7b4SIlko Iliev /* write RCR of the PSRAM */ 228f0a2c7b4SIlko Iliev x = readw(PSRAM_CTRL_REG); 229f0a2c7b4SIlko Iliev x = readw(PSRAM_CTRL_REG); 230f0a2c7b4SIlko Iliev writew(0, PSRAM_CTRL_REG); /* 0 - RCR,1 - BCR */ 231f0a2c7b4SIlko Iliev /* set RCR;0x10-async mode,0x90-page mode */ 232f0a2c7b4SIlko Iliev writew(0x90, PSRAM_CTRL_REG); 233f0a2c7b4SIlko Iliev 234f0a2c7b4SIlko Iliev 235f0a2c7b4SIlko Iliev writew(0x1234, PHYS_PSRAM); 236f0a2c7b4SIlko Iliev writew(0x5678, PHYS_PSRAM+2); 237f0a2c7b4SIlko Iliev if ((readw(PHYS_PSRAM) != 0x1234) 238f0a2c7b4SIlko Iliev || (readw(PHYS_PSRAM + 2) != 0x5678)) 239f0a2c7b4SIlko Iliev return 1; 240f0a2c7b4SIlko Iliev 241f0a2c7b4SIlko Iliev } 242f0a2c7b4SIlko Iliev 243f0a2c7b4SIlko Iliev /* Bus matrix */ 244*20d98c2cSAsen Dimov writel(AT91_MATRIX_PRA_M5(3), &matrix->pr[5].a); 245*20d98c2cSAsen Dimov writel(CONFIG_PSRAM_SCFG, &matrix->scfg[5]); 246f0a2c7b4SIlko Iliev 247f0a2c7b4SIlko Iliev return 0; 248f0a2c7b4SIlko Iliev } 249f0a2c7b4SIlko Iliev #endif 250f0a2c7b4SIlko Iliev 251f0a2c7b4SIlko Iliev static void pm9263_lcd_hw_init(void) 252f0a2c7b4SIlko Iliev { 253*20d98c2cSAsen Dimov at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE; 254f0a2c7b4SIlko Iliev 255*20d98c2cSAsen Dimov at91_set_a_periph(AT91_PIO_PORTC, 0, 0); /* LCDVSYNC */ 256*20d98c2cSAsen Dimov at91_set_a_periph(AT91_PIO_PORTC, 1, 0); /* LCDHSYNC */ 257*20d98c2cSAsen Dimov at91_set_a_periph(AT91_PIO_PORTC, 2, 0); /* LCDDOTCK */ 258*20d98c2cSAsen Dimov at91_set_a_periph(AT91_PIO_PORTC, 3, 0); /* LCDDEN */ 259*20d98c2cSAsen Dimov at91_set_b_periph(AT91_PIO_PORTB, 9, 0); /* LCDCC */ 260*20d98c2cSAsen Dimov at91_set_a_periph(AT91_PIO_PORTC, 6, 0); /* LCDD2 */ 261*20d98c2cSAsen Dimov at91_set_a_periph(AT91_PIO_PORTC, 7, 0); /* LCDD3 */ 262*20d98c2cSAsen Dimov at91_set_a_periph(AT91_PIO_PORTC, 8, 0); /* LCDD4 */ 263*20d98c2cSAsen Dimov at91_set_a_periph(AT91_PIO_PORTC, 9, 0); /* LCDD5 */ 264*20d98c2cSAsen Dimov at91_set_a_periph(AT91_PIO_PORTC, 10, 0); /* LCDD6 */ 265*20d98c2cSAsen Dimov at91_set_a_periph(AT91_PIO_PORTC, 11, 0); /* LCDD7 */ 266*20d98c2cSAsen Dimov at91_set_a_periph(AT91_PIO_PORTC, 14, 0); /* LCDD10 */ 267*20d98c2cSAsen Dimov at91_set_a_periph(AT91_PIO_PORTC, 15, 0); /* LCDD11 */ 268*20d98c2cSAsen Dimov at91_set_a_periph(AT91_PIO_PORTC, 16, 0); /* LCDD12 */ 269*20d98c2cSAsen Dimov at91_set_b_periph(AT91_PIO_PORTC, 12, 0); /* LCDD13 */ 270*20d98c2cSAsen Dimov at91_set_a_periph(AT91_PIO_PORTC, 18, 0); /* LCDD14 */ 271*20d98c2cSAsen Dimov at91_set_a_periph(AT91_PIO_PORTC, 19, 0); /* LCDD15 */ 272*20d98c2cSAsen Dimov at91_set_a_periph(AT91_PIO_PORTC, 22, 0); /* LCDD18 */ 273*20d98c2cSAsen Dimov at91_set_a_periph(AT91_PIO_PORTC, 23, 0); /* LCDD19 */ 274*20d98c2cSAsen Dimov at91_set_a_periph(AT91_PIO_PORTC, 24, 0); /* LCDD20 */ 275*20d98c2cSAsen Dimov at91_set_b_periph(AT91_PIO_PORTC, 17, 0); /* LCDD21 */ 276*20d98c2cSAsen Dimov at91_set_a_periph(AT91_PIO_PORTC, 26, 0); /* LCDD22 */ 277*20d98c2cSAsen Dimov at91_set_a_periph(AT91_PIO_PORTC, 27, 0); /* LCDD23 */ 278*20d98c2cSAsen Dimov 279*20d98c2cSAsen Dimov writel(1 << AT91SAM9263_ID_LCDC, &pmc->pcer); 280f0a2c7b4SIlko Iliev 281f0a2c7b4SIlko Iliev /* Power Control */ 282*20d98c2cSAsen Dimov at91_set_pio_output(AT91_PIO_PORTA, 22, 1); 283*20d98c2cSAsen Dimov at91_set_pio_value(AT91_PIO_PORTA, 22, 0); /* power down */ 284f0a2c7b4SIlko Iliev 285f0a2c7b4SIlko Iliev #ifdef CONFIG_LCD_IN_PSRAM 286f0a2c7b4SIlko Iliev /* initialize te PSRAM */ 287f0a2c7b4SIlko Iliev int stat = pm9263_lcd_hw_psram_init(); 288f0a2c7b4SIlko Iliev 289f0a2c7b4SIlko Iliev gd->fb_base = (stat == 0) ? PHYS_PSRAM : AT91SAM9263_SRAM0_BASE; 290f0a2c7b4SIlko Iliev #else 291f0a2c7b4SIlko Iliev gd->fb_base = AT91SAM9263_SRAM0_BASE; 292f0a2c7b4SIlko Iliev #endif 293f0a2c7b4SIlko Iliev 294f0a2c7b4SIlko Iliev } 295f0a2c7b4SIlko Iliev 296f0a2c7b4SIlko Iliev #ifdef CONFIG_LCD_INFO 297f0a2c7b4SIlko Iliev #include <nand.h> 298f0a2c7b4SIlko Iliev #include <version.h> 299f0a2c7b4SIlko Iliev 300f0a2c7b4SIlko Iliev extern flash_info_t flash_info[]; 301f0a2c7b4SIlko Iliev 302f0a2c7b4SIlko Iliev void lcd_show_board_info(void) 303f0a2c7b4SIlko Iliev { 304f0a2c7b4SIlko Iliev ulong dram_size, nand_size, flash_size, dataflash_size; 305f0a2c7b4SIlko Iliev int i; 306f0a2c7b4SIlko Iliev char temp[32]; 307f0a2c7b4SIlko Iliev 308f0a2c7b4SIlko Iliev lcd_printf ("%s\n", U_BOOT_VERSION); 309f0a2c7b4SIlko Iliev lcd_printf ("(C) 2009 Ronetix GmbH\n"); 310f0a2c7b4SIlko Iliev lcd_printf ("support@ronetix.at\n"); 311f0a2c7b4SIlko Iliev lcd_printf ("%s CPU at %s MHz", 3127c966a8bSAchim Ehrlich CONFIG_SYS_AT91_CPU_NAME, 313f0a2c7b4SIlko Iliev strmhz(temp, get_cpu_clk_rate())); 314f0a2c7b4SIlko Iliev 315f0a2c7b4SIlko Iliev dram_size = 0; 316f0a2c7b4SIlko Iliev for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) 317f0a2c7b4SIlko Iliev dram_size += gd->bd->bi_dram[i].size; 318f0a2c7b4SIlko Iliev 319f0a2c7b4SIlko Iliev nand_size = 0; 320f0a2c7b4SIlko Iliev for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++) 321f0a2c7b4SIlko Iliev nand_size += nand_info[i].size; 322f0a2c7b4SIlko Iliev 323f0a2c7b4SIlko Iliev flash_size = 0; 324f0a2c7b4SIlko Iliev for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) 325f0a2c7b4SIlko Iliev flash_size += flash_info[i].size; 326f0a2c7b4SIlko Iliev 327f0a2c7b4SIlko Iliev dataflash_size = 0; 328f0a2c7b4SIlko Iliev for (i = 0; i < CONFIG_SYS_MAX_DATAFLASH_BANKS; i++) 329f0a2c7b4SIlko Iliev dataflash_size += (unsigned int) dataflash_info[i].Device.pages_number * 330f0a2c7b4SIlko Iliev dataflash_info[i].Device.pages_size; 331f0a2c7b4SIlko Iliev 332f0a2c7b4SIlko Iliev lcd_printf ("%ld MB SDRAM, %ld MB NAND\n%ld MB NOR Flash\n" 333f0a2c7b4SIlko Iliev "4 MB PSRAM, %ld MB DataFlash\n", 334f0a2c7b4SIlko Iliev dram_size >> 20, 335f0a2c7b4SIlko Iliev nand_size >> 20, 336f0a2c7b4SIlko Iliev flash_size >> 20, 337f0a2c7b4SIlko Iliev dataflash_size >> 20); 338f0a2c7b4SIlko Iliev } 339f0a2c7b4SIlko Iliev #endif /* CONFIG_LCD_INFO */ 340f0a2c7b4SIlko Iliev 341f0a2c7b4SIlko Iliev #endif /* CONFIG_LCD */ 342f0a2c7b4SIlko Iliev 343f0a2c7b4SIlko Iliev int board_init(void) 344f0a2c7b4SIlko Iliev { 345*20d98c2cSAsen Dimov at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE; 346*20d98c2cSAsen Dimov 347f0a2c7b4SIlko Iliev /* Enable Ctrlc */ 348f0a2c7b4SIlko Iliev console_init_f(); 349f0a2c7b4SIlko Iliev 350*20d98c2cSAsen Dimov writel((1 << AT91SAM9263_ID_PIOA) | 351f0a2c7b4SIlko Iliev (1 << AT91SAM9263_ID_PIOCDE) | 352*20d98c2cSAsen Dimov (1 << AT91SAM9263_ID_PIOB), 353*20d98c2cSAsen Dimov &pmc->pcer); 354f0a2c7b4SIlko Iliev 355f0a2c7b4SIlko Iliev /* arch number of AT91SAM9263EK-Board */ 356f0a2c7b4SIlko Iliev gd->bd->bi_arch_number = MACH_TYPE_PM9263; 357f0a2c7b4SIlko Iliev 358f0a2c7b4SIlko Iliev /* adress of boot parameters */ 359f0a2c7b4SIlko Iliev gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; 360f0a2c7b4SIlko Iliev 361f0a2c7b4SIlko Iliev at91_serial_hw_init(); 362f0a2c7b4SIlko Iliev #ifdef CONFIG_CMD_NAND 363f0a2c7b4SIlko Iliev pm9263_nand_hw_init(); 364f0a2c7b4SIlko Iliev #endif 365f0a2c7b4SIlko Iliev #ifdef CONFIG_HAS_DATAFLASH 366f0a2c7b4SIlko Iliev at91_spi0_hw_init(1 << 0); 367f0a2c7b4SIlko Iliev #endif 368f0a2c7b4SIlko Iliev #ifdef CONFIG_MACB 369f0a2c7b4SIlko Iliev pm9263_macb_hw_init(); 370f0a2c7b4SIlko Iliev #endif 371f0a2c7b4SIlko Iliev #ifdef CONFIG_USB_OHCI_NEW 372f0a2c7b4SIlko Iliev at91_uhp_hw_init(); 373f0a2c7b4SIlko Iliev #endif 374f0a2c7b4SIlko Iliev #ifdef CONFIG_LCD 375f0a2c7b4SIlko Iliev pm9263_lcd_hw_init(); 376f0a2c7b4SIlko Iliev #endif 377f0a2c7b4SIlko Iliev return 0; 378f0a2c7b4SIlko Iliev } 379f0a2c7b4SIlko Iliev 380f0a2c7b4SIlko Iliev int dram_init(void) 381f0a2c7b4SIlko Iliev { 382f0a2c7b4SIlko Iliev gd->bd->bi_dram[0].start = PHYS_SDRAM; 383f0a2c7b4SIlko Iliev gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE; 384f0a2c7b4SIlko Iliev return 0; 385f0a2c7b4SIlko Iliev } 386f0a2c7b4SIlko Iliev 387f0a2c7b4SIlko Iliev #ifdef CONFIG_RESET_PHY_R 388f0a2c7b4SIlko Iliev void reset_phy(void) 389f0a2c7b4SIlko Iliev { 390f0a2c7b4SIlko Iliev #ifdef CONFIG_MACB 391f0a2c7b4SIlko Iliev /* 392f0a2c7b4SIlko Iliev * Initialize ethernet HW addr prior to starting Linux, 393f0a2c7b4SIlko Iliev * needed for nfsroot 394f0a2c7b4SIlko Iliev */ 395f0a2c7b4SIlko Iliev eth_init(gd->bd); 396f0a2c7b4SIlko Iliev #endif 397f0a2c7b4SIlko Iliev } 398f0a2c7b4SIlko Iliev #endif 399f0a2c7b4SIlko Iliev 400f0a2c7b4SIlko Iliev int board_eth_init(bd_t *bis) 401f0a2c7b4SIlko Iliev { 402f0a2c7b4SIlko Iliev int rc = 0; 403f0a2c7b4SIlko Iliev #ifdef CONFIG_MACB 404*20d98c2cSAsen Dimov rc = macb_eth_initialize(0, (void *)AT91_EMAC_BASE, 0x01); 405f0a2c7b4SIlko Iliev #endif 406f0a2c7b4SIlko Iliev return rc; 407f0a2c7b4SIlko Iliev } 408f0a2c7b4SIlko Iliev 409f0a2c7b4SIlko Iliev #ifdef CONFIG_DISPLAY_BOARDINFO 410f0a2c7b4SIlko Iliev int checkboard (void) 411f0a2c7b4SIlko Iliev { 412f0a2c7b4SIlko Iliev char *ss; 413f0a2c7b4SIlko Iliev 414f0a2c7b4SIlko Iliev printf ("Board : Ronetix PM9263\n"); 415f0a2c7b4SIlko Iliev 416f0a2c7b4SIlko Iliev switch (gd->fb_base) { 417f0a2c7b4SIlko Iliev case PHYS_PSRAM: 418f0a2c7b4SIlko Iliev ss = "(PSRAM)"; 419f0a2c7b4SIlko Iliev break; 420f0a2c7b4SIlko Iliev 421f0a2c7b4SIlko Iliev case AT91SAM9263_SRAM0_BASE: 422f0a2c7b4SIlko Iliev ss = "(Internal SRAM)"; 423f0a2c7b4SIlko Iliev break; 424f0a2c7b4SIlko Iliev 425f0a2c7b4SIlko Iliev default: 426f0a2c7b4SIlko Iliev ss = ""; 427f0a2c7b4SIlko Iliev break; 428f0a2c7b4SIlko Iliev } 429f0a2c7b4SIlko Iliev printf("Video memory : 0x%08lX %s\n", gd->fb_base, ss ); 430f0a2c7b4SIlko Iliev 431f0a2c7b4SIlko Iliev printf ("\n"); 432f0a2c7b4SIlko Iliev return 0; 433f0a2c7b4SIlko Iliev } 434f0a2c7b4SIlko Iliev #endif 435