1f0a2c7b4SIlko Iliev /* 2f0a2c7b4SIlko Iliev * (C) Copyright 2007-2008 3f0a2c7b4SIlko Iliev * Stelian Pop <stelian.pop@leadtechdesign.com> 4f0a2c7b4SIlko Iliev * Lead Tech Design <www.leadtechdesign.com> 5f0a2c7b4SIlko Iliev * Copyright (C) 2008 Ronetix Ilko Iliev (www.ronetix.at) 6f0a2c7b4SIlko Iliev * Copyright (C) 2009 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> 7f0a2c7b4SIlko Iliev * 8f0a2c7b4SIlko Iliev * See file CREDITS for list of people who contributed to this 9f0a2c7b4SIlko Iliev * project. 10f0a2c7b4SIlko Iliev * 11f0a2c7b4SIlko Iliev * This program is free software; you can redistribute it and/or 12f0a2c7b4SIlko Iliev * modify it under the terms of the GNU General Public License as 13f0a2c7b4SIlko Iliev * published by the Free Software Foundation; either version 2 of 14f0a2c7b4SIlko Iliev * the License, or (at your option) any later version. 15f0a2c7b4SIlko Iliev * 16f0a2c7b4SIlko Iliev * This program is distributed in the hope that it will be useful, 17f0a2c7b4SIlko Iliev * but WITHOUT ANY WARRANTY; without even the implied warranty of 18f0a2c7b4SIlko Iliev * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 19f0a2c7b4SIlko Iliev * GNU General Public License for more details. 20f0a2c7b4SIlko Iliev * 21f0a2c7b4SIlko Iliev * You should have received a copy of the GNU General Public License 22f0a2c7b4SIlko Iliev * along with this program; if not, write to the Free Software 23f0a2c7b4SIlko Iliev * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 24f0a2c7b4SIlko Iliev * MA 02111-1307 USA 25f0a2c7b4SIlko Iliev */ 26f0a2c7b4SIlko Iliev 27f0a2c7b4SIlko Iliev #include <common.h> 28f0a2c7b4SIlko Iliev #include <asm/sizes.h> 29684a567aSAsen Dimov #include <asm/io.h> 30f0a2c7b4SIlko Iliev #include <asm/arch/at91sam9_smc.h> 31f0a2c7b4SIlko Iliev #include <asm/arch/at91_common.h> 32f0a2c7b4SIlko Iliev #include <asm/arch/at91_pmc.h> 33f0a2c7b4SIlko Iliev #include <asm/arch/at91_rstc.h> 3420d98c2cSAsen Dimov #include <asm/arch/at91_matrix.h> 35f0a2c7b4SIlko Iliev #include <asm/arch/clk.h> 36684a567aSAsen Dimov #include <asm/arch/gpio.h> 37f0a2c7b4SIlko Iliev #include <lcd.h> 38f0a2c7b4SIlko Iliev #include <atmel_lcdc.h> 39f0a2c7b4SIlko Iliev #include <dataflash.h> 40f0a2c7b4SIlko Iliev #if defined(CONFIG_RESET_PHY_R) && defined(CONFIG_MACB) 41f0a2c7b4SIlko Iliev #include <net.h> 42f0a2c7b4SIlko Iliev #endif 43f0a2c7b4SIlko Iliev #include <netdev.h> 44f0a2c7b4SIlko Iliev 45f0a2c7b4SIlko Iliev DECLARE_GLOBAL_DATA_PTR; 46f0a2c7b4SIlko Iliev 47f0a2c7b4SIlko Iliev /* ------------------------------------------------------------------------- */ 48f0a2c7b4SIlko Iliev /* 49f0a2c7b4SIlko Iliev * Miscelaneous platform dependent initialisations 50f0a2c7b4SIlko Iliev */ 51f0a2c7b4SIlko Iliev 52f0a2c7b4SIlko Iliev #ifdef CONFIG_CMD_NAND 53f0a2c7b4SIlko Iliev static void pm9263_nand_hw_init(void) 54f0a2c7b4SIlko Iliev { 55f0a2c7b4SIlko Iliev unsigned long csa; 56684a567aSAsen Dimov struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC0; 57684a567aSAsen Dimov struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX; 58f0a2c7b4SIlko Iliev 59f0a2c7b4SIlko Iliev /* Enable CS3 */ 6020d98c2cSAsen Dimov csa = readl(&matrix->csa[0]) | AT91_MATRIX_CSA_EBI_CS3A; 6120d98c2cSAsen Dimov writel(csa, &matrix->csa[0]); 62f0a2c7b4SIlko Iliev 63f0a2c7b4SIlko Iliev /* Configure SMC CS3 for NAND/SmartMedia */ 6420d98c2cSAsen Dimov writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(1) | 6520d98c2cSAsen Dimov AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(1), 6620d98c2cSAsen Dimov &smc->cs[3].setup); 6720d98c2cSAsen Dimov 6820d98c2cSAsen Dimov writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(3) | 6920d98c2cSAsen Dimov AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(3), 7020d98c2cSAsen Dimov &smc->cs[3].pulse); 7120d98c2cSAsen Dimov 7220d98c2cSAsen Dimov writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(5), 7320d98c2cSAsen Dimov &smc->cs[3].cycle); 7420d98c2cSAsen Dimov 7520d98c2cSAsen Dimov writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE | 7620d98c2cSAsen Dimov AT91_SMC_MODE_EXNW_DISABLE | 77f0a2c7b4SIlko Iliev #ifdef CONFIG_SYS_NAND_DBW_16 7820d98c2cSAsen Dimov AT91_SMC_MODE_DBW_16 | 79f0a2c7b4SIlko Iliev #else /* CONFIG_SYS_NAND_DBW_8 */ 8020d98c2cSAsen Dimov AT91_SMC_MODE_DBW_8 | 81f0a2c7b4SIlko Iliev #endif 8220d98c2cSAsen Dimov AT91_SMC_MODE_TDF_CYCLE(2), 8320d98c2cSAsen Dimov &smc->cs[3].mode); 84f0a2c7b4SIlko Iliev 85f0a2c7b4SIlko Iliev /* Configure RDY/BSY */ 8620d98c2cSAsen Dimov at91_set_pio_input(CONFIG_SYS_NAND_READY_PIN, 1); 87f0a2c7b4SIlko Iliev 88f0a2c7b4SIlko Iliev /* Enable NandFlash */ 8920d98c2cSAsen Dimov at91_set_pio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1); 90f0a2c7b4SIlko Iliev } 91f0a2c7b4SIlko Iliev #endif 92f0a2c7b4SIlko Iliev 93f0a2c7b4SIlko Iliev #ifdef CONFIG_MACB 94f0a2c7b4SIlko Iliev static void pm9263_macb_hw_init(void) 95f0a2c7b4SIlko Iliev { 96684a567aSAsen Dimov struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; 9720d98c2cSAsen Dimov 98f0a2c7b4SIlko Iliev /* 99f0a2c7b4SIlko Iliev * PB27 enables the 50MHz oscillator for Ethernet PHY 100f0a2c7b4SIlko Iliev * 1 - enable 101f0a2c7b4SIlko Iliev * 0 - disable 102f0a2c7b4SIlko Iliev */ 10320d98c2cSAsen Dimov at91_set_pio_output(AT91_PIO_PORTB, 27, 1); 10420d98c2cSAsen Dimov at91_set_pio_value(AT91_PIO_PORTB, 27, 1); /* 1- enable, 0 - disable */ 105f0a2c7b4SIlko Iliev 106f0a2c7b4SIlko Iliev /* Enable clock */ 107684a567aSAsen Dimov writel(1 << ATMEL_ID_EMAC, &pmc->pcer); 108f0a2c7b4SIlko Iliev 109f0a2c7b4SIlko Iliev /* 110f0a2c7b4SIlko Iliev * Disable pull-up on: 111f0a2c7b4SIlko Iliev * RXDV (PC25) => PHY normal mode (not Test mode) 112f0a2c7b4SIlko Iliev * ERX0 (PE25) => PHY ADDR0 113f0a2c7b4SIlko Iliev * ERX1 (PE26) => PHY ADDR1 => PHYADDR = 0x0 114f0a2c7b4SIlko Iliev * 115f0a2c7b4SIlko Iliev * PHY has internal pull-down 116f0a2c7b4SIlko Iliev */ 117f0a2c7b4SIlko Iliev 11820d98c2cSAsen Dimov at91_set_pio_pullup(AT91_PIO_PORTC, 25, 0); 11920d98c2cSAsen Dimov at91_set_pio_pullup(AT91_PIO_PORTE, 25, 0); 12020d98c2cSAsen Dimov at91_set_pio_pullup(AT91_PIO_PORTE, 26, 0); 121f0a2c7b4SIlko Iliev 122f0a2c7b4SIlko Iliev /* Re-enable pull-up */ 12320d98c2cSAsen Dimov at91_set_pio_pullup(AT91_PIO_PORTC, 25, 1); 12420d98c2cSAsen Dimov at91_set_pio_pullup(AT91_PIO_PORTE, 25, 1); 12520d98c2cSAsen Dimov at91_set_pio_pullup(AT91_PIO_PORTE, 26, 1); 126f0a2c7b4SIlko Iliev 127f0a2c7b4SIlko Iliev at91_macb_hw_init(); 128f0a2c7b4SIlko Iliev } 129f0a2c7b4SIlko Iliev #endif 130f0a2c7b4SIlko Iliev 131f0a2c7b4SIlko Iliev #ifdef CONFIG_LCD 132f0a2c7b4SIlko Iliev vidinfo_t panel_info = { 133f0a2c7b4SIlko Iliev vl_col: 240, 134f0a2c7b4SIlko Iliev vl_row: 320, 135f0a2c7b4SIlko Iliev vl_clk: 4965000, 136f0a2c7b4SIlko Iliev vl_sync: ATMEL_LCDC_INVLINE_INVERTED | 137f0a2c7b4SIlko Iliev ATMEL_LCDC_INVFRAME_INVERTED, 138f0a2c7b4SIlko Iliev vl_bpix: 3, 139f0a2c7b4SIlko Iliev vl_tft: 1, 140f0a2c7b4SIlko Iliev vl_hsync_len: 5, 141f0a2c7b4SIlko Iliev vl_left_margin: 1, 142f0a2c7b4SIlko Iliev vl_right_margin:33, 143f0a2c7b4SIlko Iliev vl_vsync_len: 1, 144f0a2c7b4SIlko Iliev vl_upper_margin:1, 145f0a2c7b4SIlko Iliev vl_lower_margin:0, 146684a567aSAsen Dimov mmio: ATMEL_BASE_LCDC, 147f0a2c7b4SIlko Iliev }; 148f0a2c7b4SIlko Iliev 149f0a2c7b4SIlko Iliev void lcd_enable(void) 150f0a2c7b4SIlko Iliev { 15120d98c2cSAsen Dimov at91_set_pio_value(AT91_PIO_PORTA, 22, 1); /* power up */ 152f0a2c7b4SIlko Iliev } 153f0a2c7b4SIlko Iliev 154f0a2c7b4SIlko Iliev void lcd_disable(void) 155f0a2c7b4SIlko Iliev { 15620d98c2cSAsen Dimov at91_set_pio_value(AT91_PIO_PORTA, 22, 0); /* power down */ 157f0a2c7b4SIlko Iliev } 158f0a2c7b4SIlko Iliev 159f0a2c7b4SIlko Iliev #ifdef CONFIG_LCD_IN_PSRAM 160f0a2c7b4SIlko Iliev 16120d98c2cSAsen Dimov #define PSRAM_CRE_PIN AT91_PIO_PORTB, 29 162f0a2c7b4SIlko Iliev #define PSRAM_CTRL_REG (PHYS_PSRAM + PHYS_PSRAM_SIZE - 2) 163f0a2c7b4SIlko Iliev 164f0a2c7b4SIlko Iliev /* Initialize the PSRAM memory */ 165f0a2c7b4SIlko Iliev static int pm9263_lcd_hw_psram_init(void) 166f0a2c7b4SIlko Iliev { 1677a11c7f9SJean-Christophe PLAGNIOL-VILLARD unsigned long csa; 168684a567aSAsen Dimov struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC1; 169684a567aSAsen Dimov struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX; 1707a11c7f9SJean-Christophe PLAGNIOL-VILLARD 1717a11c7f9SJean-Christophe PLAGNIOL-VILLARD /* Enable CS3 3.3v, no pull-ups */ 17220d98c2cSAsen Dimov csa = readl(&matrix->csa[1]) | AT91_MATRIX_CSA_DBPUC | 17320d98c2cSAsen Dimov AT91_MATRIX_CSA_VDDIOMSEL_3_3V; 17420d98c2cSAsen Dimov 17520d98c2cSAsen Dimov writel(csa, &matrix->csa[1]); 1767a11c7f9SJean-Christophe PLAGNIOL-VILLARD 1777a11c7f9SJean-Christophe PLAGNIOL-VILLARD /* Configure SMC1 CS0 for PSRAM - 16-bit */ 17820d98c2cSAsen Dimov writel(AT91_SMC_SETUP_NWE(0) | AT91_SMC_SETUP_NCS_WR(0) | 17920d98c2cSAsen Dimov AT91_SMC_SETUP_NRD(0) | AT91_SMC_SETUP_NCS_RD(0), 18020d98c2cSAsen Dimov &smc->cs[0].setup); 18120d98c2cSAsen Dimov 18220d98c2cSAsen Dimov writel(AT91_SMC_PULSE_NWE(7) | AT91_SMC_PULSE_NCS_WR(7) | 18320d98c2cSAsen Dimov AT91_SMC_PULSE_NRD(2) | AT91_SMC_PULSE_NCS_RD(7), 18420d98c2cSAsen Dimov &smc->cs[0].pulse); 18520d98c2cSAsen Dimov 18620d98c2cSAsen Dimov writel(AT91_SMC_CYCLE_NWE(8) | AT91_SMC_CYCLE_NRD(8), 18720d98c2cSAsen Dimov &smc->cs[0].cycle); 18820d98c2cSAsen Dimov 18920d98c2cSAsen Dimov writel(AT91_SMC_MODE_DBW_16 | AT91_SMC_MODE_PMEN | AT91_SMC_MODE_PS_32, 19020d98c2cSAsen Dimov &smc->cs[0].mode); 191f0a2c7b4SIlko Iliev 192f0a2c7b4SIlko Iliev /* setup PB29 as output */ 19320d98c2cSAsen Dimov at91_set_pio_output(PSRAM_CRE_PIN, 1); 194f0a2c7b4SIlko Iliev 19520d98c2cSAsen Dimov at91_set_pio_value(PSRAM_CRE_PIN, 0); /* set PSRAM_CRE_PIN to '0' */ 196f0a2c7b4SIlko Iliev 197f0a2c7b4SIlko Iliev /* PSRAM: write BCR */ 198*0a59b711SAnatolij Gustschin readw(PSRAM_CTRL_REG); 199*0a59b711SAnatolij Gustschin readw(PSRAM_CTRL_REG); 200f0a2c7b4SIlko Iliev writew(1, PSRAM_CTRL_REG); /* 0 - RCR,1 - BCR */ 201f0a2c7b4SIlko Iliev writew(0x9d4f, PSRAM_CTRL_REG); /* write the BCR */ 202f0a2c7b4SIlko Iliev 203f0a2c7b4SIlko Iliev /* write RCR of the PSRAM */ 204*0a59b711SAnatolij Gustschin readw(PSRAM_CTRL_REG); 205*0a59b711SAnatolij Gustschin readw(PSRAM_CTRL_REG); 206f0a2c7b4SIlko Iliev writew(0, PSRAM_CTRL_REG); /* 0 - RCR,1 - BCR */ 207f0a2c7b4SIlko Iliev /* set RCR; 0x10-async mode,0x90-page mode */ 208f0a2c7b4SIlko Iliev writew(0x90, PSRAM_CTRL_REG); 209f0a2c7b4SIlko Iliev 210f0a2c7b4SIlko Iliev /* 211f0a2c7b4SIlko Iliev * test to see if the PSRAM is MT45W2M16A or MT45W2M16B 212f0a2c7b4SIlko Iliev * MT45W2M16B - CRE must be 0 213f0a2c7b4SIlko Iliev * MT45W2M16A - CRE must be 1 214f0a2c7b4SIlko Iliev */ 215f0a2c7b4SIlko Iliev writew(0x1234, PHYS_PSRAM); 216f0a2c7b4SIlko Iliev writew(0x5678, PHYS_PSRAM + 2); 217f0a2c7b4SIlko Iliev 218f0a2c7b4SIlko Iliev /* test if the chip is MT45W2M16B */ 219f0a2c7b4SIlko Iliev if ((readw(PHYS_PSRAM) != 0x1234) || (readw(PHYS_PSRAM+2) != 0x5678)) { 220f0a2c7b4SIlko Iliev /* try with CRE=1 (MT45W2M16A) */ 22120d98c2cSAsen Dimov at91_set_pio_value(PSRAM_CRE_PIN, 1); /* set PSRAM_CRE_PIN to '1' */ 222f0a2c7b4SIlko Iliev 223f0a2c7b4SIlko Iliev /* write RCR of the PSRAM */ 224*0a59b711SAnatolij Gustschin readw(PSRAM_CTRL_REG); 225*0a59b711SAnatolij Gustschin readw(PSRAM_CTRL_REG); 226f0a2c7b4SIlko Iliev writew(0, PSRAM_CTRL_REG); /* 0 - RCR,1 - BCR */ 227f0a2c7b4SIlko Iliev /* set RCR;0x10-async mode,0x90-page mode */ 228f0a2c7b4SIlko Iliev writew(0x90, PSRAM_CTRL_REG); 229f0a2c7b4SIlko Iliev 230f0a2c7b4SIlko Iliev 231f0a2c7b4SIlko Iliev writew(0x1234, PHYS_PSRAM); 232f0a2c7b4SIlko Iliev writew(0x5678, PHYS_PSRAM+2); 233f0a2c7b4SIlko Iliev if ((readw(PHYS_PSRAM) != 0x1234) 234f0a2c7b4SIlko Iliev || (readw(PHYS_PSRAM + 2) != 0x5678)) 235f0a2c7b4SIlko Iliev return 1; 236f0a2c7b4SIlko Iliev 237f0a2c7b4SIlko Iliev } 238f0a2c7b4SIlko Iliev 239f0a2c7b4SIlko Iliev /* Bus matrix */ 24020d98c2cSAsen Dimov writel(AT91_MATRIX_PRA_M5(3), &matrix->pr[5].a); 24120d98c2cSAsen Dimov writel(CONFIG_PSRAM_SCFG, &matrix->scfg[5]); 242f0a2c7b4SIlko Iliev 243f0a2c7b4SIlko Iliev return 0; 244f0a2c7b4SIlko Iliev } 245f0a2c7b4SIlko Iliev #endif 246f0a2c7b4SIlko Iliev 247f0a2c7b4SIlko Iliev static void pm9263_lcd_hw_init(void) 248f0a2c7b4SIlko Iliev { 249684a567aSAsen Dimov struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; 250f0a2c7b4SIlko Iliev 25120d98c2cSAsen Dimov at91_set_a_periph(AT91_PIO_PORTC, 0, 0); /* LCDVSYNC */ 25220d98c2cSAsen Dimov at91_set_a_periph(AT91_PIO_PORTC, 1, 0); /* LCDHSYNC */ 25320d98c2cSAsen Dimov at91_set_a_periph(AT91_PIO_PORTC, 2, 0); /* LCDDOTCK */ 25420d98c2cSAsen Dimov at91_set_a_periph(AT91_PIO_PORTC, 3, 0); /* LCDDEN */ 25520d98c2cSAsen Dimov at91_set_b_periph(AT91_PIO_PORTB, 9, 0); /* LCDCC */ 25620d98c2cSAsen Dimov at91_set_a_periph(AT91_PIO_PORTC, 6, 0); /* LCDD2 */ 25720d98c2cSAsen Dimov at91_set_a_periph(AT91_PIO_PORTC, 7, 0); /* LCDD3 */ 25820d98c2cSAsen Dimov at91_set_a_periph(AT91_PIO_PORTC, 8, 0); /* LCDD4 */ 25920d98c2cSAsen Dimov at91_set_a_periph(AT91_PIO_PORTC, 9, 0); /* LCDD5 */ 26020d98c2cSAsen Dimov at91_set_a_periph(AT91_PIO_PORTC, 10, 0); /* LCDD6 */ 26120d98c2cSAsen Dimov at91_set_a_periph(AT91_PIO_PORTC, 11, 0); /* LCDD7 */ 26220d98c2cSAsen Dimov at91_set_a_periph(AT91_PIO_PORTC, 14, 0); /* LCDD10 */ 26320d98c2cSAsen Dimov at91_set_a_periph(AT91_PIO_PORTC, 15, 0); /* LCDD11 */ 26420d98c2cSAsen Dimov at91_set_a_periph(AT91_PIO_PORTC, 16, 0); /* LCDD12 */ 26520d98c2cSAsen Dimov at91_set_b_periph(AT91_PIO_PORTC, 12, 0); /* LCDD13 */ 26620d98c2cSAsen Dimov at91_set_a_periph(AT91_PIO_PORTC, 18, 0); /* LCDD14 */ 26720d98c2cSAsen Dimov at91_set_a_periph(AT91_PIO_PORTC, 19, 0); /* LCDD15 */ 26820d98c2cSAsen Dimov at91_set_a_periph(AT91_PIO_PORTC, 22, 0); /* LCDD18 */ 26920d98c2cSAsen Dimov at91_set_a_periph(AT91_PIO_PORTC, 23, 0); /* LCDD19 */ 27020d98c2cSAsen Dimov at91_set_a_periph(AT91_PIO_PORTC, 24, 0); /* LCDD20 */ 27120d98c2cSAsen Dimov at91_set_b_periph(AT91_PIO_PORTC, 17, 0); /* LCDD21 */ 27220d98c2cSAsen Dimov at91_set_a_periph(AT91_PIO_PORTC, 26, 0); /* LCDD22 */ 27320d98c2cSAsen Dimov at91_set_a_periph(AT91_PIO_PORTC, 27, 0); /* LCDD23 */ 27420d98c2cSAsen Dimov 275684a567aSAsen Dimov writel(1 << ATMEL_ID_LCDC, &pmc->pcer); 276f0a2c7b4SIlko Iliev 277f0a2c7b4SIlko Iliev /* Power Control */ 27820d98c2cSAsen Dimov at91_set_pio_output(AT91_PIO_PORTA, 22, 1); 27920d98c2cSAsen Dimov at91_set_pio_value(AT91_PIO_PORTA, 22, 0); /* power down */ 280f0a2c7b4SIlko Iliev 281f0a2c7b4SIlko Iliev #ifdef CONFIG_LCD_IN_PSRAM 282f0a2c7b4SIlko Iliev /* initialize te PSRAM */ 283f0a2c7b4SIlko Iliev int stat = pm9263_lcd_hw_psram_init(); 284f0a2c7b4SIlko Iliev 285684a567aSAsen Dimov gd->fb_base = (stat == 0) ? PHYS_PSRAM : ATMEL_BASE_SRAM0; 286f0a2c7b4SIlko Iliev #else 287684a567aSAsen Dimov gd->fb_base = ATMEL_BASE_SRAM0; 288f0a2c7b4SIlko Iliev #endif 289f0a2c7b4SIlko Iliev 290f0a2c7b4SIlko Iliev } 291f0a2c7b4SIlko Iliev 292f0a2c7b4SIlko Iliev #ifdef CONFIG_LCD_INFO 293f0a2c7b4SIlko Iliev #include <nand.h> 294f0a2c7b4SIlko Iliev #include <version.h> 295f0a2c7b4SIlko Iliev 296f0a2c7b4SIlko Iliev extern flash_info_t flash_info[]; 297f0a2c7b4SIlko Iliev 298f0a2c7b4SIlko Iliev void lcd_show_board_info(void) 299f0a2c7b4SIlko Iliev { 300f0a2c7b4SIlko Iliev ulong dram_size, nand_size, flash_size, dataflash_size; 301f0a2c7b4SIlko Iliev int i; 302f0a2c7b4SIlko Iliev char temp[32]; 303f0a2c7b4SIlko Iliev 304f0a2c7b4SIlko Iliev lcd_printf ("%s\n", U_BOOT_VERSION); 305f0a2c7b4SIlko Iliev lcd_printf ("(C) 2009 Ronetix GmbH\n"); 306f0a2c7b4SIlko Iliev lcd_printf ("support@ronetix.at\n"); 307f0a2c7b4SIlko Iliev lcd_printf ("%s CPU at %s MHz", 3087c966a8bSAchim Ehrlich CONFIG_SYS_AT91_CPU_NAME, 309f0a2c7b4SIlko Iliev strmhz(temp, get_cpu_clk_rate())); 310f0a2c7b4SIlko Iliev 311f0a2c7b4SIlko Iliev dram_size = 0; 312f0a2c7b4SIlko Iliev for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) 313f0a2c7b4SIlko Iliev dram_size += gd->bd->bi_dram[i].size; 314f0a2c7b4SIlko Iliev 315f0a2c7b4SIlko Iliev nand_size = 0; 316f0a2c7b4SIlko Iliev for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++) 317f0a2c7b4SIlko Iliev nand_size += nand_info[i].size; 318f0a2c7b4SIlko Iliev 319f0a2c7b4SIlko Iliev flash_size = 0; 320f0a2c7b4SIlko Iliev for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) 321f0a2c7b4SIlko Iliev flash_size += flash_info[i].size; 322f0a2c7b4SIlko Iliev 323f0a2c7b4SIlko Iliev dataflash_size = 0; 324f0a2c7b4SIlko Iliev for (i = 0; i < CONFIG_SYS_MAX_DATAFLASH_BANKS; i++) 325f0a2c7b4SIlko Iliev dataflash_size += (unsigned int) dataflash_info[i].Device.pages_number * 326f0a2c7b4SIlko Iliev dataflash_info[i].Device.pages_size; 327f0a2c7b4SIlko Iliev 328f0a2c7b4SIlko Iliev lcd_printf ("%ld MB SDRAM, %ld MB NAND\n%ld MB NOR Flash\n" 329f0a2c7b4SIlko Iliev "4 MB PSRAM, %ld MB DataFlash\n", 330f0a2c7b4SIlko Iliev dram_size >> 20, 331f0a2c7b4SIlko Iliev nand_size >> 20, 332f0a2c7b4SIlko Iliev flash_size >> 20, 333f0a2c7b4SIlko Iliev dataflash_size >> 20); 334f0a2c7b4SIlko Iliev } 335f0a2c7b4SIlko Iliev #endif /* CONFIG_LCD_INFO */ 336f0a2c7b4SIlko Iliev 337f0a2c7b4SIlko Iliev #endif /* CONFIG_LCD */ 338f0a2c7b4SIlko Iliev 339f0a2c7b4SIlko Iliev int board_init(void) 340f0a2c7b4SIlko Iliev { 341684a567aSAsen Dimov struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; 34220d98c2cSAsen Dimov 343f0a2c7b4SIlko Iliev /* Enable Ctrlc */ 344f0a2c7b4SIlko Iliev console_init_f(); 345f0a2c7b4SIlko Iliev 346684a567aSAsen Dimov writel((1 << ATMEL_ID_PIOA) | 347684a567aSAsen Dimov (1 << ATMEL_ID_PIOCDE) | 348684a567aSAsen Dimov (1 << ATMEL_ID_PIOB), 34920d98c2cSAsen Dimov &pmc->pcer); 350f0a2c7b4SIlko Iliev 351f0a2c7b4SIlko Iliev /* arch number of AT91SAM9263EK-Board */ 352f0a2c7b4SIlko Iliev gd->bd->bi_arch_number = MACH_TYPE_PM9263; 353f0a2c7b4SIlko Iliev 354f0a2c7b4SIlko Iliev /* adress of boot parameters */ 355f0a2c7b4SIlko Iliev gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; 356f0a2c7b4SIlko Iliev 357684a567aSAsen Dimov at91_seriald_hw_init(); 358f0a2c7b4SIlko Iliev #ifdef CONFIG_CMD_NAND 359f0a2c7b4SIlko Iliev pm9263_nand_hw_init(); 360f0a2c7b4SIlko Iliev #endif 361f0a2c7b4SIlko Iliev #ifdef CONFIG_HAS_DATAFLASH 362f0a2c7b4SIlko Iliev at91_spi0_hw_init(1 << 0); 363f0a2c7b4SIlko Iliev #endif 364f0a2c7b4SIlko Iliev #ifdef CONFIG_MACB 365f0a2c7b4SIlko Iliev pm9263_macb_hw_init(); 366f0a2c7b4SIlko Iliev #endif 367f0a2c7b4SIlko Iliev #ifdef CONFIG_USB_OHCI_NEW 368f0a2c7b4SIlko Iliev at91_uhp_hw_init(); 369f0a2c7b4SIlko Iliev #endif 370f0a2c7b4SIlko Iliev #ifdef CONFIG_LCD 371f0a2c7b4SIlko Iliev pm9263_lcd_hw_init(); 372f0a2c7b4SIlko Iliev #endif 373f0a2c7b4SIlko Iliev return 0; 374f0a2c7b4SIlko Iliev } 375f0a2c7b4SIlko Iliev 376f0a2c7b4SIlko Iliev int dram_init(void) 377f0a2c7b4SIlko Iliev { 3789a2a05a4SAsen Dimov /* dram_init must store complete ramsize in gd->ram_size */ 379a55d23ccSAlbert ARIBAUD gd->ram_size = get_ram_size((void *)PHYS_SDRAM, 3809a2a05a4SAsen Dimov PHYS_SDRAM_SIZE); 3819a2a05a4SAsen Dimov return 0; 3829a2a05a4SAsen Dimov } 3839a2a05a4SAsen Dimov 3849a2a05a4SAsen Dimov void dram_init_banksize(void) 3859a2a05a4SAsen Dimov { 386f0a2c7b4SIlko Iliev gd->bd->bi_dram[0].start = PHYS_SDRAM; 387f0a2c7b4SIlko Iliev gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE; 388f0a2c7b4SIlko Iliev } 389f0a2c7b4SIlko Iliev 390f0a2c7b4SIlko Iliev #ifdef CONFIG_RESET_PHY_R 391f0a2c7b4SIlko Iliev void reset_phy(void) 392f0a2c7b4SIlko Iliev { 393f0a2c7b4SIlko Iliev } 394f0a2c7b4SIlko Iliev #endif 395f0a2c7b4SIlko Iliev 396f0a2c7b4SIlko Iliev int board_eth_init(bd_t *bis) 397f0a2c7b4SIlko Iliev { 398f0a2c7b4SIlko Iliev int rc = 0; 399f0a2c7b4SIlko Iliev #ifdef CONFIG_MACB 400684a567aSAsen Dimov rc = macb_eth_initialize(0, (void *)ATMEL_BASE_EMAC, 0x01); 401f0a2c7b4SIlko Iliev #endif 402f0a2c7b4SIlko Iliev return rc; 403f0a2c7b4SIlko Iliev } 404f0a2c7b4SIlko Iliev 405f0a2c7b4SIlko Iliev #ifdef CONFIG_DISPLAY_BOARDINFO 406f0a2c7b4SIlko Iliev int checkboard (void) 407f0a2c7b4SIlko Iliev { 408f0a2c7b4SIlko Iliev char *ss; 409f0a2c7b4SIlko Iliev 410f0a2c7b4SIlko Iliev printf ("Board : Ronetix PM9263\n"); 411f0a2c7b4SIlko Iliev 412f0a2c7b4SIlko Iliev switch (gd->fb_base) { 413f0a2c7b4SIlko Iliev case PHYS_PSRAM: 414f0a2c7b4SIlko Iliev ss = "(PSRAM)"; 415f0a2c7b4SIlko Iliev break; 416f0a2c7b4SIlko Iliev 417684a567aSAsen Dimov case ATMEL_BASE_SRAM0: 418f0a2c7b4SIlko Iliev ss = "(Internal SRAM)"; 419f0a2c7b4SIlko Iliev break; 420f0a2c7b4SIlko Iliev 421f0a2c7b4SIlko Iliev default: 422f0a2c7b4SIlko Iliev ss = ""; 423f0a2c7b4SIlko Iliev break; 424f0a2c7b4SIlko Iliev } 425f0a2c7b4SIlko Iliev printf("Video memory : 0x%08lX %s\n", gd->fb_base, ss ); 426f0a2c7b4SIlko Iliev 427f0a2c7b4SIlko Iliev printf ("\n"); 428f0a2c7b4SIlko Iliev return 0; 429f0a2c7b4SIlko Iliev } 430f0a2c7b4SIlko Iliev #endif 431