1 /* 2 * (C) Copyright 2007-2008 3 * Stelian Pop <stelian@popies.net> 4 * Lead Tech Design <www.leadtechdesign.com> 5 * Copyright (C) 2008 Ronetix Ilko Iliev (www.ronetix.at) 6 * Copyright (C) 2009 Jean-Christopher PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> 7 * 8 * SPDX-License-Identifier: GPL-2.0+ 9 */ 10 11 #include <common.h> 12 #include <linux/sizes.h> 13 #include <asm/io.h> 14 #include <asm/gpio.h> 15 #include <asm/arch/at91sam9_smc.h> 16 #include <asm/arch/at91_common.h> 17 #include <asm/arch/at91_rstc.h> 18 #include <asm/arch/at91_matrix.h> 19 #include <asm/arch/clk.h> 20 #include <asm/arch/gpio.h> 21 22 #include <lcd.h> 23 #include <atmel_lcdc.h> 24 #include <dataflash.h> 25 #if defined(CONFIG_RESET_PHY_R) && defined(CONFIG_DRIVER_DM9000) 26 #include <net.h> 27 #endif 28 #include <netdev.h> 29 #include <asm/mach-types.h> 30 31 DECLARE_GLOBAL_DATA_PTR; 32 33 /* ------------------------------------------------------------------------- */ 34 /* 35 * Miscelaneous platform dependent initialisations 36 */ 37 38 #ifdef CONFIG_CMD_NAND 39 static void pm9261_nand_hw_init(void) 40 { 41 unsigned long csa; 42 struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC; 43 struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX; 44 45 /* Enable CS3 */ 46 csa = readl(&matrix->csa) | AT91_MATRIX_CSA_EBI_CS3A; 47 writel(csa, &matrix->csa); 48 49 /* Configure SMC CS3 for NAND/SmartMedia */ 50 writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(0) | 51 AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(0), 52 &smc->cs[3].setup); 53 54 writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(3) | 55 AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(3), 56 &smc->cs[3].pulse); 57 58 writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(5), 59 &smc->cs[3].cycle); 60 61 writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE | 62 AT91_SMC_MODE_EXNW_DISABLE | 63 #ifdef CONFIG_SYS_NAND_DBW_16 64 AT91_SMC_MODE_DBW_16 | 65 #else /* CONFIG_SYS_NAND_DBW_8 */ 66 AT91_SMC_MODE_DBW_8 | 67 #endif 68 AT91_SMC_MODE_TDF_CYCLE(2), 69 &smc->cs[3].mode); 70 71 at91_periph_clk_enable(ATMEL_ID_PIOA); 72 at91_periph_clk_enable(ATMEL_ID_PIOC); 73 74 /* Configure RDY/BSY */ 75 gpio_direction_input(CONFIG_SYS_NAND_READY_PIN); 76 77 /* Enable NandFlash */ 78 gpio_direction_output(CONFIG_SYS_NAND_ENABLE_PIN, 1); 79 80 at91_set_a_periph(AT91_PIO_PORTC, 0, 0); /* NANDOE */ 81 at91_set_a_periph(AT91_PIO_PORTC, 1, 0); /* NANDWE */ 82 } 83 #endif 84 85 86 #ifdef CONFIG_DRIVER_DM9000 87 static void pm9261_dm9000_hw_init(void) 88 { 89 struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC; 90 91 /* Configure SMC CS2 for DM9000 */ 92 writel(AT91_SMC_SETUP_NWE(2) | AT91_SMC_SETUP_NCS_WR(0) | 93 AT91_SMC_SETUP_NRD(2) | AT91_SMC_SETUP_NCS_RD(0), 94 &smc->cs[2].setup); 95 96 writel(AT91_SMC_PULSE_NWE(4) | AT91_SMC_PULSE_NCS_WR(8) | 97 AT91_SMC_PULSE_NRD(4) | AT91_SMC_PULSE_NCS_RD(8), 98 &smc->cs[2].pulse); 99 100 writel(AT91_SMC_CYCLE_NWE(16) | AT91_SMC_CYCLE_NRD(16), 101 &smc->cs[2].cycle); 102 103 writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE | 104 AT91_SMC_MODE_EXNW_DISABLE | 105 AT91_SMC_MODE_BAT | AT91_SMC_MODE_DBW_16 | 106 AT91_SMC_MODE_TDF_CYCLE(1), 107 &smc->cs[2].mode); 108 109 /* Configure Interrupt pin as input, no pull-up */ 110 at91_periph_clk_enable(ATMEL_ID_PIOA); 111 at91_set_pio_input(AT91_PIO_PORTA, 24, 0); 112 } 113 #endif 114 115 #ifdef CONFIG_LCD 116 vidinfo_t panel_info = { 117 .vl_col = 240, 118 .vl_row = 320, 119 .vl_clk = 4965000, 120 .vl_sync = ATMEL_LCDC_INVLINE_INVERTED | 121 ATMEL_LCDC_INVFRAME_INVERTED, 122 .vl_bpix = 3, 123 .vl_tft = 1, 124 .vl_hsync_len = 5, 125 .vl_left_margin = 1, 126 .vl_right_margin = 33, 127 .vl_vsync_len = 1, 128 .vl_upper_margin = 1, 129 .vl_lower_margin = 0, 130 .mmio = ATMEL_BASE_LCDC, 131 }; 132 133 void lcd_enable(void) 134 { 135 at91_set_pio_value(AT91_PIO_PORTA, 22, 0); /* power up */ 136 } 137 138 void lcd_disable(void) 139 { 140 at91_set_pio_value(AT91_PIO_PORTA, 22, 1); /* power down */ 141 } 142 143 static void pm9261_lcd_hw_init(void) 144 { 145 at91_set_a_periph(AT91_PIO_PORTB, 1, 0); /* LCDHSYNC */ 146 at91_set_a_periph(AT91_PIO_PORTB, 2, 0); /* LCDDOTCK */ 147 at91_set_a_periph(AT91_PIO_PORTB, 3, 0); /* LCDDEN */ 148 at91_set_a_periph(AT91_PIO_PORTB, 4, 0); /* LCDCC */ 149 at91_set_a_periph(AT91_PIO_PORTB, 7, 0); /* LCDD2 */ 150 at91_set_a_periph(AT91_PIO_PORTB, 8, 0); /* LCDD3 */ 151 at91_set_a_periph(AT91_PIO_PORTB, 9, 0); /* LCDD4 */ 152 at91_set_a_periph(AT91_PIO_PORTB, 10, 0); /* LCDD5 */ 153 at91_set_a_periph(AT91_PIO_PORTB, 11, 0); /* LCDD6 */ 154 at91_set_a_periph(AT91_PIO_PORTB, 12, 0); /* LCDD7 */ 155 at91_set_a_periph(AT91_PIO_PORTB, 15, 0); /* LCDD10 */ 156 at91_set_a_periph(AT91_PIO_PORTB, 16, 0); /* LCDD11 */ 157 at91_set_a_periph(AT91_PIO_PORTB, 17, 0); /* LCDD12 */ 158 at91_set_a_periph(AT91_PIO_PORTB, 18, 0); /* LCDD13 */ 159 at91_set_a_periph(AT91_PIO_PORTB, 19, 0); /* LCDD14 */ 160 at91_set_a_periph(AT91_PIO_PORTB, 20, 0); /* LCDD15 */ 161 at91_set_b_periph(AT91_PIO_PORTB, 23, 0); /* LCDD18 */ 162 at91_set_b_periph(AT91_PIO_PORTB, 24, 0); /* LCDD19 */ 163 at91_set_b_periph(AT91_PIO_PORTB, 25, 0); /* LCDD20 */ 164 at91_set_b_periph(AT91_PIO_PORTB, 26, 0); /* LCDD21 */ 165 at91_set_b_periph(AT91_PIO_PORTB, 27, 0); /* LCDD22 */ 166 at91_set_b_periph(AT91_PIO_PORTB, 28, 0); /* LCDD23 */ 167 168 at91_system_clk_enable(AT91_PMC_HCK1); 169 170 gd->fb_base = ATMEL_BASE_SRAM; 171 } 172 173 #ifdef CONFIG_LCD_INFO 174 #include <nand.h> 175 #include <version.h> 176 177 extern flash_info_t flash_info[]; 178 179 void lcd_show_board_info(void) 180 { 181 ulong dram_size, nand_size, flash_size, dataflash_size; 182 int i; 183 char temp[32]; 184 185 lcd_printf ("%s\n", U_BOOT_VERSION); 186 lcd_printf ("(C) 2009 Ronetix GmbH\n"); 187 lcd_printf ("support@ronetix.at\n"); 188 lcd_printf ("%s CPU at %s MHz", 189 CONFIG_SYS_AT91_CPU_NAME, 190 strmhz(temp, get_cpu_clk_rate())); 191 192 dram_size = 0; 193 for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) 194 dram_size += gd->bd->bi_dram[i].size; 195 196 nand_size = 0; 197 for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++) 198 nand_size += get_nand_dev_by_index(i)->size; 199 200 flash_size = 0; 201 for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) 202 flash_size += flash_info[i].size; 203 204 dataflash_size = 0; 205 for (i = 0; i < CONFIG_SYS_MAX_DATAFLASH_BANKS; i++) 206 dataflash_size += (unsigned int) dataflash_info[i].Device.pages_number * 207 dataflash_info[i].Device.pages_size; 208 209 lcd_printf ("%ld MB SDRAM, %ld MB NAND\n%ld MB NOR Flash\n" 210 "%ld MB DataFlash\n", 211 dram_size >> 20, 212 nand_size >> 20, 213 flash_size >> 20, 214 dataflash_size >> 20); 215 } 216 #endif /* CONFIG_LCD_INFO */ 217 218 #endif /* CONFIG_LCD */ 219 220 int board_early_init_f(void) 221 { 222 at91_periph_clk_enable(ATMEL_ID_PIOA); 223 at91_periph_clk_enable(ATMEL_ID_PIOC); 224 225 at91_seriald_hw_init(); 226 227 return 0; 228 } 229 230 int board_init(void) 231 { 232 /* arch number of PM9261-Board */ 233 gd->bd->bi_arch_number = MACH_TYPE_PM9261; 234 235 /* adress of boot parameters */ 236 gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; 237 238 #ifdef CONFIG_CMD_NAND 239 pm9261_nand_hw_init(); 240 #endif 241 #ifdef CONFIG_HAS_DATAFLASH 242 at91_spi0_hw_init(1 << 0); 243 #endif 244 #ifdef CONFIG_DRIVER_DM9000 245 pm9261_dm9000_hw_init(); 246 #endif 247 #ifdef CONFIG_LCD 248 pm9261_lcd_hw_init(); 249 #endif 250 return 0; 251 } 252 253 #ifdef CONFIG_DRIVER_DM9000 254 int board_eth_init(bd_t *bis) 255 { 256 return dm9000_initialize(bis); 257 } 258 #endif 259 260 int dram_init(void) 261 { 262 /* dram_init must store complete ramsize in gd->ram_size */ 263 gd->ram_size = get_ram_size((void *)PHYS_SDRAM, 264 PHYS_SDRAM_SIZE); 265 return 0; 266 } 267 268 int dram_init_banksize(void) 269 { 270 gd->bd->bi_dram[0].start = PHYS_SDRAM; 271 gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE; 272 273 return 0; 274 } 275 276 #ifdef CONFIG_RESET_PHY_R 277 void reset_phy(void) 278 { 279 #ifdef CONFIG_DRIVER_DM9000 280 /* 281 * Initialize ethernet HW addr prior to starting Linux, 282 * needed for nfsroot 283 */ 284 eth_init(); 285 #endif 286 } 287 #endif 288 289 #ifdef CONFIG_DISPLAY_BOARDINFO 290 int checkboard (void) 291 { 292 char buf[32]; 293 294 printf ("Board : Ronetix PM9261\n"); 295 printf ("Crystal frequency: %8s MHz\n", 296 strmhz(buf, get_main_clk_rate())); 297 printf ("CPU clock : %8s MHz\n", 298 strmhz(buf, get_cpu_clk_rate())); 299 printf ("Master clock : %8s MHz\n", 300 strmhz(buf, get_mck_clk_rate())); 301 302 return 0; 303 } 304 #endif 305