1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * (C) Copyright 2007-2008 4 * Stelian Pop <stelian@popies.net> 5 * Lead Tech Design <www.leadtechdesign.com> 6 * Copyright (C) 2008 Ronetix Ilko Iliev (www.ronetix.at) 7 * Copyright (C) 2009 Jean-Christopher PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> 8 */ 9 10 #include <common.h> 11 #include <linux/sizes.h> 12 #include <asm/io.h> 13 #include <asm/gpio.h> 14 #include <asm/arch/at91sam9_smc.h> 15 #include <asm/arch/at91_common.h> 16 #include <asm/arch/at91_rstc.h> 17 #include <asm/arch/at91_matrix.h> 18 #include <asm/arch/clk.h> 19 #include <asm/arch/gpio.h> 20 21 #include <lcd.h> 22 #include <atmel_lcdc.h> 23 #if defined(CONFIG_RESET_PHY_R) && defined(CONFIG_DRIVER_DM9000) 24 #include <net.h> 25 #endif 26 #include <netdev.h> 27 #include <asm/mach-types.h> 28 29 DECLARE_GLOBAL_DATA_PTR; 30 31 /* ------------------------------------------------------------------------- */ 32 /* 33 * Miscelaneous platform dependent initialisations 34 */ 35 36 #ifdef CONFIG_CMD_NAND 37 static void pm9261_nand_hw_init(void) 38 { 39 unsigned long csa; 40 struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC; 41 struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX; 42 43 /* Enable CS3 */ 44 csa = readl(&matrix->csa) | AT91_MATRIX_CSA_EBI_CS3A; 45 writel(csa, &matrix->csa); 46 47 /* Configure SMC CS3 for NAND/SmartMedia */ 48 writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(0) | 49 AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(0), 50 &smc->cs[3].setup); 51 52 writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(3) | 53 AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(3), 54 &smc->cs[3].pulse); 55 56 writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(5), 57 &smc->cs[3].cycle); 58 59 writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE | 60 AT91_SMC_MODE_EXNW_DISABLE | 61 #ifdef CONFIG_SYS_NAND_DBW_16 62 AT91_SMC_MODE_DBW_16 | 63 #else /* CONFIG_SYS_NAND_DBW_8 */ 64 AT91_SMC_MODE_DBW_8 | 65 #endif 66 AT91_SMC_MODE_TDF_CYCLE(2), 67 &smc->cs[3].mode); 68 69 at91_periph_clk_enable(ATMEL_ID_PIOA); 70 at91_periph_clk_enable(ATMEL_ID_PIOC); 71 72 /* Configure RDY/BSY */ 73 gpio_direction_input(CONFIG_SYS_NAND_READY_PIN); 74 75 /* Enable NandFlash */ 76 gpio_direction_output(CONFIG_SYS_NAND_ENABLE_PIN, 1); 77 78 at91_set_a_periph(AT91_PIO_PORTC, 0, 0); /* NANDOE */ 79 at91_set_a_periph(AT91_PIO_PORTC, 1, 0); /* NANDWE */ 80 } 81 #endif 82 83 84 #ifdef CONFIG_DRIVER_DM9000 85 static void pm9261_dm9000_hw_init(void) 86 { 87 struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC; 88 89 /* Configure SMC CS2 for DM9000 */ 90 writel(AT91_SMC_SETUP_NWE(2) | AT91_SMC_SETUP_NCS_WR(0) | 91 AT91_SMC_SETUP_NRD(2) | AT91_SMC_SETUP_NCS_RD(0), 92 &smc->cs[2].setup); 93 94 writel(AT91_SMC_PULSE_NWE(4) | AT91_SMC_PULSE_NCS_WR(8) | 95 AT91_SMC_PULSE_NRD(4) | AT91_SMC_PULSE_NCS_RD(8), 96 &smc->cs[2].pulse); 97 98 writel(AT91_SMC_CYCLE_NWE(16) | AT91_SMC_CYCLE_NRD(16), 99 &smc->cs[2].cycle); 100 101 writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE | 102 AT91_SMC_MODE_EXNW_DISABLE | 103 AT91_SMC_MODE_BAT | AT91_SMC_MODE_DBW_16 | 104 AT91_SMC_MODE_TDF_CYCLE(1), 105 &smc->cs[2].mode); 106 107 /* Configure Interrupt pin as input, no pull-up */ 108 at91_periph_clk_enable(ATMEL_ID_PIOA); 109 at91_set_pio_input(AT91_PIO_PORTA, 24, 0); 110 } 111 #endif 112 113 #ifdef CONFIG_LCD 114 vidinfo_t panel_info = { 115 .vl_col = 240, 116 .vl_row = 320, 117 .vl_clk = 4965000, 118 .vl_sync = ATMEL_LCDC_INVLINE_INVERTED | 119 ATMEL_LCDC_INVFRAME_INVERTED, 120 .vl_bpix = 3, 121 .vl_tft = 1, 122 .vl_hsync_len = 5, 123 .vl_left_margin = 1, 124 .vl_right_margin = 33, 125 .vl_vsync_len = 1, 126 .vl_upper_margin = 1, 127 .vl_lower_margin = 0, 128 .mmio = ATMEL_BASE_LCDC, 129 }; 130 131 void lcd_enable(void) 132 { 133 at91_set_pio_value(AT91_PIO_PORTA, 22, 0); /* power up */ 134 } 135 136 void lcd_disable(void) 137 { 138 at91_set_pio_value(AT91_PIO_PORTA, 22, 1); /* power down */ 139 } 140 141 static void pm9261_lcd_hw_init(void) 142 { 143 at91_set_a_periph(AT91_PIO_PORTB, 1, 0); /* LCDHSYNC */ 144 at91_set_a_periph(AT91_PIO_PORTB, 2, 0); /* LCDDOTCK */ 145 at91_set_a_periph(AT91_PIO_PORTB, 3, 0); /* LCDDEN */ 146 at91_set_a_periph(AT91_PIO_PORTB, 4, 0); /* LCDCC */ 147 at91_set_a_periph(AT91_PIO_PORTB, 7, 0); /* LCDD2 */ 148 at91_set_a_periph(AT91_PIO_PORTB, 8, 0); /* LCDD3 */ 149 at91_set_a_periph(AT91_PIO_PORTB, 9, 0); /* LCDD4 */ 150 at91_set_a_periph(AT91_PIO_PORTB, 10, 0); /* LCDD5 */ 151 at91_set_a_periph(AT91_PIO_PORTB, 11, 0); /* LCDD6 */ 152 at91_set_a_periph(AT91_PIO_PORTB, 12, 0); /* LCDD7 */ 153 at91_set_a_periph(AT91_PIO_PORTB, 15, 0); /* LCDD10 */ 154 at91_set_a_periph(AT91_PIO_PORTB, 16, 0); /* LCDD11 */ 155 at91_set_a_periph(AT91_PIO_PORTB, 17, 0); /* LCDD12 */ 156 at91_set_a_periph(AT91_PIO_PORTB, 18, 0); /* LCDD13 */ 157 at91_set_a_periph(AT91_PIO_PORTB, 19, 0); /* LCDD14 */ 158 at91_set_a_periph(AT91_PIO_PORTB, 20, 0); /* LCDD15 */ 159 at91_set_b_periph(AT91_PIO_PORTB, 23, 0); /* LCDD18 */ 160 at91_set_b_periph(AT91_PIO_PORTB, 24, 0); /* LCDD19 */ 161 at91_set_b_periph(AT91_PIO_PORTB, 25, 0); /* LCDD20 */ 162 at91_set_b_periph(AT91_PIO_PORTB, 26, 0); /* LCDD21 */ 163 at91_set_b_periph(AT91_PIO_PORTB, 27, 0); /* LCDD22 */ 164 at91_set_b_periph(AT91_PIO_PORTB, 28, 0); /* LCDD23 */ 165 166 at91_system_clk_enable(AT91_PMC_HCK1); 167 168 gd->fb_base = ATMEL_BASE_SRAM; 169 } 170 171 #ifdef CONFIG_LCD_INFO 172 #include <nand.h> 173 #include <version.h> 174 175 extern flash_info_t flash_info[]; 176 177 void lcd_show_board_info(void) 178 { 179 ulong dram_size, nand_size, flash_size; 180 int i; 181 char temp[32]; 182 183 lcd_printf ("%s\n", U_BOOT_VERSION); 184 lcd_printf ("(C) 2009 Ronetix GmbH\n"); 185 lcd_printf ("support@ronetix.at\n"); 186 lcd_printf ("%s CPU at %s MHz", 187 CONFIG_SYS_AT91_CPU_NAME, 188 strmhz(temp, get_cpu_clk_rate())); 189 190 dram_size = 0; 191 for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) 192 dram_size += gd->bd->bi_dram[i].size; 193 194 nand_size = 0; 195 for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++) 196 nand_size += get_nand_dev_by_index(i)->size; 197 198 flash_size = 0; 199 for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) 200 flash_size += flash_info[i].size; 201 202 lcd_printf ("%ld MB SDRAM, %ld MB NAND\n%ld MB NOR Flash\n" 203 "%ld MB DataFlash\n", 204 dram_size >> 20, 205 nand_size >> 20, 206 flash_size >> 20); 207 } 208 #endif /* CONFIG_LCD_INFO */ 209 210 #endif /* CONFIG_LCD */ 211 212 int board_early_init_f(void) 213 { 214 return 0; 215 } 216 217 int board_init(void) 218 { 219 /* arch number of PM9261-Board */ 220 gd->bd->bi_arch_number = MACH_TYPE_PM9261; 221 222 /* adress of boot parameters */ 223 gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; 224 225 #ifdef CONFIG_CMD_NAND 226 pm9261_nand_hw_init(); 227 #endif 228 #ifdef CONFIG_DRIVER_DM9000 229 pm9261_dm9000_hw_init(); 230 #endif 231 #ifdef CONFIG_LCD 232 pm9261_lcd_hw_init(); 233 #endif 234 return 0; 235 } 236 237 #ifdef CONFIG_DRIVER_DM9000 238 int board_eth_init(bd_t *bis) 239 { 240 return dm9000_initialize(bis); 241 } 242 #endif 243 244 int dram_init(void) 245 { 246 /* dram_init must store complete ramsize in gd->ram_size */ 247 gd->ram_size = get_ram_size((void *)PHYS_SDRAM, 248 PHYS_SDRAM_SIZE); 249 return 0; 250 } 251 252 int dram_init_banksize(void) 253 { 254 gd->bd->bi_dram[0].start = PHYS_SDRAM; 255 gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE; 256 257 return 0; 258 } 259 260 #ifdef CONFIG_RESET_PHY_R 261 void reset_phy(void) 262 { 263 #ifdef CONFIG_DRIVER_DM9000 264 /* 265 * Initialize ethernet HW addr prior to starting Linux, 266 * needed for nfsroot 267 */ 268 eth_init(); 269 #endif 270 } 271 #endif 272 273 #ifdef CONFIG_DISPLAY_BOARDINFO 274 int checkboard (void) 275 { 276 char buf[32]; 277 278 printf ("Board : Ronetix PM9261\n"); 279 printf ("Crystal frequency: %8s MHz\n", 280 strmhz(buf, get_main_clk_rate())); 281 printf ("CPU clock : %8s MHz\n", 282 strmhz(buf, get_cpu_clk_rate())); 283 printf ("Master clock : %8s MHz\n", 284 strmhz(buf, get_mck_clk_rate())); 285 286 return 0; 287 } 288 #endif 289