1 /* 2 * (C) Copyright 2007-2008 3 * Stelian Pop <stelian@popies.net> 4 * Lead Tech Design <www.leadtechdesign.com> 5 * Copyright (C) 2008 Ronetix Ilko Iliev (www.ronetix.at) 6 * Copyright (C) 2009 Jean-Christopher PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> 7 * 8 * SPDX-License-Identifier: GPL-2.0+ 9 */ 10 11 #include <common.h> 12 #include <asm/sizes.h> 13 #include <asm/io.h> 14 #include <asm/arch/at91sam9_smc.h> 15 #include <asm/arch/at91_common.h> 16 #include <asm/arch/at91_pmc.h> 17 #include <asm/arch/at91_rstc.h> 18 #include <asm/arch/at91_matrix.h> 19 #include <asm/arch/clk.h> 20 #include <asm/arch/gpio.h> 21 22 #include <lcd.h> 23 #include <atmel_lcdc.h> 24 #include <dataflash.h> 25 #if defined(CONFIG_RESET_PHY_R) && defined(CONFIG_DRIVER_DM9000) 26 #include <net.h> 27 #endif 28 #include <netdev.h> 29 30 DECLARE_GLOBAL_DATA_PTR; 31 32 /* ------------------------------------------------------------------------- */ 33 /* 34 * Miscelaneous platform dependent initialisations 35 */ 36 37 #ifdef CONFIG_CMD_NAND 38 static void pm9261_nand_hw_init(void) 39 { 40 unsigned long csa; 41 struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC; 42 struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX; 43 struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; 44 45 /* Enable CS3 */ 46 csa = readl(&matrix->csa) | AT91_MATRIX_CSA_EBI_CS3A; 47 writel(csa, &matrix->csa); 48 49 /* Configure SMC CS3 for NAND/SmartMedia */ 50 writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(0) | 51 AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(0), 52 &smc->cs[3].setup); 53 54 writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(3) | 55 AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(3), 56 &smc->cs[3].pulse); 57 58 writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(5), 59 &smc->cs[3].cycle); 60 61 writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE | 62 AT91_SMC_MODE_EXNW_DISABLE | 63 #ifdef CONFIG_SYS_NAND_DBW_16 64 AT91_SMC_MODE_DBW_16 | 65 #else /* CONFIG_SYS_NAND_DBW_8 */ 66 AT91_SMC_MODE_DBW_8 | 67 #endif 68 AT91_SMC_MODE_TDF_CYCLE(2), 69 &smc->cs[3].mode); 70 71 writel(1 << ATMEL_ID_PIOA | 72 1 << ATMEL_ID_PIOC, 73 &pmc->pcer); 74 75 /* Configure RDY/BSY */ 76 at91_set_pio_input(CONFIG_SYS_NAND_READY_PIN, 1); 77 78 /* Enable NandFlash */ 79 at91_set_pio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1); 80 81 at91_set_a_periph(AT91_PIO_PORTC, 0, 0); /* NANDOE */ 82 at91_set_a_periph(AT91_PIO_PORTC, 1, 0); /* NANDWE */ 83 } 84 #endif 85 86 87 #ifdef CONFIG_DRIVER_DM9000 88 static void pm9261_dm9000_hw_init(void) 89 { 90 struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC; 91 struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; 92 93 /* Configure SMC CS2 for DM9000 */ 94 writel(AT91_SMC_SETUP_NWE(2) | AT91_SMC_SETUP_NCS_WR(0) | 95 AT91_SMC_SETUP_NRD(2) | AT91_SMC_SETUP_NCS_RD(0), 96 &smc->cs[2].setup); 97 98 writel(AT91_SMC_PULSE_NWE(4) | AT91_SMC_PULSE_NCS_WR(8) | 99 AT91_SMC_PULSE_NRD(4) | AT91_SMC_PULSE_NCS_RD(8), 100 &smc->cs[2].pulse); 101 102 writel(AT91_SMC_CYCLE_NWE(16) | AT91_SMC_CYCLE_NRD(16), 103 &smc->cs[2].cycle); 104 105 writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE | 106 AT91_SMC_MODE_EXNW_DISABLE | 107 AT91_SMC_MODE_BAT | AT91_SMC_MODE_DBW_16 | 108 AT91_SMC_MODE_TDF_CYCLE(1), 109 &smc->cs[2].mode); 110 111 /* Configure Interrupt pin as input, no pull-up */ 112 writel(1 << ATMEL_ID_PIOA, &pmc->pcer); 113 at91_set_pio_input(AT91_PIO_PORTA, 24, 0); 114 } 115 #endif 116 117 #ifdef CONFIG_LCD 118 vidinfo_t panel_info = { 119 vl_col: 240, 120 vl_row: 320, 121 vl_clk: 4965000, 122 vl_sync: ATMEL_LCDC_INVLINE_INVERTED | 123 ATMEL_LCDC_INVFRAME_INVERTED, 124 vl_bpix: 3, 125 vl_tft: 1, 126 vl_hsync_len: 5, 127 vl_left_margin: 1, 128 vl_right_margin:33, 129 vl_vsync_len: 1, 130 vl_upper_margin:1, 131 vl_lower_margin:0, 132 mmio: ATMEL_BASE_LCDC, 133 }; 134 135 void lcd_enable(void) 136 { 137 at91_set_pio_value(AT91_PIO_PORTA, 22, 0); /* power up */ 138 } 139 140 void lcd_disable(void) 141 { 142 at91_set_pio_value(AT91_PIO_PORTA, 22, 1); /* power down */ 143 } 144 145 static void pm9261_lcd_hw_init(void) 146 { 147 struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; 148 149 at91_set_a_periph(AT91_PIO_PORTB, 1, 0); /* LCDHSYNC */ 150 at91_set_a_periph(AT91_PIO_PORTB, 2, 0); /* LCDDOTCK */ 151 at91_set_a_periph(AT91_PIO_PORTB, 3, 0); /* LCDDEN */ 152 at91_set_a_periph(AT91_PIO_PORTB, 4, 0); /* LCDCC */ 153 at91_set_a_periph(AT91_PIO_PORTB, 7, 0); /* LCDD2 */ 154 at91_set_a_periph(AT91_PIO_PORTB, 8, 0); /* LCDD3 */ 155 at91_set_a_periph(AT91_PIO_PORTB, 9, 0); /* LCDD4 */ 156 at91_set_a_periph(AT91_PIO_PORTB, 10, 0); /* LCDD5 */ 157 at91_set_a_periph(AT91_PIO_PORTB, 11, 0); /* LCDD6 */ 158 at91_set_a_periph(AT91_PIO_PORTB, 12, 0); /* LCDD7 */ 159 at91_set_a_periph(AT91_PIO_PORTB, 15, 0); /* LCDD10 */ 160 at91_set_a_periph(AT91_PIO_PORTB, 16, 0); /* LCDD11 */ 161 at91_set_a_periph(AT91_PIO_PORTB, 17, 0); /* LCDD12 */ 162 at91_set_a_periph(AT91_PIO_PORTB, 18, 0); /* LCDD13 */ 163 at91_set_a_periph(AT91_PIO_PORTB, 19, 0); /* LCDD14 */ 164 at91_set_a_periph(AT91_PIO_PORTB, 20, 0); /* LCDD15 */ 165 at91_set_b_periph(AT91_PIO_PORTB, 23, 0); /* LCDD18 */ 166 at91_set_b_periph(AT91_PIO_PORTB, 24, 0); /* LCDD19 */ 167 at91_set_b_periph(AT91_PIO_PORTB, 25, 0); /* LCDD20 */ 168 at91_set_b_periph(AT91_PIO_PORTB, 26, 0); /* LCDD21 */ 169 at91_set_b_periph(AT91_PIO_PORTB, 27, 0); /* LCDD22 */ 170 at91_set_b_periph(AT91_PIO_PORTB, 28, 0); /* LCDD23 */ 171 172 writel(1 << 17, &pmc->scer); /* LCD controller Clock, AT91SAM9261 only */ 173 174 gd->fb_base = ATMEL_BASE_SRAM; 175 } 176 177 #ifdef CONFIG_LCD_INFO 178 #include <nand.h> 179 #include <version.h> 180 181 extern flash_info_t flash_info[]; 182 183 void lcd_show_board_info(void) 184 { 185 ulong dram_size, nand_size, flash_size, dataflash_size; 186 int i; 187 char temp[32]; 188 189 lcd_printf ("%s\n", U_BOOT_VERSION); 190 lcd_printf ("(C) 2009 Ronetix GmbH\n"); 191 lcd_printf ("support@ronetix.at\n"); 192 lcd_printf ("%s CPU at %s MHz", 193 CONFIG_SYS_AT91_CPU_NAME, 194 strmhz(temp, get_cpu_clk_rate())); 195 196 dram_size = 0; 197 for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) 198 dram_size += gd->bd->bi_dram[i].size; 199 200 nand_size = 0; 201 for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++) 202 nand_size += nand_info[i].size; 203 204 flash_size = 0; 205 for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) 206 flash_size += flash_info[i].size; 207 208 dataflash_size = 0; 209 for (i = 0; i < CONFIG_SYS_MAX_DATAFLASH_BANKS; i++) 210 dataflash_size += (unsigned int) dataflash_info[i].Device.pages_number * 211 dataflash_info[i].Device.pages_size; 212 213 lcd_printf ("%ld MB SDRAM, %ld MB NAND\n%ld MB NOR Flash\n" 214 "%ld MB DataFlash\n", 215 dram_size >> 20, 216 nand_size >> 20, 217 flash_size >> 20, 218 dataflash_size >> 20); 219 } 220 #endif /* CONFIG_LCD_INFO */ 221 222 #endif /* CONFIG_LCD */ 223 224 int board_early_init_f(void) 225 { 226 struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; 227 228 /* Enable clocks for some PIOs */ 229 writel(1 << ATMEL_ID_PIOA | 230 1 << ATMEL_ID_PIOC, 231 &pmc->pcer); 232 233 at91_seriald_hw_init(); 234 235 return 0; 236 } 237 238 int board_init(void) 239 { 240 /* arch number of PM9261-Board */ 241 gd->bd->bi_arch_number = MACH_TYPE_PM9261; 242 243 /* adress of boot parameters */ 244 gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; 245 246 #ifdef CONFIG_CMD_NAND 247 pm9261_nand_hw_init(); 248 #endif 249 #ifdef CONFIG_HAS_DATAFLASH 250 at91_spi0_hw_init(1 << 0); 251 #endif 252 #ifdef CONFIG_DRIVER_DM9000 253 pm9261_dm9000_hw_init(); 254 #endif 255 #ifdef CONFIG_LCD 256 pm9261_lcd_hw_init(); 257 #endif 258 return 0; 259 } 260 261 #ifdef CONFIG_DRIVER_DM9000 262 int board_eth_init(bd_t *bis) 263 { 264 return dm9000_initialize(bis); 265 } 266 #endif 267 268 int dram_init(void) 269 { 270 /* dram_init must store complete ramsize in gd->ram_size */ 271 gd->ram_size = get_ram_size((void *)PHYS_SDRAM, 272 PHYS_SDRAM_SIZE); 273 return 0; 274 } 275 276 void dram_init_banksize(void) 277 { 278 gd->bd->bi_dram[0].start = PHYS_SDRAM; 279 gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE; 280 } 281 282 #ifdef CONFIG_RESET_PHY_R 283 void reset_phy(void) 284 { 285 #ifdef CONFIG_DRIVER_DM9000 286 /* 287 * Initialize ethernet HW addr prior to starting Linux, 288 * needed for nfsroot 289 */ 290 eth_init(gd->bd); 291 #endif 292 } 293 #endif 294 295 #ifdef CONFIG_DISPLAY_BOARDINFO 296 int checkboard (void) 297 { 298 char buf[32]; 299 300 printf ("Board : Ronetix PM9261\n"); 301 printf ("Crystal frequency: %8s MHz\n", 302 strmhz(buf, get_main_clk_rate())); 303 printf ("CPU clock : %8s MHz\n", 304 strmhz(buf, get_cpu_clk_rate())); 305 printf ("Master clock : %8s MHz\n", 306 strmhz(buf, get_mck_clk_rate())); 307 308 return 0; 309 } 310 #endif 311