1 /*
2  * (C)Copyright 2016 Rockchip Electronics Co., Ltd
3  * Authors: Andy Yan <andy.yan@rock-chips.com>
4  * SPDX-License-Identifier:     GPL-2.0+
5  */
6 
7 #include <common.h>
8 #include <asm/io.h>
9 #include <fdtdec.h>
10 #include <asm/arch/grf_rv1108.h>
11 #include <asm/arch/hardware.h>
12 
13 DECLARE_GLOBAL_DATA_PTR;
14 
15 int mach_cpu_init(void)
16 {
17 	int node;
18 	struct rv1108_grf *grf;
19 	enum {
20 		GPIO3C3_SHIFT           = 6,
21 		GPIO3C3_MASK            = 3 << GPIO3C3_SHIFT,
22 
23 		GPIO3C2_SHIFT           = 4,
24 		GPIO3C2_MASK            = 3 << GPIO3C2_SHIFT,
25 
26 		GPIO2D2_SHIFT		= 4,
27 		GPIO2D2_MASK		= 3 << GPIO2D2_SHIFT,
28 		GPIO2D2_GPIO            = 0,
29 		GPIO2D2_UART2_SOUT_M0,
30 
31 		GPIO2D1_SHIFT		= 2,
32 		GPIO2D1_MASK		= 3 << GPIO2D1_SHIFT,
33 		GPIO2D1_GPIO            = 0,
34 		GPIO2D1_UART2_SIN_M0,
35 	};
36 
37 	node = fdt_node_offset_by_compatible(gd->fdt_blob, -1, "rockchip,rv1108-grf");
38 	grf = (struct rv1108_grf *)fdtdec_get_addr(gd->fdt_blob, node, "reg");
39 
40 	/*evb board use UART2 m0 for debug*/
41 	rk_clrsetreg(&grf->gpio2d_iomux,
42 		     GPIO2D2_MASK | GPIO2D1_MASK,
43 		     GPIO2D2_UART2_SOUT_M0 << GPIO2D2_SHIFT |
44 		     GPIO2D1_UART2_SIN_M0 << GPIO2D1_SHIFT);
45 	rk_clrreg(&grf->gpio3c_iomux, GPIO3C3_MASK | GPIO3C2_MASK);
46 
47 	return 0;
48 }
49 
50 
51 int board_init(void)
52 {
53 	return 0;
54 }
55 
56 int dram_init(void)
57 {
58 	gd->ram_size = 0x8000000;
59 
60 	return 0;
61 }
62 
63 int dram_init_banksize(void)
64 {
65 	gd->bd->bi_dram[0].start = 0x60000000;
66 	gd->bd->bi_dram[0].size = 0x8000000;
67 
68 	return 0;
69 }
70