1*2d1951feSAndy Yan /* 2*2d1951feSAndy Yan * (C)Copyright 2016 Rockchip Electronics Co., Ltd 3*2d1951feSAndy Yan * Authors: Andy Yan <andy.yan@rock-chips.com> 4*2d1951feSAndy Yan * SPDX-License-Identifier: GPL-2.0+ 5*2d1951feSAndy Yan */ 6*2d1951feSAndy Yan 7*2d1951feSAndy Yan #include <common.h> 8*2d1951feSAndy Yan #include <asm/io.h> 9*2d1951feSAndy Yan #include <fdtdec.h> 10*2d1951feSAndy Yan #include <asm/arch/grf_rv1108.h> 11*2d1951feSAndy Yan #include <asm/arch/hardware.h> 12*2d1951feSAndy Yan 13*2d1951feSAndy Yan DECLARE_GLOBAL_DATA_PTR; 14*2d1951feSAndy Yan 15*2d1951feSAndy Yan int mach_cpu_init(void) 16*2d1951feSAndy Yan { 17*2d1951feSAndy Yan int node; 18*2d1951feSAndy Yan struct rv1108_grf *grf; 19*2d1951feSAndy Yan 20*2d1951feSAndy Yan node = fdt_node_offset_by_compatible(gd->fdt_blob, -1, "rockchip,rv1108-grf"); 21*2d1951feSAndy Yan grf = (struct rv1108_grf *)fdtdec_get_addr(gd->fdt_blob, node, "reg"); 22*2d1951feSAndy Yan 23*2d1951feSAndy Yan /*evb board use UART2 m0 for debug*/ 24*2d1951feSAndy Yan rk_clrsetreg(&grf->gpio2d_iomux, 25*2d1951feSAndy Yan GPIO2D2_MASK | GPIO2D1_MASK, 26*2d1951feSAndy Yan GPIO2D2_UART2_SOUT_M0 << GPIO2D2_SHIFT | 27*2d1951feSAndy Yan GPIO2D1_UART2_SIN_M0 << GPIO2D1_SHIFT); 28*2d1951feSAndy Yan rk_clrreg(&grf->gpio3c_iomux, GPIO3C3_MASK | GPIO3C2_MASK); 29*2d1951feSAndy Yan 30*2d1951feSAndy Yan return 0; 31*2d1951feSAndy Yan } 32*2d1951feSAndy Yan 33*2d1951feSAndy Yan 34*2d1951feSAndy Yan int board_init(void) 35*2d1951feSAndy Yan { 36*2d1951feSAndy Yan return 0; 37*2d1951feSAndy Yan } 38*2d1951feSAndy Yan 39*2d1951feSAndy Yan int dram_init(void) 40*2d1951feSAndy Yan { 41*2d1951feSAndy Yan gd->ram_size = 0x8000000; 42*2d1951feSAndy Yan 43*2d1951feSAndy Yan return 0; 44*2d1951feSAndy Yan } 45*2d1951feSAndy Yan 46*2d1951feSAndy Yan int dram_init_banksize(void) 47*2d1951feSAndy Yan { 48*2d1951feSAndy Yan gd->bd->bi_dram[0].start = 0x60000000; 49*2d1951feSAndy Yan gd->bd->bi_dram[0].size = 0x8000000; 50*2d1951feSAndy Yan 51*2d1951feSAndy Yan return 0; 52*2d1951feSAndy Yan } 53