1 /*
2  * (C) Copyright 2016 Rockchip Electronics Co., Ltd
3  *
4  * SPDX-License-Identifier:     GPL-2.0+
5  */
6 #include <common.h>
7 #include <dm.h>
8 #include <ram.h>
9 #include <dm/pinctrl.h>
10 #include <dm/uclass-internal.h>
11 #include <asm/arch/periph.h>
12 #include <power/regulator.h>
13 
14 DECLARE_GLOBAL_DATA_PTR;
15 
16 int board_init(void)
17 {
18 	struct udevice *pinctrl, *regulator;
19 	int ret;
20 
21 	/*
22 	 * The PWM do not have decicated interrupt number in dts and can
23 	 * not get periph_id by pinctrl framework, so let's init them here.
24 	 * The PWM2 and PWM3 are for pwm regulater.
25 	 */
26 	ret = uclass_get_device(UCLASS_PINCTRL, 0, &pinctrl);
27 	if (ret) {
28 		debug("%s: Cannot find pinctrl device\n", __func__);
29 		goto out;
30 	}
31 
32 	/* Enable pwm0 for panel backlight */
33 	ret = pinctrl_request_noflags(pinctrl, PERIPH_ID_PWM0);
34 	if (ret) {
35 		debug("%s PWM0 pinctrl init fail! (ret=%d)\n", __func__, ret);
36 		goto out;
37 	}
38 
39 	ret = pinctrl_request_noflags(pinctrl, PERIPH_ID_PWM2);
40 	if (ret) {
41 		debug("%s PWM2 pinctrl init fail!\n", __func__);
42 		goto out;
43 	}
44 
45 	ret = pinctrl_request_noflags(pinctrl, PERIPH_ID_PWM3);
46 	if (ret) {
47 		debug("%s PWM3 pinctrl init fail!\n", __func__);
48 		goto out;
49 	}
50 
51 	ret = regulators_enable_boot_on(false);
52 	if (ret)
53 		debug("%s: Cannot enable boot on regulator\n", __func__);
54 
55 	ret = regulator_get_by_platname("vcc5v0_host", &regulator);
56 	if (ret) {
57 		debug("%s vcc5v0_host init fail! ret %d\n", __func__, ret);
58 		goto out;
59 	}
60 
61 	ret = regulator_set_enable(regulator, true);
62 	if (ret) {
63 		debug("%s vcc5v0-host-en set fail!\n", __func__);
64 		goto out;
65 	}
66 
67 out:
68 	return 0;
69 }
70 
71 int dram_init(void)
72 {
73 	struct ram_info ram;
74 	struct udevice *dev;
75 	int ret;
76 
77 	ret = uclass_get_device(UCLASS_RAM, 0, &dev);
78 	if (ret) {
79 		debug("DRAM init failed: %d\n", ret);
80 		return ret;
81 	}
82 	ret = ram_get_info(dev, &ram);
83 	if (ret) {
84 		debug("Cannot get DRAM size: %d\n", ret);
85 		return ret;
86 	}
87 	debug("SDRAM base=%llx, size=%x\n", ram.base, (unsigned int)ram.size);
88 	gd->ram_size = ram.size;
89 
90 	return 0;
91 }
92 
93 int dram_init_banksize(void)
94 {
95 	/* Reserve 0x200000 for ATF bl31 */
96 	gd->bd->bi_dram[0].start = 0x200000;
97 	gd->bd->bi_dram[0].size = 0x7e000000;
98 
99 	return 0;
100 }
101