1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * board/renesas/stout/stout.c
4 * This file is Stout board support.
5 *
6 * Copyright (C) 2015 Renesas Electronics Europe GmbH
7 * Copyright (C) 2015 Renesas Electronics Corporation
8 * Copyright (C) 2015 Cogent Embedded, Inc.
9 */
10
11 #include <common.h>
12 #include <malloc.h>
13 #include <netdev.h>
14 #include <dm.h>
15 #include <dm/platform_data/serial_sh.h>
16 #include <environment.h>
17 #include <asm/processor.h>
18 #include <asm/mach-types.h>
19 #include <asm/io.h>
20 #include <linux/errno.h>
21 #include <asm/arch/sys_proto.h>
22 #include <asm/gpio.h>
23 #include <asm/arch/rmobile.h>
24 #include <asm/arch/rcar-mstp.h>
25 #include <asm/arch/mmc.h>
26 #include <asm/arch/sh_sdhi.h>
27 #include <miiphy.h>
28 #include <i2c.h>
29 #include <mmc.h>
30 #include "qos.h"
31 #include "cpld.h"
32
33 DECLARE_GLOBAL_DATA_PTR;
34
35 #define CLK2MHZ(clk) (clk / 1000 / 1000)
s_init(void)36 void s_init(void)
37 {
38 struct rcar_rwdt *rwdt = (struct rcar_rwdt *)RWDT_BASE;
39 struct rcar_swdt *swdt = (struct rcar_swdt *)SWDT_BASE;
40
41 /* Watchdog init */
42 writel(0xA5A5A500, &rwdt->rwtcsra);
43 writel(0xA5A5A500, &swdt->swtcsra);
44
45 /* CPU frequency setting. Set to 1.4GHz */
46 if (rmobile_get_cpu_rev_integer() >= R8A7790_CUT_ES2X) {
47 u32 stat = 0;
48 u32 stc = ((1400 / CLK2MHZ(CONFIG_SYS_CLK_FREQ)) - 1)
49 << PLL0_STC_BIT;
50 clrsetbits_le32(PLL0CR, PLL0_STC_MASK, stc);
51
52 do {
53 stat = readl(PLLECR) & PLL0ST;
54 } while (stat == 0x0);
55 }
56
57 /* QoS(Quality-of-Service) Init */
58 qos_init();
59 }
60
61 #define TMU0_MSTP125 BIT(25)
62
63 #define SD2CKCR 0xE6150078
64 #define SD2_97500KHZ 0x7
65
board_early_init_f(void)66 int board_early_init_f(void)
67 {
68 /* TMU0 */
69 mstp_clrbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125);
70
71 /*
72 * SD0 clock is set to 97.5MHz by default.
73 * Set SD2 to the 97.5MHz as well.
74 */
75 writel(SD2_97500KHZ, SD2CKCR);
76
77 return 0;
78 }
79
80 #define ETHERNET_PHY_RESET 123 /* GPIO 3 31 */
81
board_init(void)82 int board_init(void)
83 {
84 /* adress of boot parameters */
85 gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
86
87 cpld_init();
88
89 /* Force ethernet PHY out of reset */
90 gpio_request(ETHERNET_PHY_RESET, "phy_reset");
91 gpio_direction_output(ETHERNET_PHY_RESET, 0);
92 mdelay(20);
93 gpio_direction_output(ETHERNET_PHY_RESET, 1);
94
95 return 0;
96 }
97
dram_init(void)98 int dram_init(void)
99 {
100 if (fdtdec_setup_mem_size_base() != 0)
101 return -EINVAL;
102
103 return 0;
104 }
105
dram_init_banksize(void)106 int dram_init_banksize(void)
107 {
108 fdtdec_setup_memory_banksize();
109
110 return 0;
111 }
112
113 /* Stout has KSZ8041NL/RNL */
114 #define PHY_CONTROL1 0x1E
115 #define PHY_LED_MODE 0xC000
116 #define PHY_LED_MODE_ACK 0x4000
board_phy_config(struct phy_device * phydev)117 int board_phy_config(struct phy_device *phydev)
118 {
119 int ret = phy_read(phydev, MDIO_DEVAD_NONE, PHY_CONTROL1);
120 ret &= ~PHY_LED_MODE;
121 ret |= PHY_LED_MODE_ACK;
122 ret = phy_write(phydev, MDIO_DEVAD_NONE, PHY_CONTROL1, (u16)ret);
123
124 return 0;
125 }
126
env_get_location(enum env_operation op,int prio)127 enum env_location env_get_location(enum env_operation op, int prio)
128 {
129 const u32 load_magic = 0xb33fc0de;
130
131 /* Block environment access if loaded using JTAG */
132 if ((readl(CONFIG_SPL_TEXT_BASE + 0x24) == load_magic) &&
133 (op != ENVOP_INIT))
134 return ENVL_UNKNOWN;
135
136 if (prio)
137 return ENVL_UNKNOWN;
138
139 return ENVL_SPI_FLASH;
140 }
141