1*21871138SVladimir Barinov /* 2*21871138SVladimir Barinov * board/renesas/stout/stout.c 3*21871138SVladimir Barinov * This file is Stout board support. 4*21871138SVladimir Barinov * 5*21871138SVladimir Barinov * Copyright (C) 2015 Renesas Electronics Europe GmbH 6*21871138SVladimir Barinov * Copyright (C) 2015 Renesas Electronics Corporation 7*21871138SVladimir Barinov * Copyright (C) 2015 Cogent Embedded, Inc. 8*21871138SVladimir Barinov * 9*21871138SVladimir Barinov * SPDX-License-Identifier: GPL-2.0 10*21871138SVladimir Barinov */ 11*21871138SVladimir Barinov 12*21871138SVladimir Barinov #include <common.h> 13*21871138SVladimir Barinov #include <malloc.h> 14*21871138SVladimir Barinov #include <netdev.h> 15*21871138SVladimir Barinov #include <dm.h> 16*21871138SVladimir Barinov #include <dm/platform_data/serial_sh.h> 17*21871138SVladimir Barinov #include <asm/processor.h> 18*21871138SVladimir Barinov #include <asm/mach-types.h> 19*21871138SVladimir Barinov #include <asm/io.h> 20*21871138SVladimir Barinov #include <asm/errno.h> 21*21871138SVladimir Barinov #include <asm/arch/sys_proto.h> 22*21871138SVladimir Barinov #include <asm/gpio.h> 23*21871138SVladimir Barinov #include <asm/arch/rmobile.h> 24*21871138SVladimir Barinov #include <asm/arch/rcar-mstp.h> 25*21871138SVladimir Barinov #include <asm/arch/mmc.h> 26*21871138SVladimir Barinov #include <asm/arch/sh_sdhi.h> 27*21871138SVladimir Barinov #include <miiphy.h> 28*21871138SVladimir Barinov #include <i2c.h> 29*21871138SVladimir Barinov #include <mmc.h> 30*21871138SVladimir Barinov #include "qos.h" 31*21871138SVladimir Barinov #include "cpld.h" 32*21871138SVladimir Barinov 33*21871138SVladimir Barinov DECLARE_GLOBAL_DATA_PTR; 34*21871138SVladimir Barinov 35*21871138SVladimir Barinov #define CLK2MHZ(clk) (clk / 1000 / 1000) 36*21871138SVladimir Barinov void s_init(void) 37*21871138SVladimir Barinov { 38*21871138SVladimir Barinov struct rcar_rwdt *rwdt = (struct rcar_rwdt *)RWDT_BASE; 39*21871138SVladimir Barinov struct rcar_swdt *swdt = (struct rcar_swdt *)SWDT_BASE; 40*21871138SVladimir Barinov 41*21871138SVladimir Barinov /* Watchdog init */ 42*21871138SVladimir Barinov writel(0xA5A5A500, &rwdt->rwtcsra); 43*21871138SVladimir Barinov writel(0xA5A5A500, &swdt->swtcsra); 44*21871138SVladimir Barinov 45*21871138SVladimir Barinov /* CPU frequency setting. Set to 1.4GHz */ 46*21871138SVladimir Barinov if (rmobile_get_cpu_rev_integer() >= R8A7790_CUT_ES2X) { 47*21871138SVladimir Barinov u32 stat = 0; 48*21871138SVladimir Barinov u32 stc = ((1400 / CLK2MHZ(CONFIG_SYS_CLK_FREQ)) - 1) 49*21871138SVladimir Barinov << PLL0_STC_BIT; 50*21871138SVladimir Barinov clrsetbits_le32(PLL0CR, PLL0_STC_MASK, stc); 51*21871138SVladimir Barinov 52*21871138SVladimir Barinov do { 53*21871138SVladimir Barinov stat = readl(PLLECR) & PLL0ST; 54*21871138SVladimir Barinov } while (stat == 0x0); 55*21871138SVladimir Barinov } 56*21871138SVladimir Barinov 57*21871138SVladimir Barinov /* QoS(Quality-of-Service) Init */ 58*21871138SVladimir Barinov qos_init(); 59*21871138SVladimir Barinov } 60*21871138SVladimir Barinov 61*21871138SVladimir Barinov #define TMU0_MSTP125 (1 << 25) 62*21871138SVladimir Barinov #define SCIFA0_MSTP204 (1 << 4) 63*21871138SVladimir Barinov #define SDHI0_MSTP314 (1 << 14) 64*21871138SVladimir Barinov #define SDHI2_MSTP312 (1 << 12) 65*21871138SVladimir Barinov #define ETHER_MSTP813 (1 << 13) 66*21871138SVladimir Barinov 67*21871138SVladimir Barinov #define MSTPSR3 0xE6150048 68*21871138SVladimir Barinov #define SMSTPCR3 0xE615013C 69*21871138SVladimir Barinov 70*21871138SVladimir Barinov #define SD2CKCR 0xE6150078 71*21871138SVladimir Barinov #define SD2_97500KHZ 0x7 72*21871138SVladimir Barinov 73*21871138SVladimir Barinov int board_early_init_f(void) 74*21871138SVladimir Barinov { 75*21871138SVladimir Barinov /* TMU0 */ 76*21871138SVladimir Barinov mstp_clrbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125); 77*21871138SVladimir Barinov /* SCIFA0 */ 78*21871138SVladimir Barinov mstp_clrbits_le32(MSTPSR2, SMSTPCR2, SCIFA0_MSTP204); 79*21871138SVladimir Barinov /* ETHER */ 80*21871138SVladimir Barinov mstp_clrbits_le32(MSTPSR8, SMSTPCR8, ETHER_MSTP813); 81*21871138SVladimir Barinov /* SDHI0,2 */ 82*21871138SVladimir Barinov mstp_clrbits_le32(MSTPSR3, SMSTPCR3, SDHI0_MSTP314 | SDHI2_MSTP312); 83*21871138SVladimir Barinov 84*21871138SVladimir Barinov /* 85*21871138SVladimir Barinov * SD0 clock is set to 97.5MHz by default. 86*21871138SVladimir Barinov * Set SD2 to the 97.5MHz as well. 87*21871138SVladimir Barinov */ 88*21871138SVladimir Barinov writel(SD2_97500KHZ, SD2CKCR); 89*21871138SVladimir Barinov 90*21871138SVladimir Barinov return 0; 91*21871138SVladimir Barinov } 92*21871138SVladimir Barinov 93*21871138SVladimir Barinov int board_init(void) 94*21871138SVladimir Barinov { 95*21871138SVladimir Barinov /* adress of boot parameters */ 96*21871138SVladimir Barinov gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; 97*21871138SVladimir Barinov 98*21871138SVladimir Barinov /* Init PFC controller */ 99*21871138SVladimir Barinov r8a7790_pinmux_init(); 100*21871138SVladimir Barinov 101*21871138SVladimir Barinov cpld_init(); 102*21871138SVladimir Barinov 103*21871138SVladimir Barinov #ifdef CONFIG_SH_ETHER 104*21871138SVladimir Barinov /* ETHER Enable */ 105*21871138SVladimir Barinov gpio_request(GPIO_FN_ETH_CRS_DV, NULL); 106*21871138SVladimir Barinov gpio_request(GPIO_FN_ETH_RX_ER, NULL); 107*21871138SVladimir Barinov gpio_request(GPIO_FN_ETH_RXD0, NULL); 108*21871138SVladimir Barinov gpio_request(GPIO_FN_ETH_RXD1, NULL); 109*21871138SVladimir Barinov gpio_request(GPIO_FN_ETH_LINK, NULL); 110*21871138SVladimir Barinov gpio_request(GPIO_FN_ETH_REF_CLK, NULL); 111*21871138SVladimir Barinov gpio_request(GPIO_FN_ETH_MDIO, NULL); 112*21871138SVladimir Barinov gpio_request(GPIO_FN_ETH_TXD1, NULL); 113*21871138SVladimir Barinov gpio_request(GPIO_FN_ETH_TX_EN, NULL); 114*21871138SVladimir Barinov gpio_request(GPIO_FN_ETH_MAGIC, NULL); 115*21871138SVladimir Barinov gpio_request(GPIO_FN_ETH_TXD0, NULL); 116*21871138SVladimir Barinov gpio_request(GPIO_FN_ETH_MDC, NULL); 117*21871138SVladimir Barinov gpio_request(GPIO_FN_IRQ1, NULL); 118*21871138SVladimir Barinov 119*21871138SVladimir Barinov gpio_request(GPIO_GP_3_31, NULL); /* PHY_RST */ 120*21871138SVladimir Barinov gpio_direction_output(GPIO_GP_3_31, 0); 121*21871138SVladimir Barinov mdelay(20); 122*21871138SVladimir Barinov gpio_set_value(GPIO_GP_3_31, 1); 123*21871138SVladimir Barinov udelay(1); 124*21871138SVladimir Barinov #endif 125*21871138SVladimir Barinov 126*21871138SVladimir Barinov return 0; 127*21871138SVladimir Barinov } 128*21871138SVladimir Barinov 129*21871138SVladimir Barinov #define CXR24 0xEE7003C0 /* MAC address high register */ 130*21871138SVladimir Barinov #define CXR25 0xEE7003C8 /* MAC address low register */ 131*21871138SVladimir Barinov int board_eth_init(bd_t *bis) 132*21871138SVladimir Barinov { 133*21871138SVladimir Barinov int ret = -ENODEV; 134*21871138SVladimir Barinov 135*21871138SVladimir Barinov #ifdef CONFIG_SH_ETHER 136*21871138SVladimir Barinov u32 val; 137*21871138SVladimir Barinov unsigned char enetaddr[6]; 138*21871138SVladimir Barinov 139*21871138SVladimir Barinov ret = sh_eth_initialize(bis); 140*21871138SVladimir Barinov if (!eth_getenv_enetaddr("ethaddr", enetaddr)) 141*21871138SVladimir Barinov return ret; 142*21871138SVladimir Barinov 143*21871138SVladimir Barinov /* Set Mac address */ 144*21871138SVladimir Barinov val = enetaddr[0] << 24 | enetaddr[1] << 16 | 145*21871138SVladimir Barinov enetaddr[2] << 8 | enetaddr[3]; 146*21871138SVladimir Barinov writel(val, CXR24); 147*21871138SVladimir Barinov 148*21871138SVladimir Barinov val = enetaddr[4] << 8 | enetaddr[5]; 149*21871138SVladimir Barinov writel(val, CXR25); 150*21871138SVladimir Barinov #endif 151*21871138SVladimir Barinov 152*21871138SVladimir Barinov return ret; 153*21871138SVladimir Barinov } 154*21871138SVladimir Barinov 155*21871138SVladimir Barinov /* Stout has KSZ8041NL/RNL */ 156*21871138SVladimir Barinov #define PHY_CONTROL1 0x1E 157*21871138SVladimir Barinov #define PHY_LED_MODE 0xC0000 158*21871138SVladimir Barinov #define PHY_LED_MODE_ACK 0x4000 159*21871138SVladimir Barinov int board_phy_config(struct phy_device *phydev) 160*21871138SVladimir Barinov { 161*21871138SVladimir Barinov int ret = phy_read(phydev, MDIO_DEVAD_NONE, PHY_CONTROL1); 162*21871138SVladimir Barinov ret &= ~PHY_LED_MODE; 163*21871138SVladimir Barinov ret |= PHY_LED_MODE_ACK; 164*21871138SVladimir Barinov ret = phy_write(phydev, MDIO_DEVAD_NONE, PHY_CONTROL1, (u16)ret); 165*21871138SVladimir Barinov 166*21871138SVladimir Barinov return 0; 167*21871138SVladimir Barinov } 168*21871138SVladimir Barinov 169*21871138SVladimir Barinov int board_mmc_init(bd_t *bis) 170*21871138SVladimir Barinov { 171*21871138SVladimir Barinov int ret = -ENODEV; 172*21871138SVladimir Barinov 173*21871138SVladimir Barinov #ifdef CONFIG_SH_SDHI 174*21871138SVladimir Barinov gpio_request(GPIO_FN_SD0_DAT0, NULL); 175*21871138SVladimir Barinov gpio_request(GPIO_FN_SD0_DAT1, NULL); 176*21871138SVladimir Barinov gpio_request(GPIO_FN_SD0_DAT2, NULL); 177*21871138SVladimir Barinov gpio_request(GPIO_FN_SD0_DAT3, NULL); 178*21871138SVladimir Barinov gpio_request(GPIO_FN_SD0_CLK, NULL); 179*21871138SVladimir Barinov gpio_request(GPIO_FN_SD0_CMD, NULL); 180*21871138SVladimir Barinov gpio_request(GPIO_FN_SD0_CD, NULL); 181*21871138SVladimir Barinov gpio_request(GPIO_FN_SD2_DAT0, NULL); 182*21871138SVladimir Barinov gpio_request(GPIO_FN_SD2_DAT1, NULL); 183*21871138SVladimir Barinov gpio_request(GPIO_FN_SD2_DAT2, NULL); 184*21871138SVladimir Barinov gpio_request(GPIO_FN_SD2_DAT3, NULL); 185*21871138SVladimir Barinov gpio_request(GPIO_FN_SD2_CLK, NULL); 186*21871138SVladimir Barinov gpio_request(GPIO_FN_SD2_CMD, NULL); 187*21871138SVladimir Barinov gpio_request(GPIO_FN_SD2_CD, NULL); 188*21871138SVladimir Barinov 189*21871138SVladimir Barinov /* SDHI0 - needs CPLD mux setup */ 190*21871138SVladimir Barinov gpio_request(GPIO_GP_3_30, NULL); 191*21871138SVladimir Barinov gpio_direction_output(GPIO_GP_3_30, 1); /* VLDO3=3.3V */ 192*21871138SVladimir Barinov gpio_request(GPIO_GP_5_24, NULL); 193*21871138SVladimir Barinov gpio_direction_output(GPIO_GP_5_24, 1); /* power on */ 194*21871138SVladimir Barinov 195*21871138SVladimir Barinov ret = sh_sdhi_init(CONFIG_SYS_SH_SDHI0_BASE, 0, 196*21871138SVladimir Barinov SH_SDHI_QUIRK_16BIT_BUF); 197*21871138SVladimir Barinov if (ret) 198*21871138SVladimir Barinov return ret; 199*21871138SVladimir Barinov 200*21871138SVladimir Barinov /* SDHI2 - needs CPLD mux setup */ 201*21871138SVladimir Barinov gpio_request(GPIO_GP_3_29, NULL); 202*21871138SVladimir Barinov gpio_direction_output(GPIO_GP_3_29, 1); /* VLDO4=3.3V */ 203*21871138SVladimir Barinov gpio_request(GPIO_GP_5_25, NULL); 204*21871138SVladimir Barinov gpio_direction_output(GPIO_GP_5_25, 1); /* power on */ 205*21871138SVladimir Barinov 206*21871138SVladimir Barinov ret = sh_sdhi_init(CONFIG_SYS_SH_SDHI2_BASE, 2, 0); 207*21871138SVladimir Barinov #endif 208*21871138SVladimir Barinov return ret; 209*21871138SVladimir Barinov } 210*21871138SVladimir Barinov 211*21871138SVladimir Barinov 212*21871138SVladimir Barinov int dram_init(void) 213*21871138SVladimir Barinov { 214*21871138SVladimir Barinov gd->ram_size = CONFIG_SYS_SDRAM_SIZE; 215*21871138SVladimir Barinov 216*21871138SVladimir Barinov return 0; 217*21871138SVladimir Barinov } 218*21871138SVladimir Barinov 219*21871138SVladimir Barinov const struct rmobile_sysinfo sysinfo = { 220*21871138SVladimir Barinov CONFIG_RMOBILE_BOARD_STRING 221*21871138SVladimir Barinov }; 222*21871138SVladimir Barinov 223*21871138SVladimir Barinov static const struct sh_serial_platdata serial_platdata = { 224*21871138SVladimir Barinov .base = SCIFA0_BASE, 225*21871138SVladimir Barinov .type = PORT_SCIFA, 226*21871138SVladimir Barinov .clk = CONFIG_MP_CLK_FREQ, 227*21871138SVladimir Barinov }; 228*21871138SVladimir Barinov 229*21871138SVladimir Barinov U_BOOT_DEVICE(stout_serials) = { 230*21871138SVladimir Barinov .name = "serial_sh", 231*21871138SVladimir Barinov .platdata = &serial_platdata, 232*21871138SVladimir Barinov }; 233