1 /* 2 * board/renesas/silk/silk_spl.c 3 * 4 * Copyright (C) 2018 Marek Vasut <marek.vasut@gmail.com> 5 * 6 * SPDX-License-Identifier: GPL-2.0 7 */ 8 9 #include <common.h> 10 #include <malloc.h> 11 #include <dm/platform_data/serial_sh.h> 12 #include <asm/processor.h> 13 #include <asm/mach-types.h> 14 #include <asm/io.h> 15 #include <linux/errno.h> 16 #include <asm/arch/sys_proto.h> 17 #include <asm/gpio.h> 18 #include <asm/arch/rmobile.h> 19 #include <asm/arch/rcar-mstp.h> 20 21 #include <spl.h> 22 23 #define TMU0_MSTP125 BIT(25) 24 #define SCIF2_MSTP719 BIT(19) 25 #define QSPI_MSTP917 BIT(17) 26 27 #define SD1CKCR 0xE6150078 28 #define SD_97500KHZ 0x7 29 30 struct reg_config { 31 u16 off; 32 u32 val; 33 }; 34 35 static void dbsc_wait(u16 reg) 36 { 37 static const u32 dbsc3_0_base = DBSC3_0_BASE; 38 39 while (!(readl(dbsc3_0_base + reg) & BIT(0))) 40 ; 41 } 42 43 static void spl_init_sys(void) 44 { 45 u32 r0 = 0; 46 47 writel(0xa5a5a500, 0xe6020004); 48 writel(0xa5a5a500, 0xe6030004); 49 50 asm volatile( 51 /* ICIALLU - Invalidate I$ to PoU */ 52 "mcr 15, 0, %0, cr7, cr5, 0 \n" 53 /* BPIALL - Invalidate branch predictors */ 54 "mcr 15, 0, %0, cr7, cr5, 6 \n" 55 /* Set SCTLR[IZ] */ 56 "mrc 15, 0, %0, cr1, cr0, 0 \n" 57 "orr %0, #0x1800 \n" 58 "mcr 15, 0, %0, cr1, cr0, 0 \n" 59 "isb sy \n" 60 :"=r"(r0)); 61 } 62 63 static void spl_init_pfc(void) 64 { 65 static const struct reg_config pfc_with_unlock[] = { 66 { 0x0090, 0x00018040 }, 67 { 0x0094, 0x00000000 }, 68 { 0x0098, 0x00000000 }, 69 { 0x0020, 0x94000000 }, 70 { 0x0024, 0x00000006 }, 71 { 0x0028, 0x40000000 }, 72 { 0x002c, 0x00000155 }, 73 { 0x0030, 0x00000002 }, 74 { 0x0034, 0x00000000 }, 75 { 0x0038, 0x00000000 }, 76 { 0x003c, 0x00000000 }, 77 { 0x0040, 0x60000000 }, 78 { 0x0044, 0x36dab6db }, 79 { 0x0048, 0x926da012 }, 80 { 0x004c, 0x0008c383 }, 81 { 0x0050, 0x00000000 }, 82 { 0x0054, 0x00000140 }, 83 { 0x0004, 0xffffffff }, 84 { 0x0008, 0x00ec3fff }, 85 { 0x000c, 0x5bffffff }, 86 { 0x0010, 0x01bfe1ff }, 87 { 0x0014, 0x5bffffff }, 88 { 0x0018, 0x0f4b200f }, 89 { 0x001c, 0x03ffffff }, 90 }; 91 92 static const struct reg_config pfc_without_unlock[] = { 93 { 0x0100, 0x00000000 }, 94 { 0x0104, 0x4203fdf0 }, 95 { 0x0108, 0x00000000 }, 96 { 0x010c, 0x159007ff }, 97 { 0x0110, 0x80000000 }, 98 { 0x0114, 0x00de481f }, 99 { 0x0118, 0x00000000 }, 100 }; 101 102 static const struct reg_config pfc_with_unlock2[] = { 103 { 0x0060, 0xffffffff }, 104 { 0x0064, 0xfffff000 }, 105 { 0x0068, 0x55555500 }, 106 { 0x006c, 0xffffff00 }, 107 { 0x0070, 0x00000000 }, 108 }; 109 110 static const u32 pfc_base = 0xe6060000; 111 112 unsigned int i; 113 114 for (i = 0; i < ARRAY_SIZE(pfc_with_unlock); i++) { 115 writel(~pfc_with_unlock[i].val, pfc_base); 116 writel(pfc_with_unlock[i].val, 117 pfc_base | pfc_with_unlock[i].off); 118 } 119 120 for (i = 0; i < ARRAY_SIZE(pfc_without_unlock); i++) 121 writel(pfc_without_unlock[i].val, 122 pfc_base | pfc_without_unlock[i].off); 123 124 for (i = 0; i < ARRAY_SIZE(pfc_with_unlock2); i++) { 125 writel(~pfc_with_unlock2[i].val, pfc_base); 126 writel(pfc_with_unlock2[i].val, 127 pfc_base | pfc_with_unlock2[i].off); 128 } 129 } 130 131 static void spl_init_gpio(void) 132 { 133 static const u16 gpio_offs[] = { 134 0x1000, 0x2000, 0x3000, 0x4000 135 }; 136 137 static const struct reg_config gpio_set[] = { 138 { 0x2000, 0x24000000 }, 139 { 0x4000, 0xa4000000 }, 140 { 0x5000, 0x0084c000 }, 141 }; 142 143 static const struct reg_config gpio_clr[] = { 144 { 0x1000, 0x01000000 }, 145 { 0x2000, 0x24000000 }, 146 { 0x3000, 0x00000000 }, 147 { 0x4000, 0xa4000000 }, 148 { 0x5000, 0x00044380 }, 149 }; 150 151 static const u32 gpio_base = 0xe6050000; 152 153 unsigned int i; 154 155 for (i = 0; i < ARRAY_SIZE(gpio_offs); i++) 156 writel(0, gpio_base | 0x20 | gpio_offs[i]); 157 writel(BIT(23), gpio_base | 0x5020); 158 159 for (i = 0; i < ARRAY_SIZE(gpio_offs); i++) 160 writel(0, gpio_base | 0x00 | gpio_offs[i]); 161 writel(BIT(23), gpio_base | 0x5000); 162 163 for (i = 0; i < ARRAY_SIZE(gpio_set); i++) 164 writel(gpio_set[i].val, gpio_base | 0x08 | gpio_set[i].off); 165 166 for (i = 0; i < ARRAY_SIZE(gpio_clr); i++) 167 writel(gpio_clr[i].val, gpio_base | 0x04 | gpio_clr[i].off); 168 } 169 170 static void spl_init_lbsc(void) 171 { 172 static const struct reg_config lbsc_config[] = { 173 { 0x00, 0x00000020 }, 174 { 0x08, 0x00002020 }, 175 { 0x30, 0x2a103320 }, 176 { 0x38, 0xff70ff70 }, 177 }; 178 179 static const u16 lbsc_offs[] = { 180 0x80, 0x84, 0x88, 0x8c, 0xa0, 0xc0, 0xc4, 0xc8 181 }; 182 183 static const u32 lbsc_base = 0xfec00200; 184 185 unsigned int i; 186 187 for (i = 0; i < ARRAY_SIZE(lbsc_config); i++) { 188 writel(lbsc_config[i].val, 189 lbsc_base | lbsc_config[i].off); 190 writel(lbsc_config[i].val, 191 lbsc_base | (lbsc_config[i].off + 4)); 192 } 193 194 for (i = 0; i < ARRAY_SIZE(lbsc_offs); i++) 195 writel(0, lbsc_base | lbsc_offs[i]); 196 } 197 198 static void spl_init_dbsc(void) 199 { 200 static const struct reg_config dbsc_config1[] = { 201 { 0x0018, 0x21000000 }, 202 { 0x0018, 0x11000000 }, 203 { 0x0018, 0x10000000 }, 204 { 0x0280, 0x0000a55a }, 205 { 0x0290, 0x00000001 }, 206 { 0x02a0, 0x80000000 }, 207 { 0x0290, 0x00000004 }, 208 }; 209 210 static const struct reg_config dbsc_config2[] = { 211 { 0x0290, 0x00000006 }, 212 { 0x02a0, 0x0005c000 }, 213 }; 214 215 static const struct reg_config dbsc_config3r2[] = { 216 { 0x0290, 0x0000000f }, 217 { 0x02a0, 0x00181224 }, 218 }; 219 220 static const struct reg_config dbsc_config4[] = { 221 { 0x0290, 0x00000010 }, 222 { 0x02a0, 0xf004649b }, 223 { 0x0290, 0x00000061 }, 224 { 0x02a0, 0x0000006d }, 225 { 0x0290, 0x00000001 }, 226 { 0x02a0, 0x00000073 }, 227 { 0x0020, 0x00000007 }, 228 { 0x0024, 0x0f030a02 }, 229 { 0x0030, 0x00000001 }, 230 { 0x00b0, 0x00000000 }, 231 { 0x0040, 0x00000009 }, 232 { 0x0044, 0x00000007 }, 233 { 0x0048, 0x00000000 }, 234 { 0x0050, 0x00000009 }, 235 { 0x0054, 0x000a0009 }, 236 { 0x0058, 0x00000021 }, 237 { 0x005c, 0x00000018 }, 238 { 0x0060, 0x00000005 }, 239 { 0x0064, 0x00000020 }, 240 { 0x0068, 0x00000007 }, 241 { 0x006c, 0x0000000a }, 242 { 0x0070, 0x00000009 }, 243 { 0x0074, 0x00000010 }, 244 { 0x0078, 0x000000ae }, 245 { 0x007c, 0x00140005 }, 246 { 0x0080, 0x00050004 }, 247 { 0x0084, 0x50213005 }, 248 { 0x0088, 0x000c0000 }, 249 { 0x008c, 0x00000200 }, 250 { 0x0090, 0x00000040 }, 251 { 0x0100, 0x00000001 }, 252 { 0x00c0, 0x00020001 }, 253 { 0x00c8, 0x20042004 }, 254 { 0x0380, 0x00020003 }, 255 { 0x0390, 0x0000001f }, 256 }; 257 258 static const struct reg_config dbsc_config5[] = { 259 { 0x0244, 0x00000011 }, 260 { 0x0290, 0x00000003 }, 261 { 0x02a0, 0x0300c4e1 }, 262 { 0x0290, 0x00000023 }, 263 { 0x02a0, 0x00fcb6d0 }, 264 { 0x0290, 0x00000011 }, 265 { 0x02a0, 0x1000040b }, 266 { 0x0290, 0x00000012 }, 267 { 0x02a0, 0x85589955 }, 268 { 0x0290, 0x00000013 }, 269 { 0x02a0, 0x1a852400 }, 270 { 0x0290, 0x00000014 }, 271 { 0x02a0, 0x300210b4 }, 272 { 0x0290, 0x00000015 }, 273 { 0x02a0, 0x00000b50 }, 274 { 0x0290, 0x00000016 }, 275 { 0x02a0, 0x00000006 }, 276 { 0x0290, 0x00000017 }, 277 { 0x02a0, 0x00000010 }, 278 { 0x0290, 0x0000001a }, 279 { 0x02a0, 0x910035c7 }, 280 { 0x0290, 0x00000004 }, 281 }; 282 283 static const struct reg_config dbsc_config6[] = { 284 { 0x0290, 0x00000001 }, 285 { 0x02a0, 0x00000181 }, 286 { 0x0018, 0x11000000 }, 287 { 0x0290, 0x00000004 }, 288 }; 289 290 static const struct reg_config dbsc_config7[] = { 291 { 0x0290, 0x00000001 }, 292 { 0x02a0, 0x0000fe01 }, 293 { 0x0304, 0x00000000 }, 294 { 0x00f4, 0x01004c20 }, 295 { 0x00f8, 0x012c00be }, 296 { 0x00e0, 0x00000140 }, 297 { 0x00e4, 0x00081450 }, 298 { 0x00e8, 0x00010000 }, 299 { 0x0290, 0x00000004 }, 300 }; 301 302 static const struct reg_config dbsc_config8[] = { 303 { 0x0014, 0x00000001 }, 304 { 0x0290, 0x00000010 }, 305 { 0x02a0, 0xf00464db }, 306 { 0x0010, 0x00000001 }, 307 { 0x0280, 0x00000000 }, 308 }; 309 310 static const u32 dbsc3_0_base = DBSC3_0_BASE; 311 unsigned int i; 312 313 for (i = 0; i < ARRAY_SIZE(dbsc_config1); i++) 314 writel(dbsc_config1[i].val, dbsc3_0_base | dbsc_config1[i].off); 315 316 dbsc_wait(0x2a0); 317 318 for (i = 0; i < ARRAY_SIZE(dbsc_config2); i++) 319 writel(dbsc_config2[i].val, dbsc3_0_base | dbsc_config2[i].off); 320 321 for (i = 0; i < ARRAY_SIZE(dbsc_config3r2); i++) { 322 writel(dbsc_config3r2[i].val, 323 dbsc3_0_base | dbsc_config3r2[i].off); 324 } 325 326 for (i = 0; i < ARRAY_SIZE(dbsc_config4); i++) 327 writel(dbsc_config4[i].val, dbsc3_0_base | dbsc_config4[i].off); 328 329 dbsc_wait(0x240); 330 331 for (i = 0; i < ARRAY_SIZE(dbsc_config5); i++) 332 writel(dbsc_config5[i].val, dbsc3_0_base | dbsc_config5[i].off); 333 334 dbsc_wait(0x2a0); 335 336 for (i = 0; i < ARRAY_SIZE(dbsc_config6); i++) 337 writel(dbsc_config6[i].val, dbsc3_0_base | dbsc_config6[i].off); 338 339 dbsc_wait(0x2a0); 340 341 for (i = 0; i < ARRAY_SIZE(dbsc_config7); i++) 342 writel(dbsc_config7[i].val, dbsc3_0_base | dbsc_config7[i].off); 343 344 dbsc_wait(0x2a0); 345 346 for (i = 0; i < ARRAY_SIZE(dbsc_config8); i++) 347 writel(dbsc_config8[i].val, dbsc3_0_base | dbsc_config8[i].off); 348 349 } 350 351 static void spl_init_qspi(void) 352 { 353 mstp_clrbits_le32(MSTPSR9, SMSTPCR9, QSPI_MSTP917); 354 355 static const u32 qspi_base = 0xe6b10000; 356 357 writeb(0x08, qspi_base + 0x00); 358 writeb(0x00, qspi_base + 0x01); 359 writeb(0x06, qspi_base + 0x02); 360 writeb(0x01, qspi_base + 0x0a); 361 writeb(0x00, qspi_base + 0x0b); 362 writeb(0x00, qspi_base + 0x0c); 363 writeb(0x00, qspi_base + 0x0d); 364 writeb(0x00, qspi_base + 0x0e); 365 366 writew(0xe080, qspi_base + 0x10); 367 368 writeb(0xc0, qspi_base + 0x18); 369 writeb(0x00, qspi_base + 0x18); 370 writeb(0x00, qspi_base + 0x08); 371 writeb(0x48, qspi_base + 0x00); 372 } 373 374 void board_init_f(ulong dummy) 375 { 376 mstp_clrbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125); 377 mstp_clrbits_le32(MSTPSR7, SMSTPCR7, SCIF2_MSTP719); 378 379 /* Set SD1 to the 97.5MHz */ 380 writel(SD_97500KHZ, SD1CKCR); 381 382 spl_init_sys(); 383 spl_init_pfc(); 384 spl_init_gpio(); 385 spl_init_lbsc(); 386 spl_init_dbsc(); 387 spl_init_qspi(); 388 } 389 390 void spl_board_init(void) 391 { 392 /* UART clocks enabled and gd valid - init serial console */ 393 preloader_console_init(); 394 } 395 396 void board_boot_order(u32 *spl_boot_list) 397 { 398 const u32 jtag_magic = 0x1337c0de; 399 const u32 load_magic = 0xb33fc0de; 400 401 /* 402 * If JTAG probe sets special word at 0xe6300020, then it must 403 * put U-Boot into RAM and SPL will start it from RAM. 404 */ 405 if (readl(CONFIG_SPL_TEXT_BASE + 0x20) == jtag_magic) { 406 printf("JTAG boot detected!\n"); 407 408 while (readl(CONFIG_SPL_TEXT_BASE + 0x24) != load_magic) 409 ; 410 411 spl_boot_list[0] = BOOT_DEVICE_RAM; 412 spl_boot_list[1] = BOOT_DEVICE_NONE; 413 414 return; 415 } 416 417 /* Boot from SPI NOR with YMODEM UART fallback. */ 418 spl_boot_list[0] = BOOT_DEVICE_SPI; 419 spl_boot_list[1] = BOOT_DEVICE_UART; 420 spl_boot_list[2] = BOOT_DEVICE_NONE; 421 } 422 423 void reset_cpu(ulong addr) 424 { 425 } 426