1 /* 2 * board/renesas/silk/silk.c 3 * 4 * Copyright (C) 2015 Renesas Electronics Corporation 5 * Copyright (C) 2015 Cogent Embedded, Inc. 6 * 7 * SPDX-License-Identifier: GPL-2.0 8 */ 9 10 #include <common.h> 11 #include <malloc.h> 12 #include <asm/processor.h> 13 #include <asm/mach-types.h> 14 #include <asm/io.h> 15 #include <asm/errno.h> 16 #include <asm/arch/sys_proto.h> 17 #include <asm/gpio.h> 18 #include <asm/arch/rmobile.h> 19 #include <asm/arch/rcar-mstp.h> 20 #include <asm/arch/mmc.h> 21 #include <netdev.h> 22 #include <miiphy.h> 23 #include <i2c.h> 24 #include <div64.h> 25 #include "qos.h" 26 27 DECLARE_GLOBAL_DATA_PTR; 28 29 #define CLK2MHZ(clk) (clk / 1000 / 1000) 30 void s_init(void) 31 { 32 struct rcar_rwdt *rwdt = (struct rcar_rwdt *)RWDT_BASE; 33 struct rcar_swdt *swdt = (struct rcar_swdt *)SWDT_BASE; 34 35 /* Watchdog init */ 36 writel(0xA5A5A500, &rwdt->rwtcsra); 37 writel(0xA5A5A500, &swdt->swtcsra); 38 39 /* QoS */ 40 qos_init(); 41 } 42 43 #define TMU0_MSTP125 (1 << 25) 44 #define SCIF2_MSTP719 (1 << 19) 45 #define ETHER_MSTP813 (1 << 13) 46 #define IIC1_MSTP323 (1 << 23) 47 #define MMC0_MSTP315 (1 << 15) 48 49 int board_early_init_f(void) 50 { 51 /* TMU */ 52 mstp_clrbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125); 53 54 /* SCIF2 */ 55 mstp_clrbits_le32(MSTPSR7, SMSTPCR7, SCIF2_MSTP719); 56 57 /* ETHER */ 58 mstp_clrbits_le32(MSTPSR8, SMSTPCR8, ETHER_MSTP813); 59 60 /* IIC1 / sh-i2c ch1 */ 61 mstp_clrbits_le32(MSTPSR3, SMSTPCR3, IIC1_MSTP323); 62 63 #ifdef CONFIG_SH_MMCIF 64 /* MMC */ 65 mstp_clrbits_le32(MSTPSR3, SMSTPCR3, MMC0_MSTP315); 66 #endif 67 return 0; 68 } 69 70 int board_init(void) 71 { 72 /* adress of boot parameters */ 73 gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; 74 75 /* Init PFC controller */ 76 r8a7794_pinmux_init(); 77 78 /* Ether Enable */ 79 gpio_request(GPIO_FN_ETH_CRS_DV, NULL); 80 gpio_request(GPIO_FN_ETH_RX_ER, NULL); 81 gpio_request(GPIO_FN_ETH_RXD0, NULL); 82 gpio_request(GPIO_FN_ETH_RXD1, NULL); 83 gpio_request(GPIO_FN_ETH_LINK, NULL); 84 gpio_request(GPIO_FN_ETH_REFCLK, NULL); 85 gpio_request(GPIO_FN_ETH_MDIO, NULL); 86 gpio_request(GPIO_FN_ETH_TXD1, NULL); 87 gpio_request(GPIO_FN_ETH_TX_EN, NULL); 88 gpio_request(GPIO_FN_ETH_MAGIC, NULL); 89 gpio_request(GPIO_FN_ETH_TXD0, NULL); 90 gpio_request(GPIO_FN_ETH_MDC, NULL); 91 gpio_request(GPIO_FN_IRQ8, NULL); 92 93 /* PHY reset */ 94 gpio_request(GPIO_GP_1_24, NULL); 95 gpio_direction_output(GPIO_GP_1_24, 0); 96 mdelay(20); 97 gpio_set_value(GPIO_GP_1_24, 1); 98 udelay(1); 99 100 return 0; 101 } 102 103 #define CXR24 0xEE7003C0 /* MAC address high register */ 104 #define CXR25 0xEE7003C8 /* MAC address low register */ 105 int board_eth_init(bd_t *bis) 106 { 107 #ifdef CONFIG_SH_ETHER 108 int ret = -ENODEV; 109 u32 val; 110 unsigned char enetaddr[6]; 111 112 ret = sh_eth_initialize(bis); 113 if (!eth_getenv_enetaddr("ethaddr", enetaddr)) 114 return ret; 115 116 /* Set Mac address */ 117 val = enetaddr[0] << 24 | enetaddr[1] << 16 | 118 enetaddr[2] << 8 | enetaddr[3]; 119 writel(val, CXR24); 120 121 val = enetaddr[4] << 8 | enetaddr[5]; 122 writel(val, CXR25); 123 124 return ret; 125 #else 126 return 0; 127 #endif 128 } 129 130 int board_mmc_init(bd_t *bis) 131 { 132 int ret = 0; 133 134 #ifdef CONFIG_SH_MMCIF 135 /* MMC0 */ 136 gpio_request(GPIO_GP_4_31, NULL); 137 gpio_set_value(GPIO_GP_4_31, 1); 138 139 ret = mmcif_mmc_init(); 140 #endif 141 return ret; 142 } 143 144 int dram_init(void) 145 { 146 gd->ram_size = CONFIG_SYS_SDRAM_SIZE; 147 148 return 0; 149 } 150 151 const struct rmobile_sysinfo sysinfo = { 152 CONFIG_RMOBILE_BOARD_STRING 153 }; 154 155 void reset_cpu(ulong addr) 156 { 157 u8 val; 158 159 i2c_set_bus_num(1); /* PowerIC connected to ch1 */ 160 i2c_read(CONFIG_SYS_I2C_POWERIC_ADDR, 0x13, 1, &val, 1); 161 val |= 0x02; 162 i2c_write(CONFIG_SYS_I2C_POWERIC_ADDR, 0x13, 1, &val, 1); 163 } 164