1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * board/renesas/silk/silk.c 4 * 5 * Copyright (C) 2015 Renesas Electronics Corporation 6 * Copyright (C) 2015 Cogent Embedded, Inc. 7 */ 8 9 #include <common.h> 10 #include <malloc.h> 11 #include <dm.h> 12 #include <dm/platform_data/serial_sh.h> 13 #include <environment.h> 14 #include <asm/processor.h> 15 #include <asm/mach-types.h> 16 #include <asm/io.h> 17 #include <linux/errno.h> 18 #include <asm/arch/sys_proto.h> 19 #include <asm/gpio.h> 20 #include <asm/arch/rmobile.h> 21 #include <asm/arch/rcar-mstp.h> 22 #include <asm/arch/mmc.h> 23 #include <asm/arch/sh_sdhi.h> 24 #include <netdev.h> 25 #include <miiphy.h> 26 #include <i2c.h> 27 #include <div64.h> 28 #include "qos.h" 29 30 DECLARE_GLOBAL_DATA_PTR; 31 32 void s_init(void) 33 { 34 struct rcar_rwdt *rwdt = (struct rcar_rwdt *)RWDT_BASE; 35 struct rcar_swdt *swdt = (struct rcar_swdt *)SWDT_BASE; 36 37 /* Watchdog init */ 38 writel(0xA5A5A500, &rwdt->rwtcsra); 39 writel(0xA5A5A500, &swdt->swtcsra); 40 41 /* QoS */ 42 qos_init(); 43 } 44 45 #define TMU0_MSTP125 BIT(25) 46 #define MMC0_MSTP315 BIT(15) 47 48 #define SD1CKCR 0xE6150078 49 #define SD_97500KHZ 0x7 50 51 int board_early_init_f(void) 52 { 53 /* TMU */ 54 mstp_clrbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125); 55 56 /* Set SD1 to the 97.5MHz */ 57 writel(SD_97500KHZ, SD1CKCR); 58 59 return 0; 60 } 61 62 #define ETHERNET_PHY_RESET 56 /* GPIO 1 24 */ 63 64 int board_init(void) 65 { 66 /* adress of boot parameters */ 67 gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; 68 69 /* Force ethernet PHY out of reset */ 70 gpio_request(ETHERNET_PHY_RESET, "phy_reset"); 71 gpio_direction_output(ETHERNET_PHY_RESET, 0); 72 mdelay(20); 73 gpio_direction_output(ETHERNET_PHY_RESET, 1); 74 udelay(1); 75 76 return 0; 77 } 78 79 int dram_init(void) 80 { 81 if (fdtdec_setup_mem_size_base() != 0) 82 return -EINVAL; 83 84 return 0; 85 } 86 87 int dram_init_banksize(void) 88 { 89 fdtdec_setup_memory_banksize(); 90 91 return 0; 92 } 93 94 /* porter has KSZ8041RNLI */ 95 #define PHY_CONTROL1 0x1E 96 #define PHY_LED_MODE 0xC000 97 #define PHY_LED_MODE_ACK 0x4000 98 int board_phy_config(struct phy_device *phydev) 99 { 100 int ret = phy_read(phydev, MDIO_DEVAD_NONE, PHY_CONTROL1); 101 ret &= ~PHY_LED_MODE; 102 ret |= PHY_LED_MODE_ACK; 103 ret = phy_write(phydev, MDIO_DEVAD_NONE, PHY_CONTROL1, (u16)ret); 104 105 return 0; 106 } 107 108 void reset_cpu(ulong addr) 109 { 110 struct udevice *dev; 111 const u8 pmic_bus = 1; 112 const u8 pmic_addr = 0x5a; 113 u8 data; 114 int ret; 115 116 ret = i2c_get_chip_for_busnum(pmic_bus, pmic_addr, 1, &dev); 117 if (ret) 118 hang(); 119 120 ret = dm_i2c_read(dev, 0x13, &data, 1); 121 if (ret) 122 hang(); 123 124 data |= BIT(1); 125 126 ret = dm_i2c_write(dev, 0x13, &data, 1); 127 if (ret) 128 hang(); 129 } 130 131 enum env_location env_get_location(enum env_operation op, int prio) 132 { 133 const u32 load_magic = 0xb33fc0de; 134 135 /* Block environment access if loaded using JTAG */ 136 if ((readl(CONFIG_SPL_TEXT_BASE + 0x24) == load_magic) && 137 (op != ENVOP_INIT)) 138 return ENVL_UNKNOWN; 139 140 if (prio) 141 return ENVL_UNKNOWN; 142 143 return ENVL_SPI_FLASH; 144 } 145