1*83d290c5STom Rini // SPDX-License-Identifier: GPL-2.0+ 2c6525d45SNobuhiro Iwamatsu /* 3c6525d45SNobuhiro Iwamatsu * Copyright (C) 2008 Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com> 4c6525d45SNobuhiro Iwamatsu */ 5c6525d45SNobuhiro Iwamatsu 6c6525d45SNobuhiro Iwamatsu #include <common.h> 7c6525d45SNobuhiro Iwamatsu #include <asm/io.h> 8c6525d45SNobuhiro Iwamatsu #include <asm/processor.h> 9c6525d45SNobuhiro Iwamatsu #include <asm/pci.h> 10c6525d45SNobuhiro Iwamatsu #include <netdev.h> 11c6525d45SNobuhiro Iwamatsu 12c6525d45SNobuhiro Iwamatsu int checkboard(void) 13c6525d45SNobuhiro Iwamatsu { 14c6525d45SNobuhiro Iwamatsu puts("BOARD: Renesas Technology Corp. R0P7785LC0011RL\n"); 15c6525d45SNobuhiro Iwamatsu return 0; 16c6525d45SNobuhiro Iwamatsu } 17c6525d45SNobuhiro Iwamatsu 18c6525d45SNobuhiro Iwamatsu int board_init(void) 19c6525d45SNobuhiro Iwamatsu { 20c6525d45SNobuhiro Iwamatsu return 0; 21c6525d45SNobuhiro Iwamatsu } 22c6525d45SNobuhiro Iwamatsu 23c6525d45SNobuhiro Iwamatsu static struct pci_controller hose; 24c6525d45SNobuhiro Iwamatsu void pci_init_board(void) 25c6525d45SNobuhiro Iwamatsu { 26c6525d45SNobuhiro Iwamatsu pci_sh7780_init(&hose); 27c6525d45SNobuhiro Iwamatsu } 28c6525d45SNobuhiro Iwamatsu 29c6525d45SNobuhiro Iwamatsu int board_eth_init(bd_t *bis) 30c6525d45SNobuhiro Iwamatsu { 31c6525d45SNobuhiro Iwamatsu return pci_eth_init(bis); 32c6525d45SNobuhiro Iwamatsu } 33ada93182SYoshihiro Shimoda 34ada93182SYoshihiro Shimoda #if defined(CONFIG_SH_32BIT) 3554841ab5SWolfgang Denk int do_pmb(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) 36ada93182SYoshihiro Shimoda { 37ada93182SYoshihiro Shimoda /* clear ITLB */ 38ada93182SYoshihiro Shimoda writel(0x00000004, 0xff000010); 39ada93182SYoshihiro Shimoda 40ada93182SYoshihiro Shimoda /* delete PMB for peripheral */ 41ada93182SYoshihiro Shimoda writel(0, PMB_ADDR_BASE(0)); 42ada93182SYoshihiro Shimoda writel(0, PMB_DATA_BASE(0)); 43ada93182SYoshihiro Shimoda writel(0, PMB_ADDR_BASE(1)); 44ada93182SYoshihiro Shimoda writel(0, PMB_DATA_BASE(1)); 45ada93182SYoshihiro Shimoda writel(0, PMB_ADDR_BASE(2)); 46ada93182SYoshihiro Shimoda writel(0, PMB_DATA_BASE(2)); 47ada93182SYoshihiro Shimoda 48ada93182SYoshihiro Shimoda /* add PMB for SDRAM(0x40000000 - 0x47ffffff) */ 49ada93182SYoshihiro Shimoda writel(mk_pmb_addr_val(0x80), PMB_ADDR_BASE(8)); 50ada93182SYoshihiro Shimoda writel(mk_pmb_data_val(0x40, 0, 1, 1, 0, 1, 1), PMB_DATA_BASE(8)); 51ada93182SYoshihiro Shimoda writel(mk_pmb_addr_val(0xa0), PMB_ADDR_BASE(12)); 52ada93182SYoshihiro Shimoda writel(mk_pmb_data_val(0x40, 1, 1, 1, 0, 0, 1), PMB_DATA_BASE(12)); 53ada93182SYoshihiro Shimoda 54ada93182SYoshihiro Shimoda return 0; 55ada93182SYoshihiro Shimoda } 56ada93182SYoshihiro Shimoda 57ada93182SYoshihiro Shimoda U_BOOT_CMD( 58ada93182SYoshihiro Shimoda pmb, 1, 1, do_pmb, 59ada93182SYoshihiro Shimoda "pmb - PMB setting\n", 60ada93182SYoshihiro Shimoda "\n" 61a89c33dbSWolfgang Denk " - PMB setting for all SDRAM mapping" 62ada93182SYoshihiro Shimoda ); 63ada93182SYoshihiro Shimoda #endif 64