1/*
2 * Copyright (C) 2008 Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License as
6 * published by the Free Software Foundation; either version 2 of
7 * the License, or (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
17 * MA 02111-1307 USA
18 */
19#include <config.h>
20#include <version.h>
21#include <asm/processor.h>
22
23.macro	write32, addr, data
24	mov.l \addr ,r1
25	mov.l \data ,r0
26	mov.l r0, @r1
27.endm
28
29.macro	write16, addr, data
30	mov.l \addr ,r1
31	mov.l \data ,r0
32	mov.w r0, @r1
33.endm
34
35.macro	write8, addr, data
36	mov.l \addr ,r1
37	mov.l \data ,r0
38	mov.b r0, @r1
39.endm
40
41.macro	wait_timer, time
42	mov.l	\time ,r3
431:
44	nop
45	tst	r3, r3
46	bf/s	1b
47	dt	r3
48.endm
49
50#include <asm/processor.h>
51
52	.global	lowlevel_init
53
54	.text
55	.align	2
56
57lowlevel_init:
58	wait_timer	WAIT_200US
59	wait_timer	WAIT_200US
60
61	/*------- LBSC -------*/
62	write32 MMSELR_A,	MMSELR_D
63
64	/*------- DBSC2 -------*/
65	write32 DBSC2_DBCONF_A,	DBSC2_DBCONF_D
66	write32 DBSC2_DBTR0_A,	DBSC2_DBTR0_D
67	write32 DBSC2_DBTR1_A,	DBSC2_DBTR1_D
68	write32 DBSC2_DBTR2_A,	DBSC2_DBTR2_D
69	write32 DBSC2_DBFREQ_A,	DBSC2_DBFREQ_D1
70	write32 DBSC2_DBFREQ_A,	DBSC2_DBFREQ_D2
71	wait_timer	WAIT_200US
72
73	write32 DBSC2_DBDICODTOCD_A,	DBSC2_DBDICODTOCD_D
74	write32 DBSC2_DBCMDCNT_A,	DBSC2_DBCMDCNT_D_CKE_H
75	wait_timer	WAIT_200US
76	write32 DBSC2_DBCMDCNT_A,	DBSC2_DBCMDCNT_D_PALL
77	write32 DBSC2_DBMRCNT_A,	DBSC2_DBMRCNT_D_EMRS2
78	write32 DBSC2_DBMRCNT_A,	DBSC2_DBMRCNT_D_EMRS3
79	write32 DBSC2_DBMRCNT_A,	DBSC2_DBMRCNT_D_EMRS1_1
80	write32 DBSC2_DBMRCNT_A,	DBSC2_DBMRCNT_D_MRS_1
81	write32 DBSC2_DBCMDCNT_A,	DBSC2_DBCMDCNT_D_PALL
82	write32 DBSC2_DBCMDCNT_A,	DBSC2_DBCMDCNT_D_REF
83	write32 DBSC2_DBCMDCNT_A,	DBSC2_DBCMDCNT_D_REF
84	write32 DBSC2_DBMRCNT_A,	DBSC2_DBMRCNT_D_MRS_2
85	wait_timer	WAIT_200US
86
87	write32 DBSC2_DBMRCNT_A,	DBSC2_DBMRCNT_D_EMRS1_2
88	write32 DBSC2_DBMRCNT_A,	DBSC2_DBMRCNT_D_EMRS1_1
89
90	write32 DBSC2_DBEN_A,		DBSC2_DBEN_D
91	write32 DBSC2_DBRFCNT1_A,	DBSC2_DBRFCNT1_D
92	write32 DBSC2_DBRFCNT2_A,	DBSC2_DBRFCNT2_D
93	write32 DBSC2_DBRFCNT0_A,	DBSC2_DBRFCNT0_D
94	wait_timer	WAIT_200US
95
96	/*------- GPIO -------*/
97	write16 PACR_A,	PACR_D
98	write16 PBCR_A,	PBCR_D
99	write16 PCCR_A,	PCCR_D
100	write16 PDCR_A,	PDCR_D
101	write16 PECR_A,	PECR_D
102	write16 PFCR_A,	PFCR_D
103	write16 PGCR_A,	PGCR_D
104	write16 PHCR_A,	PHCR_D
105	write16 PJCR_A,	PJCR_D
106	write16 PKCR_A,	PKCR_D
107	write16 PLCR_A,	PLCR_D
108	write16 PMCR_A,	PMCR_D
109	write16 PNCR_A,	PNCR_D
110	write16 PPCR_A,	PPCR_D
111	write16 PQCR_A,	PQCR_D
112	write16 PRCR_A,	PRCR_D
113
114	write8	PEPUPR_A,	PEPUPR_D
115	write8	PHPUPR_A,	PHPUPR_D
116	write8	PJPUPR_A,	PJPUPR_D
117	write8	PKPUPR_A,	PKPUPR_D
118	write8	PLPUPR_A,	PLPUPR_D
119	write8	PMPUPR_A,	PMPUPR_D
120	write8	PNPUPR_A,	PNPUPR_D
121	write16	PPUPR1_A,	PPUPR1_D
122	write16	PPUPR2_A,	PPUPR2_D
123	write16	P1MSELR_A,	P1MSELR_D
124	write16	P2MSELR_A,	P2MSELR_D
125
126	/*------- LBSC -------*/
127	write32	BCR_A,		BCR_D
128	write32	CS0BCR_A,	CS0BCR_D
129	write32	CS0WCR_A,	CS0WCR_D
130	write32	CS1BCR_A,	CS1BCR_D
131	write32	CS1WCR_A,	CS1WCR_D
132	write32	CS4BCR_A,	CS4BCR_D
133	write32	CS4WCR_A,	CS4WCR_D
134
135	mov.l	PASCR_A, r0
136	mov.l	@r0, r2
137	mov.l	PASCR_32BIT_MODE, r1
138	tst	r1, r2
139	bt	lbsc_29bit
140
141	write32	CS2BCR_A,	CS_USB_BCR_D
142	write32	CS2WCR_A,	CS_USB_WCR_D
143	write32	CS3BCR_A,	CS_SD_BCR_D
144	write32	CS3WCR_A,	CS_SD_WCR_D
145	write32	CS5BCR_A,	CS_I2C_BCR_D
146	write32	CS5WCR_A,	CS_I2C_WCR_D
147	write32	CS6BCR_A,	CS0BCR_D
148	write32	CS6WCR_A,	CS0WCR_D
149	bra	lbsc_end
150	 nop
151
152lbsc_29bit:
153	write32	CS5BCR_A,	CS_USB_BCR_D
154	write32	CS5WCR_A,	CS_USB_WCR_D
155	write32	CS6BCR_A,	CS_SD_BCR_D
156	write32	CS6WCR_A,	CS_SD_WCR_D
157
158lbsc_end:
159
160	write32	CCR_A,	CCR_D
161
162	rts
163	nop
164
165	.align 4
166
167/*------- LBSC -------*/
168MMSELR_A:	.long	0xfc400020
169MMSELR_D:	.long	0xa5a50002
170
171/*------- DBSC2 -------*/
172#define DBSC2_BASE	0xfe800000
173DBSC2_DBSTATE_A:	.long	DBSC2_BASE + 0x0c
174DBSC2_DBEN_A:		.long	DBSC2_BASE + 0x10
175DBSC2_DBCMDCNT_A:	.long	DBSC2_BASE + 0x14
176DBSC2_DBCONF_A:		.long	DBSC2_BASE + 0x20
177DBSC2_DBTR0_A:		.long	DBSC2_BASE + 0x30
178DBSC2_DBTR1_A:		.long	DBSC2_BASE + 0x34
179DBSC2_DBTR2_A:		.long	DBSC2_BASE + 0x38
180DBSC2_DBRFCNT0_A:	.long	DBSC2_BASE + 0x40
181DBSC2_DBRFCNT1_A:	.long	DBSC2_BASE + 0x44
182DBSC2_DBRFCNT2_A:	.long	DBSC2_BASE + 0x48
183DBSC2_DBRFSTS_A:	.long	DBSC2_BASE + 0x4c
184DBSC2_DBFREQ_A:		.long	DBSC2_BASE + 0x50
185DBSC2_DBDICODTOCD_A:	.long	DBSC2_BASE + 0x54
186DBSC2_DBMRCNT_A:	.long	DBSC2_BASE + 0x60
187DDR_DUMMY_ACCESS_A:	.long	0x40000000
188
189DBSC2_DBCONF_D:		.long	0x00630002
190DBSC2_DBTR0_D:		.long	0x050b1f04
191DBSC2_DBTR1_D:		.long	0x00040204
192DBSC2_DBTR2_D:		.long	0x02100308
193DBSC2_DBFREQ_D1:	.long	0x00000000
194DBSC2_DBFREQ_D2:	.long	0x00000100
195DBSC2_DBDICODTOCD_D:	.long	0x000f0907
196
197DBSC2_DBCMDCNT_D_CKE_H:	.long	0x00000003
198DBSC2_DBCMDCNT_D_PALL:	.long	0x00000002
199DBSC2_DBCMDCNT_D_REF:	.long	0x00000004
200
201DBSC2_DBMRCNT_D_EMRS2:	.long	0x00020000
202DBSC2_DBMRCNT_D_EMRS3:	.long	0x00030000
203DBSC2_DBMRCNT_D_EMRS1_1:	.long	0x00010006
204DBSC2_DBMRCNT_D_EMRS1_2:	.long	0x00010386
205DBSC2_DBMRCNT_D_MRS_1:	.long	0x00000952
206DBSC2_DBMRCNT_D_MRS_2:	.long	0x00000852
207
208DBSC2_DBEN_D:		.long	0x00000001
209
210DBSC2_DBPDCNT0_D3:	.long	0x00000080
211DBSC2_DBRFCNT1_D:	.long	0x00000926
212DBSC2_DBRFCNT2_D:	.long	0x00fe00fe
213DBSC2_DBRFCNT0_D:	.long	0x00010000
214
215WAIT_200US:	.long	33333
216
217/*------- GPIO -------*/
218#define GPIO_BASE	0xffe70000
219PACR_A:		.long	GPIO_BASE + 0x00
220PBCR_A:		.long	GPIO_BASE + 0x02
221PCCR_A:		.long	GPIO_BASE + 0x04
222PDCR_A:		.long	GPIO_BASE + 0x06
223PECR_A:		.long	GPIO_BASE + 0x08
224PFCR_A:		.long	GPIO_BASE + 0x0a
225PGCR_A:		.long	GPIO_BASE + 0x0c
226PHCR_A:		.long	GPIO_BASE + 0x0e
227PJCR_A:		.long	GPIO_BASE + 0x10
228PKCR_A:		.long	GPIO_BASE + 0x12
229PLCR_A:		.long	GPIO_BASE + 0x14
230PMCR_A:		.long	GPIO_BASE + 0x16
231PNCR_A:		.long	GPIO_BASE + 0x18
232PPCR_A:		.long	GPIO_BASE + 0x1a
233PQCR_A:		.long	GPIO_BASE + 0x1c
234PRCR_A:		.long	GPIO_BASE + 0x1e
235PEPUPR_A:	.long	GPIO_BASE + 0x48
236PHPUPR_A:	.long	GPIO_BASE + 0x4e
237PJPUPR_A:	.long	GPIO_BASE + 0x50
238PKPUPR_A:	.long	GPIO_BASE + 0x52
239PLPUPR_A:	.long	GPIO_BASE + 0x54
240PMPUPR_A:	.long	GPIO_BASE + 0x56
241PNPUPR_A:	.long	GPIO_BASE + 0x58
242PPUPR1_A:	.long	GPIO_BASE + 0x60
243PPUPR2_A:	.long	GPIO_BASE + 0x62
244P1MSELR_A:	.long	GPIO_BASE + 0x80
245P2MSELR_A:	.long	GPIO_BASE + 0x82
246
247PACR_D:		.long	0x0000
248PBCR_D:		.long	0x0000
249PCCR_D:		.long	0x0000
250PDCR_D:		.long	0x0000
251PECR_D:		.long	0x0000
252PFCR_D:		.long	0x0000
253PGCR_D:		.long	0x0000
254PHCR_D:		.long	0x00c0
255PJCR_D:		.long	0xc3fc
256PKCR_D:		.long	0x03ff
257PLCR_D:		.long	0x0000
258PMCR_D:		.long	0xffff
259PNCR_D:		.long	0xf0c3
260PPCR_D:		.long	0x0000
261PQCR_D:		.long	0x0000
262PRCR_D:		.long	0x0000
263
264PEPUPR_D:	.long	0xff
265PHPUPR_D:	.long	0x00
266PJPUPR_D:	.long	0x00
267PKPUPR_D:	.long	0x00
268PLPUPR_D:	.long	0x00
269PMPUPR_D:	.long	0xfc
270PNPUPR_D:	.long	0x00
271PPUPR1_D:	.long	0xffbf
272PPUPR2_D:	.long	0xff00
273P1MSELR_D:	.long	0x3780
274P2MSELR_D:	.long	0x0000
275
276/*------- LBSC -------*/
277PASCR_A:		.long	0xff000070
278PASCR_32BIT_MODE:	.long	0x80000000	/* check booting mode */
279
280BCR_A:		.long	BCR
281CS0BCR_A:	.long	CS0BCR
282CS0WCR_A:	.long	CS0WCR
283CS1BCR_A:	.long	CS1BCR
284CS1WCR_A:	.long	CS1WCR
285CS2BCR_A:	.long	CS2BCR
286CS2WCR_A:	.long	CS2WCR
287CS3BCR_A:	.long	CS3BCR
288CS3WCR_A:	.long	CS3WCR
289CS4BCR_A:	.long	CS4BCR
290CS4WCR_A:	.long	CS4WCR
291CS5BCR_A:	.long	CS5BCR
292CS5WCR_A:	.long	CS5WCR
293CS6BCR_A:	.long	CS6BCR
294CS6WCR_A:	.long	CS6WCR
295
296BCR_D:		.long	0x80000003
297CS0BCR_D:	.long	0x22222340
298CS0WCR_D:	.long	0x00111118
299CS1BCR_D:	.long	0x11111100
300CS1WCR_D:	.long	0x33333303
301CS4BCR_D:	.long	0x11111300
302CS4WCR_D:	.long	0x00101012
303
304/* USB setting : 32bit mode = CS2, 29bit mode = CS5 */
305CS_USB_BCR_D:	.long	0x11111200
306CS_USB_WCR_D:	.long	0x00020004
307
308/* SD setting : 32bit mode = CS3, 29bit mode = CS6 */
309CS_SD_BCR_D:	.long	0x00000300
310CS_SD_WCR_D:	.long	0x00030108
311
312/* I2C setting : 32bit mode = CS5, 29bit mode = CS1(already setting) */
313CS_I2C_BCR_D:	.long	0x11111100
314CS_I2C_WCR_D:	.long	0x00000003
315
316CCR_A:		.long	0xff00001c
317CCR_D:		.long	0x0000090b
318