1/*
2 * Copyright (C) 2008 Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
3 *
4 * SPDX-License-Identifier:	GPL-2.0+
5 */
6#include <config.h>
7#include <asm/processor.h>
8#include <asm/macro.h>
9
10#include <asm/processor.h>
11
12	.global	lowlevel_init
13
14	.text
15	.align	2
16
17lowlevel_init:
18	wait_timer	WAIT_200US
19	wait_timer	WAIT_200US
20
21	/*------- LBSC -------*/
22	write32 MMSELR_A,	MMSELR_D
23
24	/*------- DBSC2 -------*/
25	write32 DBSC2_DBCONF_A,	DBSC2_DBCONF_D
26	write32 DBSC2_DBTR0_A,	DBSC2_DBTR0_D
27	write32 DBSC2_DBTR1_A,	DBSC2_DBTR1_D
28	write32 DBSC2_DBTR2_A,	DBSC2_DBTR2_D
29	write32 DBSC2_DBFREQ_A,	DBSC2_DBFREQ_D1
30	write32 DBSC2_DBFREQ_A,	DBSC2_DBFREQ_D2
31	wait_timer	WAIT_200US
32
33	write32 DBSC2_DBDICODTOCD_A,	DBSC2_DBDICODTOCD_D
34	write32 DBSC2_DBCMDCNT_A,	DBSC2_DBCMDCNT_D_CKE_H
35	wait_timer	WAIT_200US
36	write32 DBSC2_DBCMDCNT_A,	DBSC2_DBCMDCNT_D_PALL
37	write32 DBSC2_DBMRCNT_A,	DBSC2_DBMRCNT_D_EMRS2
38	write32 DBSC2_DBMRCNT_A,	DBSC2_DBMRCNT_D_EMRS3
39	write32 DBSC2_DBMRCNT_A,	DBSC2_DBMRCNT_D_EMRS1_1
40	write32 DBSC2_DBMRCNT_A,	DBSC2_DBMRCNT_D_MRS_1
41	write32 DBSC2_DBCMDCNT_A,	DBSC2_DBCMDCNT_D_PALL
42	write32 DBSC2_DBCMDCNT_A,	DBSC2_DBCMDCNT_D_REF
43	write32 DBSC2_DBCMDCNT_A,	DBSC2_DBCMDCNT_D_REF
44	write32 DBSC2_DBMRCNT_A,	DBSC2_DBMRCNT_D_MRS_2
45	wait_timer	WAIT_200US
46
47	write32 DBSC2_DBMRCNT_A,	DBSC2_DBMRCNT_D_EMRS1_2
48	write32 DBSC2_DBMRCNT_A,	DBSC2_DBMRCNT_D_EMRS1_1
49
50	write32 DBSC2_DBEN_A,		DBSC2_DBEN_D
51	write32 DBSC2_DBRFCNT1_A,	DBSC2_DBRFCNT1_D
52	write32 DBSC2_DBRFCNT2_A,	DBSC2_DBRFCNT2_D
53	write32 DBSC2_DBRFCNT0_A,	DBSC2_DBRFCNT0_D
54	wait_timer	WAIT_200US
55
56	/*------- GPIO -------*/
57	write16 PACR_A,	PXCR_D
58	write16 PBCR_A,	PXCR_D
59	write16 PCCR_A,	PXCR_D
60	write16 PDCR_A,	PXCR_D
61	write16 PECR_A,	PXCR_D
62	write16 PFCR_A,	PXCR_D
63	write16 PGCR_A,	PXCR_D
64	write16 PHCR_A,	PHCR_D
65	write16 PJCR_A,	PJCR_D
66	write16 PKCR_A,	PKCR_D
67	write16 PLCR_A,	PXCR_D
68	write16 PMCR_A,	PMCR_D
69	write16 PNCR_A,	PNCR_D
70	write16 PPCR_A,	PXCR_D
71	write16 PQCR_A,	PXCR_D
72	write16 PRCR_A,	PXCR_D
73
74	write8	PEPUPR_A,	PEPUPR_D
75	write8	PHPUPR_A,	PHPUPR_D
76	write8	PJPUPR_A,	PJPUPR_D
77	write8	PKPUPR_A,	PKPUPR_D
78	write8	PLPUPR_A,	PLPUPR_D
79	write8	PMPUPR_A,	PMPUPR_D
80	write8	PNPUPR_A,	PNPUPR_D
81	write16	PPUPR1_A,	PPUPR1_D
82	write16	PPUPR2_A,	PPUPR2_D
83	write16	P1MSELR_A,	P1MSELR_D
84	write16	P2MSELR_A,	P2MSELR_D
85
86	/*------- LBSC -------*/
87	write32	BCR_A,		BCR_D
88	write32	CS0BCR_A,	CS0BCR_D
89	write32	CS0WCR_A,	CS0WCR_D
90	write32	CS1BCR_A,	CS1BCR_D
91	write32	CS1WCR_A,	CS1WCR_D
92	write32	CS4BCR_A,	CS4BCR_D
93	write32	CS4WCR_A,	CS4WCR_D
94
95	mov.l	PASCR_A, r0
96	mov.l	@r0, r2
97	mov.l	PASCR_32BIT_MODE, r1
98	tst	r1, r2
99	bt	lbsc_29bit
100
101	write32	CS2BCR_A,	CS_USB_BCR_D
102	write32	CS2WCR_A,	CS_USB_WCR_D
103	write32	CS3BCR_A,	CS_SD_BCR_D
104	write32	CS3WCR_A,	CS_SD_WCR_D
105	write32	CS5BCR_A,	CS_I2C_BCR_D
106	write32	CS5WCR_A,	CS_I2C_WCR_D
107	write32	CS6BCR_A,	CS0BCR_D
108	write32	CS6WCR_A,	CS0WCR_D
109	bra	lbsc_end
110	 nop
111
112lbsc_29bit:
113	write32	CS5BCR_A,	CS_USB_BCR_D
114	write32	CS5WCR_A,	CS_USB_WCR_D
115	write32	CS6BCR_A,	CS_SD_BCR_D
116	write32	CS6WCR_A,	CS_SD_WCR_D
117
118lbsc_end:
119#if defined(CONFIG_SH_32BIT)
120	/*------- set PMB -------*/
121	write32	PASCR_A,	PASCR_29BIT_D
122	write32	MMUCR_A,	MMUCR_D
123
124	/*****************************************************************
125	 * ent	virt		phys		v	sz	c	wt
126	 * 0	0xa0000000	0x00000000	1	64M	0	0
127	 * 1	0xa4000000	0x04000000	1	16M	0	0
128	 * 2	0xa6000000	0x08000000	1	16M	0	0
129	 * 9	0x88000000	0x48000000	1	128M	1	1
130	 * 10	0x90000000	0x50000000	1	128M	1	1
131	 * 11	0x98000000	0x58000000	1	128M	1	1
132	 * 13	0xa8000000	0x48000000	1	128M	0	0
133	 * 14	0xb0000000	0x50000000	1	128M	0	0
134	 * 15	0xb8000000	0x58000000	1	128M	0	0
135	 */
136	write32	PMB_ADDR_FLASH_A,	PMB_ADDR_FLASH_D
137	write32	PMB_DATA_FLASH_A,	PMB_DATA_FLASH_D
138	write32	PMB_ADDR_CPLD_A,	PMB_ADDR_CPLD_D
139	write32	PMB_DATA_CPLD_A,	PMB_DATA_CPLD_D
140	write32	PMB_ADDR_USB_A,		PMB_ADDR_USB_D
141	write32	PMB_DATA_USB_A,		PMB_DATA_USB_D
142	write32	PMB_ADDR_DDR_C1_A,	PMB_ADDR_DDR_C1_D
143	write32	PMB_DATA_DDR_C1_A,	PMB_DATA_DDR_C1_D
144	write32	PMB_ADDR_DDR_C2_A,	PMB_ADDR_DDR_C2_D
145	write32	PMB_DATA_DDR_C2_A,	PMB_DATA_DDR_C2_D
146	write32	PMB_ADDR_DDR_C3_A,	PMB_ADDR_DDR_C3_D
147	write32	PMB_DATA_DDR_C3_A,	PMB_DATA_DDR_C3_D
148	write32	PMB_ADDR_DDR_N1_A,	PMB_ADDR_DDR_N1_D
149	write32	PMB_DATA_DDR_N1_A,	PMB_DATA_DDR_N1_D
150	write32	PMB_ADDR_DDR_N2_A,	PMB_ADDR_DDR_N2_D
151	write32	PMB_DATA_DDR_N2_A,	PMB_DATA_DDR_N2_D
152	write32	PMB_ADDR_DDR_N3_A,	PMB_ADDR_DDR_N3_D
153	write32	PMB_DATA_DDR_N3_A,	PMB_DATA_DDR_N3_D
154
155	write32	PASCR_A,	PASCR_INIT
156	mov.l	DUMMY_ADDR, r0
157	icbi	@r0
158#endif
159
160	write32	CCR_A,	CCR_D
161
162	rts
163	nop
164
165	.align 4
166
167/*------- GPIO -------*/
168/* P{A,B C,D,E,F,G,L,P,Q,R}CR_D */
169PXCR_D:		.word	0x0000
170
171PHCR_D:		.word	0x00c0
172PJCR_D:		.word	0xc3fc
173PKCR_D:		.word	0x03ff
174PMCR_D:		.word	0xffff
175PNCR_D:		.word	0xf0c3
176
177PEPUPR_D:	.long	0xff
178PHPUPR_D:	.long	0x00
179PJPUPR_D:	.long	0x00
180PKPUPR_D:	.long	0x00
181PLPUPR_D:	.long	0x00
182PMPUPR_D:	.long	0xfc
183PNPUPR_D:	.long	0x00
184PPUPR1_D:	.word	0xffbf
185PPUPR2_D:	.word	0xff00
186P1MSELR_D:	.word	0x3780
187P2MSELR_D:	.word	0x0000
188
189#define GPIO_BASE	0xffe70000
190PACR_A:		.long	GPIO_BASE + 0x00
191PBCR_A:		.long	GPIO_BASE + 0x02
192PCCR_A:		.long	GPIO_BASE + 0x04
193PDCR_A:		.long	GPIO_BASE + 0x06
194PECR_A:		.long	GPIO_BASE + 0x08
195PFCR_A:		.long	GPIO_BASE + 0x0a
196PGCR_A:		.long	GPIO_BASE + 0x0c
197PHCR_A:		.long	GPIO_BASE + 0x0e
198PJCR_A:		.long	GPIO_BASE + 0x10
199PKCR_A:		.long	GPIO_BASE + 0x12
200PLCR_A:		.long	GPIO_BASE + 0x14
201PMCR_A:		.long	GPIO_BASE + 0x16
202PNCR_A:		.long	GPIO_BASE + 0x18
203PPCR_A:		.long	GPIO_BASE + 0x1a
204PQCR_A:		.long	GPIO_BASE + 0x1c
205PRCR_A:		.long	GPIO_BASE + 0x1e
206PEPUPR_A:	.long	GPIO_BASE + 0x48
207PHPUPR_A:	.long	GPIO_BASE + 0x4e
208PJPUPR_A:	.long	GPIO_BASE + 0x50
209PKPUPR_A:	.long	GPIO_BASE + 0x52
210PLPUPR_A:	.long	GPIO_BASE + 0x54
211PMPUPR_A:	.long	GPIO_BASE + 0x56
212PNPUPR_A:	.long	GPIO_BASE + 0x58
213PPUPR1_A:	.long	GPIO_BASE + 0x60
214PPUPR2_A:	.long	GPIO_BASE + 0x62
215P1MSELR_A:	.long	GPIO_BASE + 0x80
216P2MSELR_A:	.long	GPIO_BASE + 0x82
217
218MMSELR_A:      .long   0xfc400020
219#if defined(CONFIG_SH_32BIT)
220MMSELR_D:      .long   0xa5a50005
221#else
222MMSELR_D:      .long   0xa5a50002
223#endif
224
225/*------- DBSC2 -------*/
226#define DBSC2_BASE	0xfe800000
227DBSC2_DBSTATE_A:	.long	DBSC2_BASE + 0x0c
228DBSC2_DBEN_A:		.long	DBSC2_BASE + 0x10
229DBSC2_DBCMDCNT_A:	.long	DBSC2_BASE + 0x14
230DBSC2_DBCONF_A:		.long	DBSC2_BASE + 0x20
231DBSC2_DBTR0_A:		.long	DBSC2_BASE + 0x30
232DBSC2_DBTR1_A:		.long	DBSC2_BASE + 0x34
233DBSC2_DBTR2_A:		.long	DBSC2_BASE + 0x38
234DBSC2_DBRFCNT0_A:	.long	DBSC2_BASE + 0x40
235DBSC2_DBRFCNT1_A:	.long	DBSC2_BASE + 0x44
236DBSC2_DBRFCNT2_A:	.long	DBSC2_BASE + 0x48
237DBSC2_DBRFSTS_A:	.long	DBSC2_BASE + 0x4c
238DBSC2_DBFREQ_A:		.long	DBSC2_BASE + 0x50
239DBSC2_DBDICODTOCD_A:.long	DBSC2_BASE + 0x54
240DBSC2_DBMRCNT_A:	.long	DBSC2_BASE + 0x60
241DDR_DUMMY_ACCESS_A:	.long	0x40000000
242
243DBSC2_DBCONF_D:		.long	0x00630002
244DBSC2_DBTR0_D:		.long	0x050b1f04
245DBSC2_DBTR1_D:		.long	0x00040204
246DBSC2_DBTR2_D:		.long	0x02100308
247DBSC2_DBFREQ_D1:	.long	0x00000000
248DBSC2_DBFREQ_D2:	.long	0x00000100
249DBSC2_DBDICODTOCD_D:.long	0x000f0907
250
251DBSC2_DBCMDCNT_D_CKE_H:	.long	0x00000003
252DBSC2_DBCMDCNT_D_PALL:	.long	0x00000002
253DBSC2_DBCMDCNT_D_REF:	.long	0x00000004
254
255DBSC2_DBMRCNT_D_EMRS2:	.long	0x00020000
256DBSC2_DBMRCNT_D_EMRS3:	.long	0x00030000
257DBSC2_DBMRCNT_D_EMRS1_1:	.long	0x00010006
258DBSC2_DBMRCNT_D_EMRS1_2:	.long	0x00010386
259DBSC2_DBMRCNT_D_MRS_1:	.long	0x00000952
260DBSC2_DBMRCNT_D_MRS_2:	.long	0x00000852
261
262DBSC2_DBEN_D:		.long	0x00000001
263
264DBSC2_DBPDCNT0_D3:	.long	0x00000080
265DBSC2_DBRFCNT1_D:	.long	0x00000926
266DBSC2_DBRFCNT2_D:	.long	0x00fe00fe
267DBSC2_DBRFCNT0_D:	.long	0x00010000
268
269WAIT_200US:    .long   33333
270
271/*------- LBSC -------*/
272PASCR_A:		.long	0xff000070
273PASCR_32BIT_MODE:	.long	0x80000000	/* check booting mode */
274
275BCR_A:		.long	BCR
276CS0BCR_A:	.long	CS0BCR
277CS0WCR_A:	.long	CS0WCR
278CS1BCR_A:	.long	CS1BCR
279CS1WCR_A:	.long	CS1WCR
280CS2BCR_A:	.long	CS2BCR
281CS2WCR_A:	.long	CS2WCR
282CS3BCR_A:	.long	CS3BCR
283CS3WCR_A:	.long	CS3WCR
284CS4BCR_A:	.long	CS4BCR
285CS4WCR_A:	.long	CS4WCR
286CS5BCR_A:	.long	CS5BCR
287CS5WCR_A:	.long	CS5WCR
288CS6BCR_A:	.long	CS6BCR
289CS6WCR_A:	.long	CS6WCR
290
291BCR_D:		.long	0x80000003
292CS0BCR_D:	.long	0x22222340
293CS0WCR_D:	.long	0x00111118
294CS1BCR_D:	.long	0x11111100
295CS1WCR_D:	.long	0x33333303
296CS4BCR_D:	.long	0x11111300
297CS4WCR_D:	.long	0x00101012
298
299/* USB setting : 32bit mode = CS2, 29bit mode = CS5 */
300CS_USB_BCR_D:	.long	0x11111200
301CS_USB_WCR_D:	.long	0x00020005
302
303/* SD setting : 32bit mode = CS3, 29bit mode = CS6 */
304CS_SD_BCR_D:	.long	0x00000300
305CS_SD_WCR_D:	.long	0x00030108
306
307/* I2C setting : 32bit mode = CS5, 29bit mode = CS1(already setting) */
308CS_I2C_BCR_D:	.long	0x11111100
309CS_I2C_WCR_D:	.long	0x00000003
310
311#if defined(CONFIG_SH_32BIT)
312/*------- set PMB -------*/
313PMB_ADDR_FLASH_A:	.long	PMB_ADDR_BASE(0)
314PMB_ADDR_CPLD_A:	.long	PMB_ADDR_BASE(1)
315PMB_ADDR_USB_A:		.long	PMB_ADDR_BASE(2)
316PMB_ADDR_DDR_C1_A:	.long	PMB_ADDR_BASE(9)
317PMB_ADDR_DDR_C2_A:	.long	PMB_ADDR_BASE(10)
318PMB_ADDR_DDR_C3_A:	.long	PMB_ADDR_BASE(11)
319PMB_ADDR_DDR_N1_A:	.long	PMB_ADDR_BASE(13)
320PMB_ADDR_DDR_N2_A:	.long	PMB_ADDR_BASE(14)
321PMB_ADDR_DDR_N3_A:	.long	PMB_ADDR_BASE(15)
322
323PMB_ADDR_FLASH_D:	.long	mk_pmb_addr_val(0xa0)
324PMB_ADDR_CPLD_D:	.long	mk_pmb_addr_val(0xa4)
325PMB_ADDR_USB_D:		.long	mk_pmb_addr_val(0xa6)
326PMB_ADDR_DDR_C1_D:	.long	mk_pmb_addr_val(0x88)
327PMB_ADDR_DDR_C2_D:	.long	mk_pmb_addr_val(0x90)
328PMB_ADDR_DDR_C3_D:	.long	mk_pmb_addr_val(0x98)
329PMB_ADDR_DDR_N1_D:	.long	mk_pmb_addr_val(0xa8)
330PMB_ADDR_DDR_N2_D:	.long	mk_pmb_addr_val(0xb0)
331PMB_ADDR_DDR_N3_D:	.long	mk_pmb_addr_val(0xb8)
332
333PMB_DATA_FLASH_A:	.long	PMB_DATA_BASE(0)
334PMB_DATA_CPLD_A:	.long	PMB_DATA_BASE(1)
335PMB_DATA_USB_A:		.long	PMB_DATA_BASE(2)
336PMB_DATA_DDR_C1_A:	.long	PMB_DATA_BASE(9)
337PMB_DATA_DDR_C2_A:	.long	PMB_DATA_BASE(10)
338PMB_DATA_DDR_C3_A:	.long	PMB_DATA_BASE(11)
339PMB_DATA_DDR_N1_A:	.long	PMB_DATA_BASE(13)
340PMB_DATA_DDR_N2_A:	.long	PMB_DATA_BASE(14)
341PMB_DATA_DDR_N3_A:	.long	PMB_DATA_BASE(15)
342
343/*						ppn   ub v s1 s0  c  wt */
344PMB_DATA_FLASH_D:	.long	mk_pmb_data_val(0x00, 1, 1, 0, 1, 0, 1)
345PMB_DATA_CPLD_D:	.long	mk_pmb_data_val(0x04, 1, 1, 0, 0, 0, 1)
346PMB_DATA_USB_D:		.long	mk_pmb_data_val(0x08, 1, 1, 0, 0, 0, 1)
347PMB_DATA_DDR_C1_D:	.long	mk_pmb_data_val(0x48, 0, 1, 1, 0, 1, 1)
348PMB_DATA_DDR_C2_D:	.long	mk_pmb_data_val(0x50, 0, 1, 1, 0, 1, 1)
349PMB_DATA_DDR_C3_D:	.long	mk_pmb_data_val(0x58, 0, 1, 1, 0, 1, 1)
350PMB_DATA_DDR_N1_D:	.long	mk_pmb_data_val(0x48, 1, 1, 1, 0, 0, 1)
351PMB_DATA_DDR_N2_D:	.long	mk_pmb_data_val(0x50, 1, 1, 1, 0, 0, 1)
352PMB_DATA_DDR_N3_D:	.long	mk_pmb_data_val(0x58, 1, 1, 1, 0, 0, 1)
353
354DUMMY_ADDR:	.long	0xa0000000
355PASCR_29BIT_D:	.long	0x00000000
356PASCR_INIT:	.long	0x80000080	/* check booting mode */
357MMUCR_A:	.long	0xff000010
358MMUCR_D:	.long	0x00000004	/* clear ITLB */
359#endif	/* CONFIG_SH_32BIT */
360
361CCR_A:		.long	0xff00001c
362CCR_D:		.long	0x0000090b
363