1/*
2 * Copyright (C) 2008 Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License as
6 * published by the Free Software Foundation; either version 2 of
7 * the License, or (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
17 * MA 02111-1307 USA
18 */
19#include <config.h>
20#include <version.h>
21#include <asm/processor.h>
22#include <asm/macro.h>
23
24#include <asm/processor.h>
25
26	.global	lowlevel_init
27
28	.text
29	.align	2
30
31lowlevel_init:
32	wait_timer	WAIT_200US
33	wait_timer	WAIT_200US
34
35	/*------- LBSC -------*/
36	write32 MMSELR_A,	MMSELR_D
37
38	/*------- DBSC2 -------*/
39	write32 DBSC2_DBCONF_A,	DBSC2_DBCONF_D
40	write32 DBSC2_DBTR0_A,	DBSC2_DBTR0_D
41	write32 DBSC2_DBTR1_A,	DBSC2_DBTR1_D
42	write32 DBSC2_DBTR2_A,	DBSC2_DBTR2_D
43	write32 DBSC2_DBFREQ_A,	DBSC2_DBFREQ_D1
44	write32 DBSC2_DBFREQ_A,	DBSC2_DBFREQ_D2
45	wait_timer	WAIT_200US
46
47	write32 DBSC2_DBDICODTOCD_A,	DBSC2_DBDICODTOCD_D
48	write32 DBSC2_DBCMDCNT_A,	DBSC2_DBCMDCNT_D_CKE_H
49	wait_timer	WAIT_200US
50	write32 DBSC2_DBCMDCNT_A,	DBSC2_DBCMDCNT_D_PALL
51	write32 DBSC2_DBMRCNT_A,	DBSC2_DBMRCNT_D_EMRS2
52	write32 DBSC2_DBMRCNT_A,	DBSC2_DBMRCNT_D_EMRS3
53	write32 DBSC2_DBMRCNT_A,	DBSC2_DBMRCNT_D_EMRS1_1
54	write32 DBSC2_DBMRCNT_A,	DBSC2_DBMRCNT_D_MRS_1
55	write32 DBSC2_DBCMDCNT_A,	DBSC2_DBCMDCNT_D_PALL
56	write32 DBSC2_DBCMDCNT_A,	DBSC2_DBCMDCNT_D_REF
57	write32 DBSC2_DBCMDCNT_A,	DBSC2_DBCMDCNT_D_REF
58	write32 DBSC2_DBMRCNT_A,	DBSC2_DBMRCNT_D_MRS_2
59	wait_timer	WAIT_200US
60
61	write32 DBSC2_DBMRCNT_A,	DBSC2_DBMRCNT_D_EMRS1_2
62	write32 DBSC2_DBMRCNT_A,	DBSC2_DBMRCNT_D_EMRS1_1
63
64	write32 DBSC2_DBEN_A,		DBSC2_DBEN_D
65	write32 DBSC2_DBRFCNT1_A,	DBSC2_DBRFCNT1_D
66	write32 DBSC2_DBRFCNT2_A,	DBSC2_DBRFCNT2_D
67	write32 DBSC2_DBRFCNT0_A,	DBSC2_DBRFCNT0_D
68	wait_timer	WAIT_200US
69
70	/*------- GPIO -------*/
71	write16 PACR_A,	PACR_D
72	write16 PBCR_A,	PBCR_D
73	write16 PCCR_A,	PCCR_D
74	write16 PDCR_A,	PDCR_D
75	write16 PECR_A,	PECR_D
76	write16 PFCR_A,	PFCR_D
77	write16 PGCR_A,	PGCR_D
78	write16 PHCR_A,	PHCR_D
79	write16 PJCR_A,	PJCR_D
80	write16 PKCR_A,	PKCR_D
81	write16 PLCR_A,	PLCR_D
82	write16 PMCR_A,	PMCR_D
83	write16 PNCR_A,	PNCR_D
84	write16 PPCR_A,	PPCR_D
85	write16 PQCR_A,	PQCR_D
86	write16 PRCR_A,	PRCR_D
87
88	write8	PEPUPR_A,	PEPUPR_D
89	write8	PHPUPR_A,	PHPUPR_D
90	write8	PJPUPR_A,	PJPUPR_D
91	write8	PKPUPR_A,	PKPUPR_D
92	write8	PLPUPR_A,	PLPUPR_D
93	write8	PMPUPR_A,	PMPUPR_D
94	write8	PNPUPR_A,	PNPUPR_D
95	write16	PPUPR1_A,	PPUPR1_D
96	write16	PPUPR2_A,	PPUPR2_D
97	write16	P1MSELR_A,	P1MSELR_D
98	write16	P2MSELR_A,	P2MSELR_D
99
100	/*------- LBSC -------*/
101	write32	BCR_A,		BCR_D
102	write32	CS0BCR_A,	CS0BCR_D
103	write32	CS0WCR_A,	CS0WCR_D
104	write32	CS1BCR_A,	CS1BCR_D
105	write32	CS1WCR_A,	CS1WCR_D
106	write32	CS4BCR_A,	CS4BCR_D
107	write32	CS4WCR_A,	CS4WCR_D
108
109	mov.l	PASCR_A, r0
110	mov.l	@r0, r2
111	mov.l	PASCR_32BIT_MODE, r1
112	tst	r1, r2
113	bt	lbsc_29bit
114
115	write32	CS2BCR_A,	CS_USB_BCR_D
116	write32	CS2WCR_A,	CS_USB_WCR_D
117	write32	CS3BCR_A,	CS_SD_BCR_D
118	write32	CS3WCR_A,	CS_SD_WCR_D
119	write32	CS5BCR_A,	CS_I2C_BCR_D
120	write32	CS5WCR_A,	CS_I2C_WCR_D
121	write32	CS6BCR_A,	CS0BCR_D
122	write32	CS6WCR_A,	CS0WCR_D
123	bra	lbsc_end
124	 nop
125
126lbsc_29bit:
127	write32	CS5BCR_A,	CS_USB_BCR_D
128	write32	CS5WCR_A,	CS_USB_WCR_D
129	write32	CS6BCR_A,	CS_SD_BCR_D
130	write32	CS6WCR_A,	CS_SD_WCR_D
131
132lbsc_end:
133#if defined(CONFIG_SH_32BIT)
134	/*------- set PMB -------*/
135	write32	PASCR_A,	PASCR_29BIT_D
136	write32	MMUCR_A,	MMUCR_D
137
138	/*****************************************************************
139	 * ent	virt		phys		v	sz	c	wt
140	 * 0	0xa0000000	0x00000000	1	64M	0	0
141	 * 1	0xa4000000	0x04000000	1	16M	0	0
142	 * 2	0xa6000000	0x08000000	1	16M	0	0
143	 * 9	0x88000000	0x48000000	1	128M	1	1
144	 * 10	0x90000000	0x50000000	1	128M	1	1
145	 * 11	0x98000000	0x58000000	1	128M	1	1
146	 * 13	0xa8000000	0x48000000	1	128M	0	0
147	 * 14	0xb0000000	0x50000000	1	128M	0	0
148	 * 15	0xb8000000	0x58000000	1	128M	0	0
149	 */
150	write32	PMB_ADDR_FLASH_A,	PMB_ADDR_FLASH_D
151	write32	PMB_DATA_FLASH_A,	PMB_DATA_FLASH_D
152	write32	PMB_ADDR_CPLD_A,	PMB_ADDR_CPLD_D
153	write32	PMB_DATA_CPLD_A,	PMB_DATA_CPLD_D
154	write32	PMB_ADDR_USB_A,		PMB_ADDR_USB_D
155	write32	PMB_DATA_USB_A,		PMB_DATA_USB_D
156	write32	PMB_ADDR_DDR_C1_A,	PMB_ADDR_DDR_C1_D
157	write32	PMB_DATA_DDR_C1_A,	PMB_DATA_DDR_C1_D
158	write32	PMB_ADDR_DDR_C2_A,	PMB_ADDR_DDR_C2_D
159	write32	PMB_DATA_DDR_C2_A,	PMB_DATA_DDR_C2_D
160	write32	PMB_ADDR_DDR_C3_A,	PMB_ADDR_DDR_C3_D
161	write32	PMB_DATA_DDR_C3_A,	PMB_DATA_DDR_C3_D
162	write32	PMB_ADDR_DDR_N1_A,	PMB_ADDR_DDR_N1_D
163	write32	PMB_DATA_DDR_N1_A,	PMB_DATA_DDR_N1_D
164	write32	PMB_ADDR_DDR_N2_A,	PMB_ADDR_DDR_N2_D
165	write32	PMB_DATA_DDR_N2_A,	PMB_DATA_DDR_N2_D
166	write32	PMB_ADDR_DDR_N3_A,	PMB_ADDR_DDR_N3_D
167	write32	PMB_DATA_DDR_N3_A,	PMB_DATA_DDR_N3_D
168
169	write32	PASCR_A,	PASCR_INIT
170	mov.l	DUMMY_ADDR, r0
171	icbi	@r0
172#endif
173
174	write32	CCR_A,	CCR_D
175
176	rts
177	nop
178
179	.align 4
180
181/*------- LBSC -------*/
182MMSELR_A:	.long	0xfc400020
183#if defined(CONFIG_SH_32BIT)
184MMSELR_D:	.long	0xa5a50005
185#else
186MMSELR_D:	.long	0xa5a50002
187#endif
188
189/*------- DBSC2 -------*/
190#define DBSC2_BASE	0xfe800000
191DBSC2_DBSTATE_A:	.long	DBSC2_BASE + 0x0c
192DBSC2_DBEN_A:		.long	DBSC2_BASE + 0x10
193DBSC2_DBCMDCNT_A:	.long	DBSC2_BASE + 0x14
194DBSC2_DBCONF_A:		.long	DBSC2_BASE + 0x20
195DBSC2_DBTR0_A:		.long	DBSC2_BASE + 0x30
196DBSC2_DBTR1_A:		.long	DBSC2_BASE + 0x34
197DBSC2_DBTR2_A:		.long	DBSC2_BASE + 0x38
198DBSC2_DBRFCNT0_A:	.long	DBSC2_BASE + 0x40
199DBSC2_DBRFCNT1_A:	.long	DBSC2_BASE + 0x44
200DBSC2_DBRFCNT2_A:	.long	DBSC2_BASE + 0x48
201DBSC2_DBRFSTS_A:	.long	DBSC2_BASE + 0x4c
202DBSC2_DBFREQ_A:		.long	DBSC2_BASE + 0x50
203DBSC2_DBDICODTOCD_A:	.long	DBSC2_BASE + 0x54
204DBSC2_DBMRCNT_A:	.long	DBSC2_BASE + 0x60
205DDR_DUMMY_ACCESS_A:	.long	0x40000000
206
207DBSC2_DBCONF_D:		.long	0x00630002
208DBSC2_DBTR0_D:		.long	0x050b1f04
209DBSC2_DBTR1_D:		.long	0x00040204
210DBSC2_DBTR2_D:		.long	0x02100308
211DBSC2_DBFREQ_D1:	.long	0x00000000
212DBSC2_DBFREQ_D2:	.long	0x00000100
213DBSC2_DBDICODTOCD_D:	.long	0x000f0907
214
215DBSC2_DBCMDCNT_D_CKE_H:	.long	0x00000003
216DBSC2_DBCMDCNT_D_PALL:	.long	0x00000002
217DBSC2_DBCMDCNT_D_REF:	.long	0x00000004
218
219DBSC2_DBMRCNT_D_EMRS2:	.long	0x00020000
220DBSC2_DBMRCNT_D_EMRS3:	.long	0x00030000
221DBSC2_DBMRCNT_D_EMRS1_1:	.long	0x00010006
222DBSC2_DBMRCNT_D_EMRS1_2:	.long	0x00010386
223DBSC2_DBMRCNT_D_MRS_1:	.long	0x00000952
224DBSC2_DBMRCNT_D_MRS_2:	.long	0x00000852
225
226DBSC2_DBEN_D:		.long	0x00000001
227
228DBSC2_DBPDCNT0_D3:	.long	0x00000080
229DBSC2_DBRFCNT1_D:	.long	0x00000926
230DBSC2_DBRFCNT2_D:	.long	0x00fe00fe
231DBSC2_DBRFCNT0_D:	.long	0x00010000
232
233WAIT_200US:	.long	33333
234
235/*------- GPIO -------*/
236PACR_D:		.long	0x0000
237PBCR_D:		.long	0x0000
238PCCR_D:		.long	0x0000
239PDCR_D:		.long	0x0000
240PECR_D:		.long	0x0000
241PFCR_D:		.long	0x0000
242PGCR_D:		.long	0x0000
243PHCR_D:		.long	0x00c0
244PJCR_D:		.long	0xc3fc
245PKCR_D:		.long	0x03ff
246PLCR_D:		.long	0x0000
247PMCR_D:		.long	0xffff
248PNCR_D:		.long	0xf0c3
249PPCR_D:		.long	0x0000
250PQCR_D:		.long	0x0000
251PRCR_D:		.long	0x0000
252
253PEPUPR_D:	.long	0xff
254PHPUPR_D:	.long	0x00
255PJPUPR_D:	.long	0x00
256PKPUPR_D:	.long	0x00
257PLPUPR_D:	.long	0x00
258PMPUPR_D:	.long	0xfc
259PNPUPR_D:	.long	0x00
260PPUPR1_D:	.long	0xffbf
261PPUPR2_D:	.long	0xff00
262P1MSELR_D:	.long	0x3780
263P2MSELR_D:	.long	0x0000
264
265#define GPIO_BASE	0xffe70000
266PACR_A:		.long	GPIO_BASE + 0x00
267PBCR_A:		.long	GPIO_BASE + 0x02
268PCCR_A:		.long	GPIO_BASE + 0x04
269PDCR_A:		.long	GPIO_BASE + 0x06
270PECR_A:		.long	GPIO_BASE + 0x08
271PFCR_A:		.long	GPIO_BASE + 0x0a
272PGCR_A:		.long	GPIO_BASE + 0x0c
273PHCR_A:		.long	GPIO_BASE + 0x0e
274PJCR_A:		.long	GPIO_BASE + 0x10
275PKCR_A:		.long	GPIO_BASE + 0x12
276PLCR_A:		.long	GPIO_BASE + 0x14
277PMCR_A:		.long	GPIO_BASE + 0x16
278PNCR_A:		.long	GPIO_BASE + 0x18
279PPCR_A:		.long	GPIO_BASE + 0x1a
280PQCR_A:		.long	GPIO_BASE + 0x1c
281PRCR_A:		.long	GPIO_BASE + 0x1e
282PEPUPR_A:	.long	GPIO_BASE + 0x48
283PHPUPR_A:	.long	GPIO_BASE + 0x4e
284PJPUPR_A:	.long	GPIO_BASE + 0x50
285PKPUPR_A:	.long	GPIO_BASE + 0x52
286PLPUPR_A:	.long	GPIO_BASE + 0x54
287PMPUPR_A:	.long	GPIO_BASE + 0x56
288PNPUPR_A:	.long	GPIO_BASE + 0x58
289PPUPR1_A:	.long	GPIO_BASE + 0x60
290PPUPR2_A:	.long	GPIO_BASE + 0x62
291P1MSELR_A:	.long	GPIO_BASE + 0x80
292P2MSELR_A:	.long	GPIO_BASE + 0x82
293
294/*------- LBSC -------*/
295PASCR_A:		.long	0xff000070
296PASCR_32BIT_MODE:	.long	0x80000000	/* check booting mode */
297
298BCR_A:		.long	BCR
299CS0BCR_A:	.long	CS0BCR
300CS0WCR_A:	.long	CS0WCR
301CS1BCR_A:	.long	CS1BCR
302CS1WCR_A:	.long	CS1WCR
303CS2BCR_A:	.long	CS2BCR
304CS2WCR_A:	.long	CS2WCR
305CS3BCR_A:	.long	CS3BCR
306CS3WCR_A:	.long	CS3WCR
307CS4BCR_A:	.long	CS4BCR
308CS4WCR_A:	.long	CS4WCR
309CS5BCR_A:	.long	CS5BCR
310CS5WCR_A:	.long	CS5WCR
311CS6BCR_A:	.long	CS6BCR
312CS6WCR_A:	.long	CS6WCR
313
314BCR_D:		.long	0x80000003
315CS0BCR_D:	.long	0x22222340
316CS0WCR_D:	.long	0x00111118
317CS1BCR_D:	.long	0x11111100
318CS1WCR_D:	.long	0x33333303
319CS4BCR_D:	.long	0x11111300
320CS4WCR_D:	.long	0x00101012
321
322/* USB setting : 32bit mode = CS2, 29bit mode = CS5 */
323CS_USB_BCR_D:	.long	0x11111200
324CS_USB_WCR_D:	.long	0x00020004
325
326/* SD setting : 32bit mode = CS3, 29bit mode = CS6 */
327CS_SD_BCR_D:	.long	0x00000300
328CS_SD_WCR_D:	.long	0x00030108
329
330/* I2C setting : 32bit mode = CS5, 29bit mode = CS1(already setting) */
331CS_I2C_BCR_D:	.long	0x11111100
332CS_I2C_WCR_D:	.long	0x00000003
333
334#if defined(CONFIG_SH_32BIT)
335/*------- set PMB -------*/
336PMB_ADDR_FLASH_A:	.long	PMB_ADDR_BASE(0)
337PMB_ADDR_CPLD_A:	.long	PMB_ADDR_BASE(1)
338PMB_ADDR_USB_A:		.long	PMB_ADDR_BASE(2)
339PMB_ADDR_DDR_C1_A:	.long	PMB_ADDR_BASE(9)
340PMB_ADDR_DDR_C2_A:	.long	PMB_ADDR_BASE(10)
341PMB_ADDR_DDR_C3_A:	.long	PMB_ADDR_BASE(11)
342PMB_ADDR_DDR_N1_A:	.long	PMB_ADDR_BASE(13)
343PMB_ADDR_DDR_N2_A:	.long	PMB_ADDR_BASE(14)
344PMB_ADDR_DDR_N3_A:	.long	PMB_ADDR_BASE(15)
345
346PMB_ADDR_FLASH_D:	.long	mk_pmb_addr_val(0xa0)
347PMB_ADDR_CPLD_D:	.long	mk_pmb_addr_val(0xa4)
348PMB_ADDR_USB_D:		.long	mk_pmb_addr_val(0xa6)
349PMB_ADDR_DDR_C1_D:	.long	mk_pmb_addr_val(0x88)
350PMB_ADDR_DDR_C2_D:	.long	mk_pmb_addr_val(0x90)
351PMB_ADDR_DDR_C3_D:	.long	mk_pmb_addr_val(0x98)
352PMB_ADDR_DDR_N1_D:	.long	mk_pmb_addr_val(0xa8)
353PMB_ADDR_DDR_N2_D:	.long	mk_pmb_addr_val(0xb0)
354PMB_ADDR_DDR_N3_D:	.long	mk_pmb_addr_val(0xb8)
355
356PMB_DATA_FLASH_A:	.long	PMB_DATA_BASE(0)
357PMB_DATA_CPLD_A:	.long	PMB_DATA_BASE(1)
358PMB_DATA_USB_A:		.long	PMB_DATA_BASE(2)
359PMB_DATA_DDR_C1_A:	.long	PMB_DATA_BASE(9)
360PMB_DATA_DDR_C2_A:	.long	PMB_DATA_BASE(10)
361PMB_DATA_DDR_C3_A:	.long	PMB_DATA_BASE(11)
362PMB_DATA_DDR_N1_A:	.long	PMB_DATA_BASE(13)
363PMB_DATA_DDR_N2_A:	.long	PMB_DATA_BASE(14)
364PMB_DATA_DDR_N3_A:	.long	PMB_DATA_BASE(15)
365
366/*						ppn   ub v s1 s0  c  wt */
367PMB_DATA_FLASH_D:	.long	mk_pmb_data_val(0x00, 1, 1, 0, 1, 0, 1)
368PMB_DATA_CPLD_D:	.long	mk_pmb_data_val(0x04, 1, 1, 0, 0, 0, 1)
369PMB_DATA_USB_D:		.long	mk_pmb_data_val(0x08, 1, 1, 0, 0, 0, 1)
370PMB_DATA_DDR_C1_D:	.long	mk_pmb_data_val(0x48, 0, 1, 1, 0, 1, 1)
371PMB_DATA_DDR_C2_D:	.long	mk_pmb_data_val(0x50, 0, 1, 1, 0, 1, 1)
372PMB_DATA_DDR_C3_D:	.long	mk_pmb_data_val(0x58, 0, 1, 1, 0, 1, 1)
373PMB_DATA_DDR_N1_D:	.long	mk_pmb_data_val(0x48, 1, 1, 1, 0, 0, 1)
374PMB_DATA_DDR_N2_D:	.long	mk_pmb_data_val(0x50, 1, 1, 1, 0, 0, 1)
375PMB_DATA_DDR_N3_D:	.long	mk_pmb_data_val(0x58, 1, 1, 1, 0, 0, 1)
376
377DUMMY_ADDR:	.long	0xa0000000
378PASCR_29BIT_D:	.long	0x00000000
379PASCR_INIT:	.long	0x80000080	/* check booting mode */
380MMUCR_A:	.long	0xff000010
381MMUCR_D:	.long	0x00000004	/* clear ITLB */
382#endif	/* CONFIG_SH_32BIT */
383
384CCR_A:		.long	0xff00001c
385CCR_D:		.long	0x0000090b
386