1/* SPDX-License-Identifier: GPL-2.0+ */
2/*
3 * Copyright (C) 2008 Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
4 */
5#include <config.h>
6#include <asm/processor.h>
7#include <asm/macro.h>
8
9#include <asm/processor.h>
10
11	.global	lowlevel_init
12
13	.text
14	.align	2
15
16lowlevel_init:
17	wait_timer	WAIT_200US
18	wait_timer	WAIT_200US
19
20	/*------- LBSC -------*/
21	write32 MMSELR_A,	MMSELR_D
22
23	/*------- DBSC2 -------*/
24	write32 DBSC2_DBCONF_A,	DBSC2_DBCONF_D
25	write32 DBSC2_DBTR0_A,	DBSC2_DBTR0_D
26	write32 DBSC2_DBTR1_A,	DBSC2_DBTR1_D
27	write32 DBSC2_DBTR2_A,	DBSC2_DBTR2_D
28	write32 DBSC2_DBFREQ_A,	DBSC2_DBFREQ_D1
29	write32 DBSC2_DBFREQ_A,	DBSC2_DBFREQ_D2
30	wait_timer	WAIT_200US
31
32	write32 DBSC2_DBDICODTOCD_A,	DBSC2_DBDICODTOCD_D
33	write32 DBSC2_DBCMDCNT_A,	DBSC2_DBCMDCNT_D_CKE_H
34	wait_timer	WAIT_200US
35	write32 DBSC2_DBCMDCNT_A,	DBSC2_DBCMDCNT_D_PALL
36	write32 DBSC2_DBMRCNT_A,	DBSC2_DBMRCNT_D_EMRS2
37	write32 DBSC2_DBMRCNT_A,	DBSC2_DBMRCNT_D_EMRS3
38	write32 DBSC2_DBMRCNT_A,	DBSC2_DBMRCNT_D_EMRS1_1
39	write32 DBSC2_DBMRCNT_A,	DBSC2_DBMRCNT_D_MRS_1
40	write32 DBSC2_DBCMDCNT_A,	DBSC2_DBCMDCNT_D_PALL
41	write32 DBSC2_DBCMDCNT_A,	DBSC2_DBCMDCNT_D_REF
42	write32 DBSC2_DBCMDCNT_A,	DBSC2_DBCMDCNT_D_REF
43	write32 DBSC2_DBMRCNT_A,	DBSC2_DBMRCNT_D_MRS_2
44	wait_timer	WAIT_200US
45
46	write32 DBSC2_DBMRCNT_A,	DBSC2_DBMRCNT_D_EMRS1_2
47	write32 DBSC2_DBMRCNT_A,	DBSC2_DBMRCNT_D_EMRS1_1
48
49	write32 DBSC2_DBEN_A,		DBSC2_DBEN_D
50	write32 DBSC2_DBRFCNT1_A,	DBSC2_DBRFCNT1_D
51	write32 DBSC2_DBRFCNT2_A,	DBSC2_DBRFCNT2_D
52	write32 DBSC2_DBRFCNT0_A,	DBSC2_DBRFCNT0_D
53	wait_timer	WAIT_200US
54
55	/*------- GPIO -------*/
56	write16 PACR_A,	PXCR_D
57	write16 PBCR_A,	PXCR_D
58	write16 PCCR_A,	PXCR_D
59	write16 PDCR_A,	PXCR_D
60	write16 PECR_A,	PXCR_D
61	write16 PFCR_A,	PXCR_D
62	write16 PGCR_A,	PXCR_D
63	write16 PHCR_A,	PHCR_D
64	write16 PJCR_A,	PJCR_D
65	write16 PKCR_A,	PKCR_D
66	write16 PLCR_A,	PXCR_D
67	write16 PMCR_A,	PMCR_D
68	write16 PNCR_A,	PNCR_D
69	write16 PPCR_A,	PXCR_D
70	write16 PQCR_A,	PXCR_D
71	write16 PRCR_A,	PXCR_D
72
73	write8	PEPUPR_A,	PEPUPR_D
74	write8	PHPUPR_A,	PHPUPR_D
75	write8	PJPUPR_A,	PJPUPR_D
76	write8	PKPUPR_A,	PKPUPR_D
77	write8	PLPUPR_A,	PLPUPR_D
78	write8	PMPUPR_A,	PMPUPR_D
79	write8	PNPUPR_A,	PNPUPR_D
80	write16	PPUPR1_A,	PPUPR1_D
81	write16	PPUPR2_A,	PPUPR2_D
82	write16	P1MSELR_A,	P1MSELR_D
83	write16	P2MSELR_A,	P2MSELR_D
84
85	/*------- LBSC -------*/
86	write32	BCR_A,		BCR_D
87	write32	CS0BCR_A,	CS0BCR_D
88	write32	CS0WCR_A,	CS0WCR_D
89	write32	CS1BCR_A,	CS1BCR_D
90	write32	CS1WCR_A,	CS1WCR_D
91	write32	CS4BCR_A,	CS4BCR_D
92	write32	CS4WCR_A,	CS4WCR_D
93
94	mov.l	PASCR_A, r0
95	mov.l	@r0, r2
96	mov.l	PASCR_32BIT_MODE, r1
97	tst	r1, r2
98	bt	lbsc_29bit
99
100	write32	CS2BCR_A,	CS_USB_BCR_D
101	write32	CS2WCR_A,	CS_USB_WCR_D
102	write32	CS3BCR_A,	CS_SD_BCR_D
103	write32	CS3WCR_A,	CS_SD_WCR_D
104	write32	CS5BCR_A,	CS_I2C_BCR_D
105	write32	CS5WCR_A,	CS_I2C_WCR_D
106	write32	CS6BCR_A,	CS0BCR_D
107	write32	CS6WCR_A,	CS0WCR_D
108	bra	lbsc_end
109	 nop
110
111lbsc_29bit:
112	write32	CS5BCR_A,	CS_USB_BCR_D
113	write32	CS5WCR_A,	CS_USB_WCR_D
114	write32	CS6BCR_A,	CS_SD_BCR_D
115	write32	CS6WCR_A,	CS_SD_WCR_D
116
117lbsc_end:
118#if defined(CONFIG_SH_32BIT)
119	/*------- set PMB -------*/
120	write32	PASCR_A,	PASCR_29BIT_D
121	write32	MMUCR_A,	MMUCR_D
122
123	/*****************************************************************
124	 * ent	virt		phys		v	sz	c	wt
125	 * 0	0xa0000000	0x00000000	1	64M	0	0
126	 * 1	0xa4000000	0x04000000	1	16M	0	0
127	 * 2	0xa6000000	0x08000000	1	16M	0	0
128	 * 9	0x88000000	0x48000000	1	128M	1	1
129	 * 10	0x90000000	0x50000000	1	128M	1	1
130	 * 11	0x98000000	0x58000000	1	128M	1	1
131	 * 13	0xa8000000	0x48000000	1	128M	0	0
132	 * 14	0xb0000000	0x50000000	1	128M	0	0
133	 * 15	0xb8000000	0x58000000	1	128M	0	0
134	 */
135	write32	PMB_ADDR_FLASH_A,	PMB_ADDR_FLASH_D
136	write32	PMB_DATA_FLASH_A,	PMB_DATA_FLASH_D
137	write32	PMB_ADDR_CPLD_A,	PMB_ADDR_CPLD_D
138	write32	PMB_DATA_CPLD_A,	PMB_DATA_CPLD_D
139	write32	PMB_ADDR_USB_A,		PMB_ADDR_USB_D
140	write32	PMB_DATA_USB_A,		PMB_DATA_USB_D
141	write32	PMB_ADDR_DDR_C1_A,	PMB_ADDR_DDR_C1_D
142	write32	PMB_DATA_DDR_C1_A,	PMB_DATA_DDR_C1_D
143	write32	PMB_ADDR_DDR_C2_A,	PMB_ADDR_DDR_C2_D
144	write32	PMB_DATA_DDR_C2_A,	PMB_DATA_DDR_C2_D
145	write32	PMB_ADDR_DDR_C3_A,	PMB_ADDR_DDR_C3_D
146	write32	PMB_DATA_DDR_C3_A,	PMB_DATA_DDR_C3_D
147	write32	PMB_ADDR_DDR_N1_A,	PMB_ADDR_DDR_N1_D
148	write32	PMB_DATA_DDR_N1_A,	PMB_DATA_DDR_N1_D
149	write32	PMB_ADDR_DDR_N2_A,	PMB_ADDR_DDR_N2_D
150	write32	PMB_DATA_DDR_N2_A,	PMB_DATA_DDR_N2_D
151	write32	PMB_ADDR_DDR_N3_A,	PMB_ADDR_DDR_N3_D
152	write32	PMB_DATA_DDR_N3_A,	PMB_DATA_DDR_N3_D
153
154	write32	PASCR_A,	PASCR_INIT
155	mov.l	DUMMY_ADDR, r0
156	icbi	@r0
157#endif
158
159	write32	CCR_A,	CCR_D
160
161	rts
162	nop
163
164	.align 4
165
166/*------- GPIO -------*/
167/* P{A,B C,D,E,F,G,L,P,Q,R}CR_D */
168PXCR_D:		.word	0x0000
169
170PHCR_D:		.word	0x00c0
171PJCR_D:		.word	0xc3fc
172PKCR_D:		.word	0x03ff
173PMCR_D:		.word	0xffff
174PNCR_D:		.word	0xf0c3
175
176PEPUPR_D:	.long	0xff
177PHPUPR_D:	.long	0x00
178PJPUPR_D:	.long	0x00
179PKPUPR_D:	.long	0x00
180PLPUPR_D:	.long	0x00
181PMPUPR_D:	.long	0xfc
182PNPUPR_D:	.long	0x00
183PPUPR1_D:	.word	0xffbf
184PPUPR2_D:	.word	0xff00
185P1MSELR_D:	.word	0x3780
186P2MSELR_D:	.word	0x0000
187
188#define GPIO_BASE	0xffe70000
189PACR_A:		.long	GPIO_BASE + 0x00
190PBCR_A:		.long	GPIO_BASE + 0x02
191PCCR_A:		.long	GPIO_BASE + 0x04
192PDCR_A:		.long	GPIO_BASE + 0x06
193PECR_A:		.long	GPIO_BASE + 0x08
194PFCR_A:		.long	GPIO_BASE + 0x0a
195PGCR_A:		.long	GPIO_BASE + 0x0c
196PHCR_A:		.long	GPIO_BASE + 0x0e
197PJCR_A:		.long	GPIO_BASE + 0x10
198PKCR_A:		.long	GPIO_BASE + 0x12
199PLCR_A:		.long	GPIO_BASE + 0x14
200PMCR_A:		.long	GPIO_BASE + 0x16
201PNCR_A:		.long	GPIO_BASE + 0x18
202PPCR_A:		.long	GPIO_BASE + 0x1a
203PQCR_A:		.long	GPIO_BASE + 0x1c
204PRCR_A:		.long	GPIO_BASE + 0x1e
205PEPUPR_A:	.long	GPIO_BASE + 0x48
206PHPUPR_A:	.long	GPIO_BASE + 0x4e
207PJPUPR_A:	.long	GPIO_BASE + 0x50
208PKPUPR_A:	.long	GPIO_BASE + 0x52
209PLPUPR_A:	.long	GPIO_BASE + 0x54
210PMPUPR_A:	.long	GPIO_BASE + 0x56
211PNPUPR_A:	.long	GPIO_BASE + 0x58
212PPUPR1_A:	.long	GPIO_BASE + 0x60
213PPUPR2_A:	.long	GPIO_BASE + 0x62
214P1MSELR_A:	.long	GPIO_BASE + 0x80
215P2MSELR_A:	.long	GPIO_BASE + 0x82
216
217MMSELR_A:      .long   0xfc400020
218#if defined(CONFIG_SH_32BIT)
219MMSELR_D:      .long   0xa5a50005
220#else
221MMSELR_D:      .long   0xa5a50002
222#endif
223
224/*------- DBSC2 -------*/
225#define DBSC2_BASE	0xfe800000
226DBSC2_DBSTATE_A:	.long	DBSC2_BASE + 0x0c
227DBSC2_DBEN_A:		.long	DBSC2_BASE + 0x10
228DBSC2_DBCMDCNT_A:	.long	DBSC2_BASE + 0x14
229DBSC2_DBCONF_A:		.long	DBSC2_BASE + 0x20
230DBSC2_DBTR0_A:		.long	DBSC2_BASE + 0x30
231DBSC2_DBTR1_A:		.long	DBSC2_BASE + 0x34
232DBSC2_DBTR2_A:		.long	DBSC2_BASE + 0x38
233DBSC2_DBRFCNT0_A:	.long	DBSC2_BASE + 0x40
234DBSC2_DBRFCNT1_A:	.long	DBSC2_BASE + 0x44
235DBSC2_DBRFCNT2_A:	.long	DBSC2_BASE + 0x48
236DBSC2_DBRFSTS_A:	.long	DBSC2_BASE + 0x4c
237DBSC2_DBFREQ_A:		.long	DBSC2_BASE + 0x50
238DBSC2_DBDICODTOCD_A:.long	DBSC2_BASE + 0x54
239DBSC2_DBMRCNT_A:	.long	DBSC2_BASE + 0x60
240DDR_DUMMY_ACCESS_A:	.long	0x40000000
241
242DBSC2_DBCONF_D:		.long	0x00630002
243DBSC2_DBTR0_D:		.long	0x050b1f04
244DBSC2_DBTR1_D:		.long	0x00040204
245DBSC2_DBTR2_D:		.long	0x02100308
246DBSC2_DBFREQ_D1:	.long	0x00000000
247DBSC2_DBFREQ_D2:	.long	0x00000100
248DBSC2_DBDICODTOCD_D:.long	0x000f0907
249
250DBSC2_DBCMDCNT_D_CKE_H:	.long	0x00000003
251DBSC2_DBCMDCNT_D_PALL:	.long	0x00000002
252DBSC2_DBCMDCNT_D_REF:	.long	0x00000004
253
254DBSC2_DBMRCNT_D_EMRS2:	.long	0x00020000
255DBSC2_DBMRCNT_D_EMRS3:	.long	0x00030000
256DBSC2_DBMRCNT_D_EMRS1_1:	.long	0x00010006
257DBSC2_DBMRCNT_D_EMRS1_2:	.long	0x00010386
258DBSC2_DBMRCNT_D_MRS_1:	.long	0x00000952
259DBSC2_DBMRCNT_D_MRS_2:	.long	0x00000852
260
261DBSC2_DBEN_D:		.long	0x00000001
262
263DBSC2_DBPDCNT0_D3:	.long	0x00000080
264DBSC2_DBRFCNT1_D:	.long	0x00000926
265DBSC2_DBRFCNT2_D:	.long	0x00fe00fe
266DBSC2_DBRFCNT0_D:	.long	0x00010000
267
268WAIT_200US:    .long   33333
269
270/*------- LBSC -------*/
271PASCR_A:		.long	0xff000070
272PASCR_32BIT_MODE:	.long	0x80000000	/* check booting mode */
273
274BCR_A:		.long	BCR
275CS0BCR_A:	.long	CS0BCR
276CS0WCR_A:	.long	CS0WCR
277CS1BCR_A:	.long	CS1BCR
278CS1WCR_A:	.long	CS1WCR
279CS2BCR_A:	.long	CS2BCR
280CS2WCR_A:	.long	CS2WCR
281CS3BCR_A:	.long	CS3BCR
282CS3WCR_A:	.long	CS3WCR
283CS4BCR_A:	.long	CS4BCR
284CS4WCR_A:	.long	CS4WCR
285CS5BCR_A:	.long	CS5BCR
286CS5WCR_A:	.long	CS5WCR
287CS6BCR_A:	.long	CS6BCR
288CS6WCR_A:	.long	CS6WCR
289
290BCR_D:		.long	0x80000003
291CS0BCR_D:	.long	0x22222340
292CS0WCR_D:	.long	0x00111118
293CS1BCR_D:	.long	0x11111100
294CS1WCR_D:	.long	0x33333303
295CS4BCR_D:	.long	0x11111300
296CS4WCR_D:	.long	0x00101012
297
298/* USB setting : 32bit mode = CS2, 29bit mode = CS5 */
299CS_USB_BCR_D:	.long	0x11111200
300CS_USB_WCR_D:	.long	0x00020005
301
302/* SD setting : 32bit mode = CS3, 29bit mode = CS6 */
303CS_SD_BCR_D:	.long	0x00000300
304CS_SD_WCR_D:	.long	0x00030108
305
306/* I2C setting : 32bit mode = CS5, 29bit mode = CS1(already setting) */
307CS_I2C_BCR_D:	.long	0x11111100
308CS_I2C_WCR_D:	.long	0x00000003
309
310#if defined(CONFIG_SH_32BIT)
311/*------- set PMB -------*/
312PMB_ADDR_FLASH_A:	.long	PMB_ADDR_BASE(0)
313PMB_ADDR_CPLD_A:	.long	PMB_ADDR_BASE(1)
314PMB_ADDR_USB_A:		.long	PMB_ADDR_BASE(2)
315PMB_ADDR_DDR_C1_A:	.long	PMB_ADDR_BASE(9)
316PMB_ADDR_DDR_C2_A:	.long	PMB_ADDR_BASE(10)
317PMB_ADDR_DDR_C3_A:	.long	PMB_ADDR_BASE(11)
318PMB_ADDR_DDR_N1_A:	.long	PMB_ADDR_BASE(13)
319PMB_ADDR_DDR_N2_A:	.long	PMB_ADDR_BASE(14)
320PMB_ADDR_DDR_N3_A:	.long	PMB_ADDR_BASE(15)
321
322PMB_ADDR_FLASH_D:	.long	mk_pmb_addr_val(0xa0)
323PMB_ADDR_CPLD_D:	.long	mk_pmb_addr_val(0xa4)
324PMB_ADDR_USB_D:		.long	mk_pmb_addr_val(0xa6)
325PMB_ADDR_DDR_C1_D:	.long	mk_pmb_addr_val(0x88)
326PMB_ADDR_DDR_C2_D:	.long	mk_pmb_addr_val(0x90)
327PMB_ADDR_DDR_C3_D:	.long	mk_pmb_addr_val(0x98)
328PMB_ADDR_DDR_N1_D:	.long	mk_pmb_addr_val(0xa8)
329PMB_ADDR_DDR_N2_D:	.long	mk_pmb_addr_val(0xb0)
330PMB_ADDR_DDR_N3_D:	.long	mk_pmb_addr_val(0xb8)
331
332PMB_DATA_FLASH_A:	.long	PMB_DATA_BASE(0)
333PMB_DATA_CPLD_A:	.long	PMB_DATA_BASE(1)
334PMB_DATA_USB_A:		.long	PMB_DATA_BASE(2)
335PMB_DATA_DDR_C1_A:	.long	PMB_DATA_BASE(9)
336PMB_DATA_DDR_C2_A:	.long	PMB_DATA_BASE(10)
337PMB_DATA_DDR_C3_A:	.long	PMB_DATA_BASE(11)
338PMB_DATA_DDR_N1_A:	.long	PMB_DATA_BASE(13)
339PMB_DATA_DDR_N2_A:	.long	PMB_DATA_BASE(14)
340PMB_DATA_DDR_N3_A:	.long	PMB_DATA_BASE(15)
341
342/*						ppn   ub v s1 s0  c  wt */
343PMB_DATA_FLASH_D:	.long	mk_pmb_data_val(0x00, 1, 1, 0, 1, 0, 1)
344PMB_DATA_CPLD_D:	.long	mk_pmb_data_val(0x04, 1, 1, 0, 0, 0, 1)
345PMB_DATA_USB_D:		.long	mk_pmb_data_val(0x08, 1, 1, 0, 0, 0, 1)
346PMB_DATA_DDR_C1_D:	.long	mk_pmb_data_val(0x48, 0, 1, 1, 0, 1, 1)
347PMB_DATA_DDR_C2_D:	.long	mk_pmb_data_val(0x50, 0, 1, 1, 0, 1, 1)
348PMB_DATA_DDR_C3_D:	.long	mk_pmb_data_val(0x58, 0, 1, 1, 0, 1, 1)
349PMB_DATA_DDR_N1_D:	.long	mk_pmb_data_val(0x48, 1, 1, 1, 0, 0, 1)
350PMB_DATA_DDR_N2_D:	.long	mk_pmb_data_val(0x50, 1, 1, 1, 0, 0, 1)
351PMB_DATA_DDR_N3_D:	.long	mk_pmb_data_val(0x58, 1, 1, 1, 0, 0, 1)
352
353DUMMY_ADDR:	.long	0xa0000000
354PASCR_29BIT_D:	.long	0x00000000
355PASCR_INIT:	.long	0x80000080	/* check booting mode */
356MMUCR_A:	.long	0xff000010
357MMUCR_D:	.long	0x00000004	/* clear ITLB */
358#endif	/* CONFIG_SH_32BIT */
359
360CCR_A:		.long	0xff00001c
361CCR_D:		.long	0x0000090b
362